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1; RUN: llc -mtriple=amdgcn -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s3; RUN: llc -mtriple=amdgcn -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s4 5declare i32 @llvm.amdgcn.workitem.id.x() #06declare void @llvm.amdgcn.s.barrier() #17 8; Function Attrs: nounwind9; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop:10; CHECK: BB0_1:11; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],12; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]]13; SI-DAG: v_add_i32_e32 [[VADDR8:v[0-9]+]], vcc, 8, [[VADDR]]14; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR8]]15; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]]16; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]]17; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, 0x88, [[VADDR]]18; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x88]]19; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, 0x100, [[VADDR]]20; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]21 22; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:223; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:3424; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:25625; CHECK: s_endpgm26define amdgpu_kernel void @signed_ds_offset_addressing_loop(ptr addrspace(1) noalias nocapture %out, ptr addrspace(3) noalias nocapture readonly %lptr, i32 %n) #2 {27entry:28 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #029 %mul = shl nsw i32 %x.i, 130 br label %for.body31 32for.body: ; preds = %for.body, %entry33 %sum.03 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]34 %offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ]35 %k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]36 tail call void @llvm.amdgcn.s.barrier() #137 %arrayidx = getelementptr inbounds float, ptr addrspace(3) %lptr, i32 %offset.0238 %tmp = load float, ptr addrspace(3) %arrayidx, align 439 %add1 = add nsw i32 %offset.02, 240 %arrayidx2 = getelementptr inbounds float, ptr addrspace(3) %lptr, i32 %add141 %tmp1 = load float, ptr addrspace(3) %arrayidx2, align 442 %add3 = add nsw i32 %offset.02, 3243 %arrayidx4 = getelementptr inbounds float, ptr addrspace(3) %lptr, i32 %add344 %tmp2 = load float, ptr addrspace(3) %arrayidx4, align 445 %add5 = add nsw i32 %offset.02, 3446 %arrayidx6 = getelementptr inbounds float, ptr addrspace(3) %lptr, i32 %add547 %tmp3 = load float, ptr addrspace(3) %arrayidx6, align 448 %add7 = add nsw i32 %offset.02, 6449 %arrayidx8 = getelementptr inbounds float, ptr addrspace(3) %lptr, i32 %add750 %tmp4 = load float, ptr addrspace(3) %arrayidx8, align 451 %add9 = fadd float %tmp, %tmp152 %add10 = fadd float %add9, %tmp253 %add11 = fadd float %add10, %tmp354 %add12 = fadd float %add11, %tmp455 %add13 = fadd float %sum.03, %add1256 %inc = add nsw i32 %k.01, 157 %add14 = add nsw i32 %offset.02, 9758 %exitcond = icmp eq i32 %inc, 859 br i1 %exitcond, label %for.end, label %for.body60 61for.end: ; preds = %for.body62 %tmp5 = sext i32 %x.i to i6463 %arrayidx15 = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tmp564 store float %add13, ptr addrspace(1) %arrayidx15, align 465 ret void66}67 68attributes #0 = { nounwind readnone }69attributes #1 = { convergent nounwind }70attributes #2 = { nounwind }71