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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire < %s | FileCheck -enable-var-scope --check-prefix=CI %s3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s4; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s5; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s6; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s7 8declare i32 @llvm.amdgcn.workitem.id.x() #09 10@lds.obj = addrspace(3) global [256 x i32] poison, align 411 12define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 {13; CI-LABEL: write_ds_sub0_offset0_global:14; CI: ; %bb.0: ; %entry15; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v016; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v017; CI-NEXT: v_mov_b32_e32 v1, 0x7b18; CI-NEXT: s_mov_b32 m0, -119; CI-NEXT: ds_write_b32 v0, v1 offset:1220; CI-NEXT: s_endpgm21;22; GFX9-LABEL: write_ds_sub0_offset0_global:23; GFX9: ; %bb.0: ; %entry24; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v025; GFX9-NEXT: v_sub_u32_e32 v0, 0, v026; GFX9-NEXT: v_mov_b32_e32 v1, 0x7b27; GFX9-NEXT: ds_write_b32 v0, v1 offset:1228; GFX9-NEXT: s_endpgm29;30; GFX10-LABEL: write_ds_sub0_offset0_global:31; GFX10: ; %bb.0: ; %entry32; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v033; GFX10-NEXT: v_mov_b32_e32 v1, 0x7b34; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v035; GFX10-NEXT: ds_write_b32 v0, v1 offset:1236; GFX10-NEXT: s_endpgm37;38; GFX11-LABEL: write_ds_sub0_offset0_global:39; GFX11: ; %bb.0: ; %entry40; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v041; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)42; GFX11-NEXT: v_dual_mov_b32 v1, 0x7b :: v_dual_lshlrev_b32 v0, 2, v043; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0, v044; GFX11-NEXT: ds_store_b32 v0, v1 offset:1245; GFX11-NEXT: s_endpgm46entry:47 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #148 %sub1 = sub i32 0, %x.i49 %tmp0 = getelementptr [256 x i32], ptr addrspace(3) @lds.obj, i32 0, i32 %sub150 %arrayidx = getelementptr inbounds i32, ptr addrspace(3) %tmp0, i32 351 store i32 123, ptr addrspace(3) %arrayidx52 ret void53}54 55define amdgpu_kernel void @write_ds_sub0_offset0_global_clamp_bit(float %dummy.val) #0 {56; CI-LABEL: write_ds_sub0_offset0_global_clamp_bit:57; CI: ; %bb.0: ; %entry58; CI-NEXT: s_load_dword s0, s[4:5], 0x059; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v060; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v061; CI-NEXT: s_mov_b64 vcc, 062; CI-NEXT: s_waitcnt lgkmcnt(0)63; CI-NEXT: v_mov_b32_e32 v1, s064; CI-NEXT: v_mov_b32_e32 v2, 0x7b65; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v166; CI-NEXT: s_mov_b32 m0, -167; CI-NEXT: s_mov_b64 s[0:1], 068; CI-NEXT: s_mov_b32 s3, 0xf00069; CI-NEXT: s_mov_b32 s2, -170; CI-NEXT: ds_write_b32 v0, v2 offset:1271; CI-NEXT: buffer_store_dword v1, off, s[0:3], 072; CI-NEXT: s_waitcnt vmcnt(0)73; CI-NEXT: s_endpgm74;75; GFX9-LABEL: write_ds_sub0_offset0_global_clamp_bit:76; GFX9: ; %bb.0: ; %entry77; GFX9-NEXT: s_load_dword s0, s[4:5], 0x078; GFX9-NEXT: s_mov_b64 vcc, 079; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v080; GFX9-NEXT: v_sub_u32_e32 v3, 0, v081; GFX9-NEXT: v_mov_b32_e32 v4, 0x7b82; GFX9-NEXT: s_waitcnt lgkmcnt(0)83; GFX9-NEXT: v_mov_b32_e32 v1, s084; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v185; GFX9-NEXT: v_mov_b32_e32 v0, 086; GFX9-NEXT: v_mov_b32_e32 v1, 087; GFX9-NEXT: ds_write_b32 v3, v4 offset:1288; GFX9-NEXT: global_store_dword v[0:1], v2, off89; GFX9-NEXT: s_waitcnt vmcnt(0)90; GFX9-NEXT: s_endpgm91;92; GFX10-LABEL: write_ds_sub0_offset0_global_clamp_bit:93; GFX10: ; %bb.0: ; %entry94; GFX10-NEXT: s_load_dword s0, s[4:5], 0x095; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v096; GFX10-NEXT: s_mov_b32 vcc_lo, 097; GFX10-NEXT: v_mov_b32_e32 v3, 0x7b98; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0, v099; GFX10-NEXT: v_mov_b32_e32 v0, 0100; GFX10-NEXT: v_mov_b32_e32 v1, 0101; GFX10-NEXT: ds_write_b32 v2, v3 offset:12102; GFX10-NEXT: s_waitcnt lgkmcnt(0)103; GFX10-NEXT: v_div_fmas_f32 v4, s0, s0, s0104; GFX10-NEXT: global_store_dword v[0:1], v4, off105; GFX10-NEXT: s_waitcnt_vscnt null, 0x0106; GFX10-NEXT: s_endpgm107;108; GFX11-LABEL: write_ds_sub0_offset0_global_clamp_bit:109; GFX11: ; %bb.0: ; %entry110; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0111; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0112; GFX11-NEXT: s_mov_b32 vcc_lo, 0113; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)114; GFX11-NEXT: v_dual_mov_b32 v3, 0x7b :: v_dual_lshlrev_b32 v0, 2, v0115; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0, v0116; GFX11-NEXT: v_mov_b32_e32 v0, 0117; GFX11-NEXT: v_mov_b32_e32 v1, 0118; GFX11-NEXT: ds_store_b32 v2, v3 offset:12119; GFX11-NEXT: s_waitcnt lgkmcnt(0)120; GFX11-NEXT: v_div_fmas_f32 v4, s0, s0, s0121; GFX11-NEXT: global_store_b32 v[0:1], v4, off dlc122; GFX11-NEXT: s_waitcnt_vscnt null, 0x0123; GFX11-NEXT: s_endpgm124entry:125 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1126 %sub1 = sub i32 0, %x.i127 %tmp0 = getelementptr [256 x i32], ptr addrspace(3) @lds.obj, i32 0, i32 %sub1128 %arrayidx = getelementptr inbounds i32, ptr addrspace(3) %tmp0, i32 3129 store i32 123, ptr addrspace(3) %arrayidx130 %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)131 store volatile float %fmas, ptr addrspace(1) null132 ret void133}134 135define amdgpu_kernel void @write_ds_sub_max_offset_global_clamp_bit(float %dummy.val) #0 {136; CI-LABEL: write_ds_sub_max_offset_global_clamp_bit:137; CI: ; %bb.0:138; CI-NEXT: s_load_dword s0, s[4:5], 0x0139; CI-NEXT: s_mov_b64 vcc, 0140; CI-NEXT: v_mov_b32_e32 v1, 0x7b141; CI-NEXT: v_mov_b32_e32 v2, 0142; CI-NEXT: s_mov_b32 m0, -1143; CI-NEXT: s_waitcnt lgkmcnt(0)144; CI-NEXT: v_mov_b32_e32 v0, s0145; CI-NEXT: v_div_fmas_f32 v0, v0, v0, v0146; CI-NEXT: s_mov_b64 s[0:1], 0147; CI-NEXT: s_mov_b32 s3, 0xf000148; CI-NEXT: s_mov_b32 s2, -1149; CI-NEXT: ds_write_b32 v2, v1150; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0151; CI-NEXT: s_waitcnt vmcnt(0)152; CI-NEXT: s_endpgm153;154; GFX9-LABEL: write_ds_sub_max_offset_global_clamp_bit:155; GFX9: ; %bb.0:156; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0157; GFX9-NEXT: s_mov_b64 vcc, 0158; GFX9-NEXT: v_mov_b32_e32 v3, 0x7b159; GFX9-NEXT: v_mov_b32_e32 v4, 0160; GFX9-NEXT: ds_write_b32 v4, v3161; GFX9-NEXT: s_waitcnt lgkmcnt(0)162; GFX9-NEXT: v_mov_b32_e32 v0, s0163; GFX9-NEXT: v_div_fmas_f32 v2, v0, v0, v0164; GFX9-NEXT: v_mov_b32_e32 v0, 0165; GFX9-NEXT: v_mov_b32_e32 v1, 0166; GFX9-NEXT: global_store_dword v[0:1], v2, off167; GFX9-NEXT: s_waitcnt vmcnt(0)168; GFX9-NEXT: s_endpgm169;170; GFX10-LABEL: write_ds_sub_max_offset_global_clamp_bit:171; GFX10: ; %bb.0:172; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0173; GFX10-NEXT: s_mov_b32 vcc_lo, 0174; GFX10-NEXT: v_mov_b32_e32 v0, 0175; GFX10-NEXT: v_mov_b32_e32 v2, 0x7b176; GFX10-NEXT: v_mov_b32_e32 v3, 0177; GFX10-NEXT: v_mov_b32_e32 v1, 0178; GFX10-NEXT: ds_write_b32 v3, v2179; GFX10-NEXT: s_waitcnt lgkmcnt(0)180; GFX10-NEXT: v_div_fmas_f32 v4, s0, s0, s0181; GFX10-NEXT: global_store_dword v[0:1], v4, off182; GFX10-NEXT: s_waitcnt_vscnt null, 0x0183; GFX10-NEXT: s_endpgm184;185; GFX11-LABEL: write_ds_sub_max_offset_global_clamp_bit:186; GFX11: ; %bb.0:187; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0188; GFX11-NEXT: s_mov_b32 vcc_lo, 0189; GFX11-NEXT: v_mov_b32_e32 v0, 0190; GFX11-NEXT: v_dual_mov_b32 v2, 0x7b :: v_dual_mov_b32 v3, 0191; GFX11-NEXT: v_mov_b32_e32 v1, 0192; GFX11-NEXT: ds_store_b32 v3, v2193; GFX11-NEXT: s_waitcnt lgkmcnt(0)194; GFX11-NEXT: v_div_fmas_f32 v4, s0, s0, s0195; GFX11-NEXT: global_store_b32 v[0:1], v4, off dlc196; GFX11-NEXT: s_waitcnt_vscnt null, 0x0197; GFX11-NEXT: s_endpgm198 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1199 %sub1 = sub i32 -1, %x.i200 %tmp0 = getelementptr [256 x i32], ptr addrspace(3) @lds.obj, i32 0, i32 %sub1201 %arrayidx = getelementptr inbounds i32, ptr addrspace(3) %tmp0, i32 16383202 store i32 123, ptr addrspace(3) %arrayidx203 %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)204 store volatile float %fmas, ptr addrspace(1) null205 ret void206}207 208define amdgpu_kernel void @add_x_shl_max_offset() #1 {209; CI-LABEL: add_x_shl_max_offset:210; CI: ; %bb.0:211; CI-NEXT: v_lshlrev_b32_e32 v0, 4, v0212; CI-NEXT: v_mov_b32_e32 v1, 13213; CI-NEXT: s_mov_b32 m0, -1214; CI-NEXT: ds_write_b8 v0, v1 offset:65535215; CI-NEXT: s_endpgm216;217; GFX9-LABEL: add_x_shl_max_offset:218; GFX9: ; %bb.0:219; GFX9-NEXT: v_lshlrev_b32_e32 v0, 4, v0220; GFX9-NEXT: v_mov_b32_e32 v1, 13221; GFX9-NEXT: ds_write_b8 v0, v1 offset:65535222; GFX9-NEXT: s_endpgm223;224; GFX10-LABEL: add_x_shl_max_offset:225; GFX10: ; %bb.0:226; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0227; GFX10-NEXT: v_mov_b32_e32 v1, 13228; GFX10-NEXT: ds_write_b8 v0, v1 offset:65535229; GFX10-NEXT: s_endpgm230;231; GFX11-TRUE16-LABEL: add_x_shl_max_offset:232; GFX11-TRUE16: ; %bb.0:233; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0234; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)235; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 4, v0236; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13237; GFX11-TRUE16-NEXT: ds_store_b8 v1, v0 offset:65535238; GFX11-TRUE16-NEXT: s_endpgm239;240; GFX11-FAKE16-LABEL: add_x_shl_max_offset:241; GFX11-FAKE16: ; %bb.0:242; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0243; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)244; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 4, v0245; GFX11-FAKE16-NEXT: ds_store_b8 v0, v1 offset:65535246; GFX11-FAKE16-NEXT: s_endpgm247 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x()248 %shl = shl i32 %x.i, 4249 %add = add i32 %shl, 65535250 %z = zext i32 %add to i64251 %ptr = inttoptr i64 %z to ptr addrspace(3)252 store i8 13, ptr addrspace(3) %ptr, align 1253 ret void254}255 256; this could have the offset transform, but sub became xor257 258define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_alt() #1 {259; CI-LABEL: add_x_shl_neg_to_sub_max_offset_alt:260; CI: ; %bb.0:261; CI-NEXT: v_mul_i32_i24_e32 v0, -4, v0262; CI-NEXT: v_mov_b32_e32 v1, 13263; CI-NEXT: s_mov_b32 m0, -1264; CI-NEXT: ds_write_b8 v0, v1 offset:65535265; CI-NEXT: s_endpgm266;267; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset_alt:268; GFX9: ; %bb.0:269; GFX9-NEXT: v_mul_i32_i24_e32 v0, -4, v0270; GFX9-NEXT: v_mov_b32_e32 v1, 13271; GFX9-NEXT: ds_write_b8 v0, v1 offset:65535272; GFX9-NEXT: s_endpgm273;274; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset_alt:275; GFX10: ; %bb.0:276; GFX10-NEXT: v_mul_i32_i24_e32 v0, -4, v0277; GFX10-NEXT: v_mov_b32_e32 v1, 13278; GFX10-NEXT: ds_write_b8 v0, v1 offset:65535279; GFX10-NEXT: s_endpgm280;281; GFX11-TRUE16-LABEL: add_x_shl_neg_to_sub_max_offset_alt:282; GFX11-TRUE16: ; %bb.0:283; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0284; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)285; GFX11-TRUE16-NEXT: v_mul_i32_i24_e32 v1, -4, v0286; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13287; GFX11-TRUE16-NEXT: ds_store_b8 v1, v0 offset:65535288; GFX11-TRUE16-NEXT: s_endpgm289;290; GFX11-FAKE16-LABEL: add_x_shl_neg_to_sub_max_offset_alt:291; GFX11-FAKE16: ; %bb.0:292; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0293; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)294; GFX11-FAKE16-NEXT: v_mul_i32_i24_e32 v0, -4, v0295; GFX11-FAKE16-NEXT: ds_store_b8 v0, v1 offset:65535296; GFX11-FAKE16-NEXT: s_endpgm297 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x()298 %.neg = mul i32 %x.i, -4299 %add = add i32 %.neg, 65535300 %z = zext i32 %add to i64301 %ptr = inttoptr i64 %z to ptr addrspace(3)302 store i8 13, ptr addrspace(3) %ptr, align 1303 ret void304}305 306; this could have the offset transform, but sub became xor307 308define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_not_canonical() #1 {309; CI-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:310; CI: ; %bb.0:311; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0312; CI-NEXT: v_xor_b32_e32 v0, 0xffff, v0313; CI-NEXT: v_mov_b32_e32 v1, 13314; CI-NEXT: s_mov_b32 m0, -1315; CI-NEXT: ds_write_b8 v0, v1316; CI-NEXT: s_endpgm317;318; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:319; GFX9: ; %bb.0:320; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0321; GFX9-NEXT: v_xor_b32_e32 v0, 0xffff, v0322; GFX9-NEXT: v_mov_b32_e32 v1, 13323; GFX9-NEXT: ds_write_b8 v0, v1324; GFX9-NEXT: s_endpgm325;326; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:327; GFX10: ; %bb.0:328; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0329; GFX10-NEXT: v_mov_b32_e32 v1, 13330; GFX10-NEXT: v_xor_b32_e32 v0, 0xffff, v0331; GFX10-NEXT: ds_write_b8 v0, v1332; GFX10-NEXT: s_endpgm333;334; GFX11-TRUE16-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:335; GFX11-TRUE16: ; %bb.0:336; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0337; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)338; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0339; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0xffff, v0340; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13341; GFX11-TRUE16-NEXT: ds_store_b8 v1, v0342; GFX11-TRUE16-NEXT: s_endpgm343;344; GFX11-FAKE16-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:345; GFX11-FAKE16: ; %bb.0:346; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0347; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)348; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0349; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff, v0350; GFX11-FAKE16-NEXT: ds_store_b8 v0, v1351; GFX11-FAKE16-NEXT: s_endpgm352 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0353 %neg = sub i32 0, %x.i354 %shl = shl i32 %neg, 2355 %add = add i32 65535, %shl356 %ptr = inttoptr i32 %add to ptr addrspace(3)357 store i8 13, ptr addrspace(3) %ptr358 ret void359}360 361define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_p1() #1 {362; CI-LABEL: add_x_shl_neg_to_sub_max_offset_p1:363; CI: ; %bb.0:364; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0365; CI-NEXT: v_sub_i32_e32 v0, vcc, 0x10000, v0366; CI-NEXT: v_mov_b32_e32 v1, 13367; CI-NEXT: s_mov_b32 m0, -1368; CI-NEXT: ds_write_b8 v0, v1369; CI-NEXT: s_endpgm370;371; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset_p1:372; GFX9: ; %bb.0:373; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0374; GFX9-NEXT: v_sub_u32_e32 v0, 0x10000, v0375; GFX9-NEXT: v_mov_b32_e32 v1, 13376; GFX9-NEXT: ds_write_b8 v0, v1377; GFX9-NEXT: s_endpgm378;379; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset_p1:380; GFX10: ; %bb.0:381; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0382; GFX10-NEXT: v_mov_b32_e32 v1, 13383; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0x10000, v0384; GFX10-NEXT: ds_write_b8 v0, v1385; GFX10-NEXT: s_endpgm386;387; GFX11-TRUE16-LABEL: add_x_shl_neg_to_sub_max_offset_p1:388; GFX11-TRUE16: ; %bb.0:389; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0390; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)391; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0392; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v1, 0x10000, v0393; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13394; GFX11-TRUE16-NEXT: ds_store_b8 v1, v0395; GFX11-TRUE16-NEXT: s_endpgm396;397; GFX11-FAKE16-LABEL: add_x_shl_neg_to_sub_max_offset_p1:398; GFX11-FAKE16: ; %bb.0:399; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0400; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)401; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0402; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v0, 0x10000, v0403; GFX11-FAKE16-NEXT: ds_store_b8 v0, v1404; GFX11-FAKE16-NEXT: s_endpgm405 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0406 %neg = sub i32 0, %x.i407 %shl = shl i32 %neg, 2408 %add = add i32 65536, %shl409 %ptr = inttoptr i32 %add to ptr addrspace(3)410 store i8 13, ptr addrspace(3) %ptr411 ret void412}413 414define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use() #1 {415; CI-LABEL: add_x_shl_neg_to_sub_multi_use:416; CI: ; %bb.0:417; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0418; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0419; CI-NEXT: v_mov_b32_e32 v1, 13420; CI-NEXT: s_mov_b32 m0, -1421; CI-NEXT: ds_write_b32 v0, v1 offset:123422; CI-NEXT: ds_write_b32 v0, v1 offset:456423; CI-NEXT: s_endpgm424;425; GFX9-LABEL: add_x_shl_neg_to_sub_multi_use:426; GFX9: ; %bb.0:427; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0428; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0429; GFX9-NEXT: v_mov_b32_e32 v1, 13430; GFX9-NEXT: ds_write_b32 v0, v1 offset:123431; GFX9-NEXT: ds_write_b32 v0, v1 offset:456432; GFX9-NEXT: s_endpgm433;434; GFX10-LABEL: add_x_shl_neg_to_sub_multi_use:435; GFX10: ; %bb.0:436; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0437; GFX10-NEXT: v_mov_b32_e32 v1, 13438; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0439; GFX10-NEXT: ds_write_b32 v0, v1 offset:123440; GFX10-NEXT: ds_write_b32 v0, v1 offset:456441; GFX10-NEXT: s_endpgm442;443; GFX11-LABEL: add_x_shl_neg_to_sub_multi_use:444; GFX11: ; %bb.0:445; GFX11-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_lshlrev_b32 v0, 2, v0446; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)447; GFX11-NEXT: v_and_b32_e32 v0, 0xffc, v0448; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0, v0449; GFX11-NEXT: ds_store_b32 v0, v1 offset:123450; GFX11-NEXT: ds_store_b32 v0, v1 offset:456451; GFX11-NEXT: s_endpgm452 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0453 %neg = sub i32 0, %x.i454 %shl = shl i32 %neg, 2455 %add0 = add i32 123, %shl456 %add1 = add i32 456, %shl457 %ptr0 = inttoptr i32 %add0 to ptr addrspace(3)458 store volatile i32 13, ptr addrspace(3) %ptr0459 %ptr1 = inttoptr i32 %add1 to ptr addrspace(3)460 store volatile i32 13, ptr addrspace(3) %ptr1461 ret void462}463 464define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 {465; CI-LABEL: add_x_shl_neg_to_sub_multi_use_same_offset:466; CI: ; %bb.0:467; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0468; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0469; CI-NEXT: v_mov_b32_e32 v1, 13470; CI-NEXT: s_mov_b32 m0, -1471; CI-NEXT: ds_write_b32 v0, v1 offset:123472; CI-NEXT: ds_write_b32 v0, v1 offset:123473; CI-NEXT: s_endpgm474;475; GFX9-LABEL: add_x_shl_neg_to_sub_multi_use_same_offset:476; GFX9: ; %bb.0:477; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0478; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0479; GFX9-NEXT: v_mov_b32_e32 v1, 13480; GFX9-NEXT: ds_write_b32 v0, v1 offset:123481; GFX9-NEXT: ds_write_b32 v0, v1 offset:123482; GFX9-NEXT: s_endpgm483;484; GFX10-LABEL: add_x_shl_neg_to_sub_multi_use_same_offset:485; GFX10: ; %bb.0:486; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0487; GFX10-NEXT: v_mov_b32_e32 v1, 13488; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0489; GFX10-NEXT: ds_write_b32 v0, v1 offset:123490; GFX10-NEXT: ds_write_b32 v0, v1 offset:123491; GFX10-NEXT: s_endpgm492;493; GFX11-LABEL: add_x_shl_neg_to_sub_multi_use_same_offset:494; GFX11: ; %bb.0:495; GFX11-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0496; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)497; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0498; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0, v0499; GFX11-NEXT: ds_store_b32 v0, v1 offset:123500; GFX11-NEXT: ds_store_b32 v0, v1 offset:123501; GFX11-NEXT: s_endpgm502 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0503 %neg = sub i32 0, %x.i504 %shl = shl i32 %neg, 2505 %add = add i32 123, %shl506 %ptr = inttoptr i32 %add to ptr addrspace(3)507 store volatile i32 13, ptr addrspace(3) %ptr508 store volatile i32 13, ptr addrspace(3) %ptr509 ret void510}511 512define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 {513; CI-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset:514; CI: ; %bb.0:515; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0516; CI-NEXT: v_sub_i32_e32 v0, vcc, 0x3fb, v0517; CI-NEXT: v_mov_b32_e32 v1, 0x7b518; CI-NEXT: v_mov_b32_e32 v2, 0519; CI-NEXT: s_mov_b32 m0, -1520; CI-NEXT: ds_write2_b32 v0, v1, v2 offset1:1521; CI-NEXT: s_endpgm522;523; GFX9-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset:524; GFX9: ; %bb.0:525; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0526; GFX9-NEXT: v_sub_u32_e32 v0, 0x3fb, v0527; GFX9-NEXT: v_mov_b32_e32 v1, 0x7b528; GFX9-NEXT: v_mov_b32_e32 v2, 0529; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:1530; GFX9-NEXT: s_endpgm531;532; GFX10-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset:533; GFX10: ; %bb.0:534; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0535; GFX10-NEXT: v_mov_b32_e32 v1, 0536; GFX10-NEXT: v_mov_b32_e32 v2, 0x7b537; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0538; GFX10-NEXT: ds_write_b32 v0, v1 offset:1023539; GFX10-NEXT: ds_write_b32 v0, v2 offset:1019540; GFX10-NEXT: s_endpgm541;542; GFX11-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset:543; GFX11: ; %bb.0:544; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0545; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0x7b546; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)547; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0548; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0x3fb, v0549; GFX11-NEXT: ds_store_2addr_b32 v0, v1, v2 offset1:1550; GFX11-NEXT: s_endpgm551 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0552 %neg = sub i32 0, %x.i553 %shl = shl i32 %neg, 2554 %add = add i32 1019, %shl555 %ptr = inttoptr i32 %add to ptr addrspace(3)556 store i64 123, ptr addrspace(3) %ptr, align 4557 ret void558}559 560define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit(float %dummy.val) #1 {561; CI-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:562; CI: ; %bb.0:563; CI-NEXT: s_load_dword s0, s[4:5], 0x0564; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0565; CI-NEXT: v_sub_i32_e32 v0, vcc, 0x3fb, v0566; CI-NEXT: s_mov_b64 vcc, 0567; CI-NEXT: s_waitcnt lgkmcnt(0)568; CI-NEXT: v_mov_b32_e32 v1, s0569; CI-NEXT: v_mov_b32_e32 v2, 0x7b570; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1571; CI-NEXT: v_mov_b32_e32 v3, 0572; CI-NEXT: s_mov_b32 m0, -1573; CI-NEXT: s_mov_b64 s[0:1], 0574; CI-NEXT: s_mov_b32 s3, 0xf000575; CI-NEXT: s_mov_b32 s2, -1576; CI-NEXT: ds_write2_b32 v0, v2, v3 offset1:1577; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0578; CI-NEXT: s_waitcnt vmcnt(0)579; CI-NEXT: s_endpgm580;581; GFX9-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:582; GFX9: ; %bb.0:583; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0584; GFX9-NEXT: s_mov_b64 vcc, 0585; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0586; GFX9-NEXT: v_sub_u32_e32 v3, 0x3fb, v0587; GFX9-NEXT: v_mov_b32_e32 v4, 0x7b588; GFX9-NEXT: s_waitcnt lgkmcnt(0)589; GFX9-NEXT: v_mov_b32_e32 v1, s0590; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1591; GFX9-NEXT: v_mov_b32_e32 v0, 0592; GFX9-NEXT: v_mov_b32_e32 v5, 0593; GFX9-NEXT: v_mov_b32_e32 v1, 0594; GFX9-NEXT: ds_write2_b32 v3, v4, v5 offset1:1595; GFX9-NEXT: global_store_dword v[0:1], v2, off596; GFX9-NEXT: s_waitcnt vmcnt(0)597; GFX9-NEXT: s_endpgm598;599; GFX10-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:600; GFX10: ; %bb.0:601; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0602; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0603; GFX10-NEXT: s_mov_b32 vcc_lo, 0604; GFX10-NEXT: v_mov_b32_e32 v3, 0605; GFX10-NEXT: v_mov_b32_e32 v4, 0x7b606; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0, v0607; GFX10-NEXT: v_mov_b32_e32 v0, 0608; GFX10-NEXT: v_mov_b32_e32 v1, 0609; GFX10-NEXT: ds_write_b32 v2, v3 offset:1023610; GFX10-NEXT: ds_write_b32 v2, v4 offset:1019611; GFX10-NEXT: s_waitcnt lgkmcnt(0)612; GFX10-NEXT: v_div_fmas_f32 v5, s0, s0, s0613; GFX10-NEXT: global_store_dword v[0:1], v5, off614; GFX10-NEXT: s_waitcnt_vscnt null, 0x0615; GFX10-NEXT: s_endpgm616;617; GFX11-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:618; GFX11: ; %bb.0:619; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0620; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0621; GFX11-NEXT: s_mov_b32 vcc_lo, 0622; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0x7b623; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)624; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0625; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0x3fb, v0626; GFX11-NEXT: v_mov_b32_e32 v0, 0627; GFX11-NEXT: v_mov_b32_e32 v1, 0628; GFX11-NEXT: ds_store_2addr_b32 v2, v3, v4 offset1:1629; GFX11-NEXT: s_waitcnt lgkmcnt(0)630; GFX11-NEXT: v_div_fmas_f32 v5, s0, s0, s0631; GFX11-NEXT: global_store_b32 v[0:1], v5, off dlc632; GFX11-NEXT: s_waitcnt_vscnt null, 0x0633; GFX11-NEXT: s_endpgm634 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0635 %neg = sub i32 0, %x.i636 %shl = shl i32 %neg, 2637 %add = add i32 1019, %shl638 %ptr = inttoptr i32 %add to ptr addrspace(3)639 store i64 123, ptr addrspace(3) %ptr, align 4640 %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)641 store volatile float %fmas, ptr addrspace(1) null642 ret void643}644 645define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 {646; CI-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:647; CI: ; %bb.0:648; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0649; CI-NEXT: v_sub_i32_e32 v0, vcc, 0x3fc, v0650; CI-NEXT: v_mov_b32_e32 v1, 0x7b651; CI-NEXT: v_mov_b32_e32 v2, 0652; CI-NEXT: s_mov_b32 m0, -1653; CI-NEXT: ds_write2_b32 v0, v1, v2 offset1:1654; CI-NEXT: s_endpgm655;656; GFX9-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:657; GFX9: ; %bb.0:658; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0659; GFX9-NEXT: v_sub_u32_e32 v0, 0x3fc, v0660; GFX9-NEXT: v_mov_b32_e32 v1, 0x7b661; GFX9-NEXT: v_mov_b32_e32 v2, 0662; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:1663; GFX9-NEXT: s_endpgm664;665; GFX10-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:666; GFX10: ; %bb.0:667; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0668; GFX10-NEXT: v_mov_b32_e32 v1, 0669; GFX10-NEXT: v_mov_b32_e32 v2, 0x7b670; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0671; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x200, v0672; GFX10-NEXT: ds_write2_b32 v0, v2, v1 offset0:127 offset1:128673; GFX10-NEXT: s_endpgm674;675; GFX11-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:676; GFX11: ; %bb.0:677; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0678; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0x7b679; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)680; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0681; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0x3fc, v0682; GFX11-NEXT: ds_store_2addr_b32 v0, v1, v2 offset1:1683; GFX11-NEXT: s_endpgm684 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0685 %neg = sub i32 0, %x.i686 %shl = shl i32 %neg, 2687 %add = add i32 1020, %shl688 %ptr = inttoptr i32 %add to ptr addrspace(3)689 store i64 123, ptr addrspace(3) %ptr, align 4690 ret void691}692 693declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1)694 695attributes #0 = { nounwind readnone }696attributes #1 = { nounwind }697attributes #2 = { nounwind convergent }698