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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --enable-var-scope --check-prefix=GCN %s2 3; Check that vectorizer does not create slow misaligned loads4 5; GCN-LABEL: {{^}}ds1align1:6; GCN-COUNT-2: ds_read_u87; GCN-COUNT-2: ds_write_b88define amdgpu_kernel void @ds1align1(ptr addrspace(3) %in, ptr addrspace(3) %out) {9  %val1 = load i8, ptr addrspace(3) %in, align 110  %gep1 = getelementptr i8, ptr addrspace(3) %in, i32 111  %val2 = load i8, ptr addrspace(3) %gep1, align 112  store i8 %val1, ptr addrspace(3) %out, align 113  %gep2 = getelementptr i8, ptr addrspace(3) %out, i32 114  store i8 %val2, ptr addrspace(3) %gep2, align 115  ret void16}17 18; GCN-LABEL: {{^}}ds2align2:19; GCN-COUNT-2: ds_read_u1620; GCN-COUNT-2: ds_write_b1621define amdgpu_kernel void @ds2align2(ptr addrspace(3) %in, ptr addrspace(3) %out) {22  %val1 = load i16, ptr addrspace(3) %in, align 223  %gep1 = getelementptr i16, ptr addrspace(3) %in, i32 124  %val2 = load i16, ptr addrspace(3) %gep1, align 225  store i16 %val1, ptr addrspace(3) %out, align 226  %gep2 = getelementptr i16, ptr addrspace(3) %out, i32 127  store i16 %val2, ptr addrspace(3) %gep2, align 228  ret void29}30 31; GCN-LABEL: {{^}}ds4align4:32; GCN: ds_read2_b3233; GCN: ds_write2_b3234define amdgpu_kernel void @ds4align4(ptr addrspace(3) %in, ptr addrspace(3) %out) {35  %val1 = load i32, ptr addrspace(3) %in, align 436  %gep1 = getelementptr i32, ptr addrspace(3) %in, i32 137  %val2 = load i32, ptr addrspace(3) %gep1, align 438  store i32 %val1, ptr addrspace(3) %out, align 439  %gep2 = getelementptr i32, ptr addrspace(3) %out, i32 140  store i32 %val2, ptr addrspace(3) %gep2, align 441  ret void42}43 44; GCN-LABEL: {{^}}ds8align8:45; GCN: ds_read2_b6446; GCN: ds_write2_b6447define amdgpu_kernel void @ds8align8(ptr addrspace(3) %in, ptr addrspace(3) %out) {48  %val1 = load i64, ptr addrspace(3) %in, align 849  %gep1 = getelementptr i64, ptr addrspace(3) %in, i64 150  %val2 = load i64, ptr addrspace(3) %gep1, align 851  store i64 %val1, ptr addrspace(3) %out, align 852  %gep2 = getelementptr i64, ptr addrspace(3) %out, i64 153  store i64 %val2, ptr addrspace(3) %gep2, align 854  ret void55}56 57; GCN-LABEL: {{^}}ds1align2:58; GCN: ds_read_u1659; GCN: ds_write_b1660define amdgpu_kernel void @ds1align2(ptr addrspace(3) %in, ptr addrspace(3) %out) {61  %val1 = load i8, ptr addrspace(3) %in, align 262  %gep1 = getelementptr i8, ptr addrspace(3) %in, i32 163  %val2 = load i8, ptr addrspace(3) %gep1, align 264  store i8 %val1, ptr addrspace(3) %out, align 265  %gep2 = getelementptr i8, ptr addrspace(3) %out, i32 166  store i8 %val2, ptr addrspace(3) %gep2, align 267  ret void68}69 70; GCN-LABEL: {{^}}ds2align4:71; GCN: ds_read_b3272; GCN: ds_write_b3273define amdgpu_kernel void @ds2align4(ptr addrspace(3) %in, ptr addrspace(3) %out) {74  %val1 = load i16, ptr addrspace(3) %in, align 475  %gep1 = getelementptr i16, ptr addrspace(3) %in, i32 176  %val2 = load i16, ptr addrspace(3) %gep1, align 477  store i16 %val1, ptr addrspace(3) %out, align 478  %gep2 = getelementptr i16, ptr addrspace(3) %out, i32 179  store i16 %val2, ptr addrspace(3) %gep2, align 480  ret void81}82 83; GCN-LABEL: {{^}}ds4align8:84; GCN: ds_read_b6485; GCN: ds_write_b6486define amdgpu_kernel void @ds4align8(ptr addrspace(3) %in, ptr addrspace(3) %out) {87  %val1 = load i32, ptr addrspace(3) %in, align 888  %gep1 = getelementptr i32, ptr addrspace(3) %in, i32 189  %val2 = load i32, ptr addrspace(3) %gep1, align 890  store i32 %val1, ptr addrspace(3) %out, align 891  %gep2 = getelementptr i32, ptr addrspace(3) %out, i32 192  store i32 %val2, ptr addrspace(3) %gep2, align 893  ret void94}95 96; GCN-LABEL: {{^}}ds8align16:97; GCN: ds_read_b12898; GCN: ds_write_b12899define amdgpu_kernel void @ds8align16(ptr addrspace(3) %in, ptr addrspace(3) %out) {100  %val1 = load i64, ptr addrspace(3) %in, align 16101  %gep1 = getelementptr i64, ptr addrspace(3) %in, i64 1102  %val2 = load i64, ptr addrspace(3) %gep1, align 16103  store i64 %val1, ptr addrspace(3) %out, align 16104  %gep2 = getelementptr i64, ptr addrspace(3) %out, i64 1105  store i64 %val2, ptr addrspace(3) %gep2, align 16106  ret void107}108