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1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -o - < %s | FileCheck --check-prefixes=GCN,GFX90A %s5; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -early-live-intervals -o - < %s | FileCheck --check-prefixes=GCN,GFX908 %s6 7; GCN-LABEL: {{^}}gws_init_odd_reg:8; GFX908-DAG: ds_gws_init v1 gds9; GFX90A-DAG: ds_gws_init v2 gds10; GCN-DAG: ds_gws_init v0 gds11define amdgpu_ps void @gws_init_odd_reg(<2 x i32> %arg) {12 %vgpr.0 = extractelement <2 x i32> %arg, i32 013 %vgpr.1 = extractelement <2 x i32> %arg, i32 114 call void @llvm.amdgcn.ds.gws.init(i32 %vgpr.0, i32 0)15 call void @llvm.amdgcn.ds.gws.init(i32 %vgpr.1, i32 0)16 ret void17}18 19; GCN-LABEL: {{^}}gws_sema_br_odd_reg:20; GFX908-DAG: ds_gws_sema_br v1 gds21; GFX90A-DAG: ds_gws_sema_br v2 gds22; GCN-DAG: ds_gws_sema_br v0 gds23define amdgpu_ps void @gws_sema_br_odd_reg(<2 x i32> %arg) {24 %vgpr.0 = extractelement <2 x i32> %arg, i32 025 %vgpr.1 = extractelement <2 x i32> %arg, i32 126 call void @llvm.amdgcn.ds.gws.sema.br(i32 %vgpr.0, i32 0)27 call void @llvm.amdgcn.ds.gws.sema.br(i32 %vgpr.1, i32 0)28 ret void29}30 31; GCN-LABEL: {{^}}gws_barrier_odd_reg:32; GFX908-DAG: ds_gws_barrier v1 gds33; GFX90A-DAG: ds_gws_barrier v2 gds34; GCN-DAG: ds_gws_barrier v0 gds35define amdgpu_ps void @gws_barrier_odd_reg(<2 x i32> %arg) {36 %vgpr.0 = extractelement <2 x i32> %arg, i32 037 %vgpr.1 = extractelement <2 x i32> %arg, i32 138 call void @llvm.amdgcn.ds.gws.barrier(i32 %vgpr.0, i32 0)39 call void @llvm.amdgcn.ds.gws.barrier(i32 %vgpr.1, i32 0)40 ret void41}42 43; GCN-LABEL: {{^}}gws_init_odd_agpr:44; GFX908-COUNT-2: ds_gws_init v{{[0-9]+}} gds45; GFX90A-COUNT-2: ds_gws_init {{[va][0-9]?[02468]}} gds46define amdgpu_ps void @gws_init_odd_agpr(<4 x i32> %arg) {47bb:48 %mai = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %arg, i32 0, i32 0, i32 0)49 %agpr.0 = extractelement <4 x i32> %mai, i32 050 %agpr.1 = extractelement <4 x i32> %mai, i32 151 call void @llvm.amdgcn.ds.gws.init(i32 %agpr.0, i32 0)52 call void @llvm.amdgcn.ds.gws.init(i32 %agpr.1, i32 0)53 ret void54}55 56declare void @llvm.amdgcn.ds.gws.init(i32, i32)57declare void @llvm.amdgcn.ds.gws.sema.br(i32, i32)58declare void @llvm.amdgcn.ds.gws.barrier(i32, i32)59declare <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32, i32, <4 x i32>, i32, i32, i32)60