914 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1250 -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-UNALIGNED %s3 4; FIXME: We don't get cases where the address was an SGPR because we5; get a copy to the address register for each one.6 7@lds = addrspace(3) global [512 x float] poison, align 48@lds.f64 = addrspace(3) global [512 x double] poison, align 89 10define amdgpu_kernel void @simple_read2_f32(ptr addrspace(1) %out) #0 {11; GFX1250-LABEL: simple_read2_f32:12; GFX1250: ; %bb.0:13; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 114; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v015; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x016; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)17; GFX1250-NEXT: v_and_b32_e32 v2, 0xffc, v018; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:819; GFX1250-NEXT: s_wait_dscnt 0x020; GFX1250-NEXT: v_add_f32_e32 v0, v0, v121; GFX1250-NEXT: s_wait_kmcnt 0x022; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]23; GFX1250-NEXT: s_endpgm24 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #125 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i26 %val0 = load float, ptr addrspace(3) %arrayidx0, align 427 %add.x = add nsw i32 %x.i, 828 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x29 %val1 = load float, ptr addrspace(3) %arrayidx1, align 430 %sum = fadd float %val0, %val131 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i32 store float %sum, ptr addrspace(1) %out.gep, align 433 ret void34}35 36define amdgpu_kernel void @simple_read2_f32_max_offset(ptr addrspace(1) %out) #0 {37; GFX1250-LABEL: simple_read2_f32_max_offset:38; GFX1250: ; %bb.0:39; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v041; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x042; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)43; GFX1250-NEXT: v_and_b32_e32 v2, 0xffc, v044; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:25545; GFX1250-NEXT: s_wait_dscnt 0x046; GFX1250-NEXT: v_add_f32_e32 v0, v0, v147; GFX1250-NEXT: s_wait_kmcnt 0x048; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]49; GFX1250-NEXT: s_endpgm50 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #151 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i52 %val0 = load float, ptr addrspace(3) %arrayidx0, align 453 %add.x = add nsw i32 %x.i, 25554 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x55 %val1 = load float, ptr addrspace(3) %arrayidx1, align 456 %sum = fadd float %val0, %val157 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i58 store float %sum, ptr addrspace(1) %out.gep, align 459 ret void60}61 62define amdgpu_kernel void @simple_read2_f32_too_far(ptr addrspace(1) %out) #0 {63; GFX1250-LABEL: simple_read2_f32_too_far:64; GFX1250: ; %bb.0:65; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 166; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v067; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x068; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)69; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v070; GFX1250-NEXT: ds_load_b32 v1, v071; GFX1250-NEXT: ds_load_b32 v2, v0 offset:102872; GFX1250-NEXT: s_wait_dscnt 0x073; GFX1250-NEXT: v_add_f32_e32 v1, v1, v274; GFX1250-NEXT: s_wait_kmcnt 0x075; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]76; GFX1250-NEXT: s_endpgm77 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #178 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i79 %val0 = load float, ptr addrspace(3) %arrayidx0, align 480 %add.x = add nsw i32 %x.i, 25781 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x82 %val1 = load float, ptr addrspace(3) %arrayidx1, align 483 %sum = fadd float %val0, %val184 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i85 store float %sum, ptr addrspace(1) %out.gep, align 486 ret void87}88 89define amdgpu_kernel void @simple_read2_f32_x2(ptr addrspace(1) %out) #0 {90; GFX1250-LABEL: simple_read2_f32_x2:91; GFX1250: ; %bb.0:92; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 193; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v094; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x095; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)96; GFX1250-NEXT: v_and_b32_e32 v4, 0xffc, v097; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v4 offset1:898; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v4 offset0:11 offset1:2799; GFX1250-NEXT: s_wait_dscnt 0x0100; GFX1250-NEXT: v_dual_add_f32 v0, v0, v1 :: v_dual_add_f32 v1, v2, v3101; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1102; GFX1250-NEXT: s_wait_kmcnt 0x0103; GFX1250-NEXT: global_store_b32 v4, v0, s[0:1]104; GFX1250-NEXT: s_endpgm105 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1106 %idx.0 = add nsw i32 %tid.x, 0107 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0108 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4109 110 %idx.1 = add nsw i32 %tid.x, 8111 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1112 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4113 %sum.0 = fadd float %val0, %val1114 115 %idx.2 = add nsw i32 %tid.x, 11116 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2117 %val2 = load float, ptr addrspace(3) %arrayidx2, align 4118 119 %idx.3 = add nsw i32 %tid.x, 27120 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3121 %val3 = load float, ptr addrspace(3) %arrayidx3, align 4122 %sum.1 = fadd float %val2, %val3123 124 %sum = fadd float %sum.0, %sum.1125 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %idx.0126 store float %sum, ptr addrspace(1) %out.gep, align 4127 ret void128}129 130; Make sure there is an instruction between the two sets of reads.131define amdgpu_kernel void @simple_read2_f32_x2_barrier(ptr addrspace(1) %out) #0 {132; GFX1250-LABEL: simple_read2_f32_x2_barrier:133; GFX1250: ; %bb.0:134; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1135; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0136; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0137; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)138; GFX1250-NEXT: v_and_b32_e32 v4, 0xffc, v0139; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v4 offset1:8140; GFX1250-NEXT: s_barrier_signal -1141; GFX1250-NEXT: s_barrier_wait -1142; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v4 offset0:11 offset1:27143; GFX1250-NEXT: s_wait_dscnt 0x0144; GFX1250-NEXT: v_dual_add_f32 v0, v0, v1 :: v_dual_add_f32 v1, v2, v3145; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)146; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1147; GFX1250-NEXT: s_wait_kmcnt 0x0148; GFX1250-NEXT: global_store_b32 v4, v0, s[0:1]149; GFX1250-NEXT: s_endpgm150 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1151 %idx.0 = add nsw i32 %tid.x, 0152 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0153 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4154 155 %idx.1 = add nsw i32 %tid.x, 8156 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1157 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4158 %sum.0 = fadd float %val0, %val1159 160 call void @llvm.amdgcn.s.barrier() #2161 162 %idx.2 = add nsw i32 %tid.x, 11163 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2164 %val2 = load float, ptr addrspace(3) %arrayidx2, align 4165 166 %idx.3 = add nsw i32 %tid.x, 27167 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3168 %val3 = load float, ptr addrspace(3) %arrayidx3, align 4169 %sum.1 = fadd float %val2, %val3170 171 %sum = fadd float %sum.0, %sum.1172 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %idx.0173 store float %sum, ptr addrspace(1) %out.gep, align 4174 ret void175}176 177; For some reason adding something to the base address for the first178; element results in only folding the inner pair.179define amdgpu_kernel void @simple_read2_f32_x2_nonzero_base(ptr addrspace(1) %out) #0 {180; GFX1250-LABEL: simple_read2_f32_x2_nonzero_base:181; GFX1250: ; %bb.0:182; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1183; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0184; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0185; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)186; GFX1250-NEXT: v_and_b32_e32 v4, 0xffc, v0187; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v4 offset0:2 offset1:8188; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v4 offset0:11 offset1:27189; GFX1250-NEXT: s_wait_dscnt 0x0190; GFX1250-NEXT: v_dual_add_f32 v0, v0, v1 :: v_dual_add_f32 v1, v2, v3191; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1192; GFX1250-NEXT: s_wait_kmcnt 0x0193; GFX1250-NEXT: global_store_b32 v4, v0, s[0:1] offset:8194; GFX1250-NEXT: s_endpgm195 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1196 %idx.0 = add nsw i32 %tid.x, 2197 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0198 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4199 200 %idx.1 = add nsw i32 %tid.x, 8201 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1202 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4203 %sum.0 = fadd float %val0, %val1204 205 %idx.2 = add nsw i32 %tid.x, 11206 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2207 %val2 = load float, ptr addrspace(3) %arrayidx2, align 4208 209 %idx.3 = add nsw i32 %tid.x, 27210 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3211 %val3 = load float, ptr addrspace(3) %arrayidx3, align 4212 %sum.1 = fadd float %val2, %val3213 214 %sum = fadd float %sum.0, %sum.1215 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %idx.0216 store float %sum, ptr addrspace(1) %out.gep, align 4217 ret void218}219 220; Be careful of vectors of pointers. We don't know if the 2 pointers221; in the vectors are really the same base, so this is not safe to222; merge.223; Base pointers come from different subregister of same super224; register. We can't safely merge this.225define amdgpu_kernel void @read2_ptr_is_subreg_arg_f32(ptr addrspace(1) %out, <2 x ptr addrspace(3)> %lds.ptr) #0 {226; GFX1250-LABEL: read2_ptr_is_subreg_arg_f32:227; GFX1250: ; %bb.0:228; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1229; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0230; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0231; GFX1250-NEXT: s_wait_kmcnt 0x0232; GFX1250-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3233; GFX1250-NEXT: ds_load_b32 v1, v1 offset:32234; GFX1250-NEXT: ds_load_b32 v2, v2235; GFX1250-NEXT: s_wait_dscnt 0x0236; GFX1250-NEXT: v_add_f32_e32 v1, v1, v2237; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset238; GFX1250-NEXT: s_endpgm239 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1240 %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0241 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0242 %gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1243 %gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0244 %gep.1 = extractelement <2 x ptr addrspace(3)> %gep, i32 1245 %val0 = load float, ptr addrspace(3) %gep.0, align 4246 %val1 = load float, ptr addrspace(3) %gep.1, align 4247 %add.x = add nsw i32 %x.i, 8248 %sum = fadd float %val0, %val1249 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i250 store float %sum, ptr addrspace(1) %out.gep, align 4251 ret void252}253 254; Apply a constant scalar offset after the pointer vector extract. We255; are rejecting merges that have the same, constant 0 offset, so make256; sure we are really rejecting it because of the different257; subregisters.258define amdgpu_kernel void @read2_ptr_is_subreg_arg_offset_f32(ptr addrspace(1) %out, <2 x ptr addrspace(3)> %lds.ptr) #0 {259; GFX1250-LABEL: read2_ptr_is_subreg_arg_offset_f32:260; GFX1250: ; %bb.0:261; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1262; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0263; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0264; GFX1250-NEXT: s_wait_kmcnt 0x0265; GFX1250-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3266; GFX1250-NEXT: ds_load_b32 v1, v1 offset:32267; GFX1250-NEXT: ds_load_b32 v2, v2 offset:32268; GFX1250-NEXT: s_wait_dscnt 0x0269; GFX1250-NEXT: v_add_f32_e32 v1, v1, v2270; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset271; GFX1250-NEXT: s_endpgm272 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1273 %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0274 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0275 %gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1276 %gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0277 %gep.1 = extractelement <2 x ptr addrspace(3)> %gep, i32 1278 279 ; Apply an additional offset after the vector that will be more obviously folded.280 %gep.1.offset = getelementptr float, ptr addrspace(3) %gep.1, i32 8281 282 %val0 = load float, ptr addrspace(3) %gep.0, align 4283 %val1 = load float, ptr addrspace(3) %gep.1.offset, align 4284 %add.x = add nsw i32 %x.i, 8285 %sum = fadd float %val0, %val1286 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i287 store float %sum, ptr addrspace(1) %out.gep, align 4288 ret void289}290 291define amdgpu_kernel void @read2_ptr_is_subreg_f32(ptr addrspace(1) %out) #0 {292; GFX1250-LABEL: read2_ptr_is_subreg_f32:293; GFX1250: ; %bb.0:294; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1295; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0296; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0297; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)298; GFX1250-NEXT: v_and_b32_e32 v2, 0xffc, v0299; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:8300; GFX1250-NEXT: s_wait_dscnt 0x0301; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1302; GFX1250-NEXT: s_wait_kmcnt 0x0303; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]304; GFX1250-NEXT: s_endpgm305 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1306 %ptr.0 = insertelement <2 x ptr addrspace(3)> poison, ptr addrspace(3) @lds, i32 0307 %ptr.1 = insertelement <2 x ptr addrspace(3)> %ptr.0, ptr addrspace(3) @lds, i32 1308 %x.i.v.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0309 %x.i.v.1 = insertelement <2 x i32> %x.i.v.0, i32 %x.i, i32 1310 %idx = add <2 x i32> %x.i.v.1, <i32 0, i32 8>311 %gep = getelementptr inbounds [512 x float], <2 x ptr addrspace(3)> %ptr.1, <2 x i32> <i32 0, i32 0>, <2 x i32> %idx312 %gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0313 %gep.1 = extractelement <2 x ptr addrspace(3)> %gep, i32 1314 %val0 = load float, ptr addrspace(3) %gep.0, align 4315 %val1 = load float, ptr addrspace(3) %gep.1, align 4316 %add.x = add nsw i32 %x.i, 8317 %sum = fadd float %val0, %val1318 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i319 store float %sum, ptr addrspace(1) %out.gep, align 4320 ret void321}322 323define amdgpu_kernel void @simple_read2_f32_volatile_0(ptr addrspace(1) %out) #0 {324; GFX1250-LABEL: simple_read2_f32_volatile_0:325; GFX1250: ; %bb.0:326; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1327; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0328; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0329; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)330; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0331; GFX1250-NEXT: ds_load_b32 v1, v0332; GFX1250-NEXT: ds_load_b32 v2, v0 offset:32333; GFX1250-NEXT: s_wait_dscnt 0x0334; GFX1250-NEXT: v_add_f32_e32 v1, v1, v2335; GFX1250-NEXT: s_wait_kmcnt 0x0336; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]337; GFX1250-NEXT: s_endpgm338 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1339 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i340 %val0 = load volatile float, ptr addrspace(3) %arrayidx0, align 4341 %add.x = add nsw i32 %x.i, 8342 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x343 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4344 %sum = fadd float %val0, %val1345 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i346 store float %sum, ptr addrspace(1) %out.gep, align 4347 ret void348}349 350define amdgpu_kernel void @simple_read2_f32_volatile_1(ptr addrspace(1) %out) #0 {351; GFX1250-LABEL: simple_read2_f32_volatile_1:352; GFX1250: ; %bb.0:353; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1354; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0355; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0356; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)357; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0358; GFX1250-NEXT: ds_load_b32 v1, v0359; GFX1250-NEXT: ds_load_b32 v2, v0 offset:32360; GFX1250-NEXT: s_wait_dscnt 0x0361; GFX1250-NEXT: v_add_f32_e32 v1, v1, v2362; GFX1250-NEXT: s_wait_kmcnt 0x0363; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]364; GFX1250-NEXT: s_endpgm365 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1366 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i367 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4368 %add.x = add nsw i32 %x.i, 8369 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x370 %val1 = load volatile float, ptr addrspace(3) %arrayidx1, align 4371 %sum = fadd float %val0, %val1372 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i373 store float %sum, ptr addrspace(1) %out.gep, align 4374 ret void375}376 377; Can't fold since not correctly aligned.378define amdgpu_kernel void @unaligned_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {379; GFX1250-LABEL: unaligned_read2_f32:380; GFX1250: ; %bb.0:381; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1382; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0383; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0384; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)385; GFX1250-NEXT: v_and_b32_e32 v2, 0xffc, v0386; GFX1250-NEXT: s_wait_kmcnt 0x0387; GFX1250-NEXT: v_add_nc_u32_e32 v0, s2, v2388; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:8389; GFX1250-NEXT: s_wait_dscnt 0x0390; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1391; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]392; GFX1250-NEXT: s_endpgm393 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1394 %arrayidx0 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %x.i395 %val0 = load float, ptr addrspace(3) %arrayidx0, align 1396 %add.x = add nsw i32 %x.i, 8397 %arrayidx1 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %add.x398 %val1 = load float, ptr addrspace(3) %arrayidx1, align 1399 %sum = fadd float %val0, %val1400 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i401 store float %sum, ptr addrspace(1) %out.gep, align 4402 ret void403}404 405define amdgpu_kernel void @unaligned_offset_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {406; GFX1250-LABEL: unaligned_offset_read2_f32:407; GFX1250: ; %bb.0:408; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1409; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0410; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0411; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)412; GFX1250-NEXT: v_and_b32_e32 v2, 0xffc, v0413; GFX1250-NEXT: s_wait_kmcnt 0x0414; GFX1250-NEXT: v_add_nc_u32_e32 v0, s2, v2415; GFX1250-NEXT: ds_load_b64 v[0:1], v0 offset:5416; GFX1250-NEXT: s_wait_dscnt 0x0417; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1418; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]419; GFX1250-NEXT: s_endpgm420 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1421 %base = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %x.i422 %addr0.i8 = getelementptr inbounds i8, ptr addrspace(3) %base, i32 5423 %val0 = load float, ptr addrspace(3) %addr0.i8, align 1424 %addr1.i8 = getelementptr inbounds i8, ptr addrspace(3) %base, i32 9425 %val1 = load float, ptr addrspace(3) %addr1.i8, align 1426 %sum = fadd float %val0, %val1427 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i428 store float %sum, ptr addrspace(1) %out.gep, align 4429 ret void430}431 432define amdgpu_kernel void @misaligned_2_simple_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {433; GFX1250-LABEL: misaligned_2_simple_read2_f32:434; GFX1250: ; %bb.0:435; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1436; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0437; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0438; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)439; GFX1250-NEXT: v_and_b32_e32 v2, 0xffc, v0440; GFX1250-NEXT: s_wait_kmcnt 0x0441; GFX1250-NEXT: v_add_nc_u32_e32 v0, s2, v2442; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:8443; GFX1250-NEXT: s_wait_dscnt 0x0444; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1445; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]446; GFX1250-NEXT: s_endpgm447 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1448 %arrayidx0 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %x.i449 %val0 = load float, ptr addrspace(3) %arrayidx0, align 2450 %add.x = add nsw i32 %x.i, 8451 %arrayidx1 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %add.x452 %val1 = load float, ptr addrspace(3) %arrayidx1, align 2453 %sum = fadd float %val0, %val1454 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i455 store float %sum, ptr addrspace(1) %out.gep, align 4456 ret void457}458 459define amdgpu_kernel void @simple_read2_f64(ptr addrspace(1) %out) #0 {460; GFX1250-LABEL: simple_read2_f64:461; GFX1250: ; %bb.0:462; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1463; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0464; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0465; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)466; GFX1250-NEXT: v_and_b32_e32 v4, 0x1ff8, v0467; GFX1250-NEXT: ds_load_2addr_b64 v[0:3], v4 offset1:8468; GFX1250-NEXT: s_wait_dscnt 0x0469; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0470; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]471; GFX1250-NEXT: s_wait_kmcnt 0x0472; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]473; GFX1250-NEXT: s_endpgm474 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1475 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i476 %val0 = load double, ptr addrspace(3) %arrayidx0, align 8477 %add.x = add nsw i32 %x.i, 8478 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x479 %val1 = load double, ptr addrspace(3) %arrayidx1, align 8480 %sum = fadd double %val0, %val1481 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i482 store double %sum, ptr addrspace(1) %out.gep, align 8483 ret void484}485 486define amdgpu_kernel void @simple_read2_f64_max_offset(ptr addrspace(1) %out) #0 {487; GFX1250-LABEL: simple_read2_f64_max_offset:488; GFX1250: ; %bb.0:489; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1490; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0491; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0492; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)493; GFX1250-NEXT: v_and_b32_e32 v4, 0x1ff8, v0494; GFX1250-NEXT: ds_load_2addr_b64 v[0:3], v4 offset1:255495; GFX1250-NEXT: s_wait_dscnt 0x0496; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0497; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]498; GFX1250-NEXT: s_wait_kmcnt 0x0499; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]500; GFX1250-NEXT: s_endpgm501 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1502 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i503 %val0 = load double, ptr addrspace(3) %arrayidx0, align 8504 %add.x = add nsw i32 %x.i, 255505 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x506 %val1 = load double, ptr addrspace(3) %arrayidx1, align 8507 %sum = fadd double %val0, %val1508 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i509 store double %sum, ptr addrspace(1) %out.gep, align 8510 ret void511}512 513define amdgpu_kernel void @simple_read2_f64_too_far(ptr addrspace(1) %out) #0 {514; GFX1250-LABEL: simple_read2_f64_too_far:515; GFX1250: ; %bb.0:516; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1517; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0518; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0519; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)520; GFX1250-NEXT: v_and_b32_e32 v4, 0x1ff8, v0521; GFX1250-NEXT: ds_load_b64 v[0:1], v4522; GFX1250-NEXT: ds_load_b64 v[2:3], v4 offset:2056523; GFX1250-NEXT: s_wait_dscnt 0x0524; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0525; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]526; GFX1250-NEXT: s_wait_kmcnt 0x0527; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]528; GFX1250-NEXT: s_endpgm529 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1530 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i531 %val0 = load double, ptr addrspace(3) %arrayidx0, align 8532 %add.x = add nsw i32 %x.i, 257533 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x534 %val1 = load double, ptr addrspace(3) %arrayidx1, align 8535 %sum = fadd double %val0, %val1536 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i537 store double %sum, ptr addrspace(1) %out.gep, align 8538 ret void539}540 541; Alignment only 4542define amdgpu_kernel void @misaligned_read2_f64(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {543; GFX1250-LABEL: misaligned_read2_f64:544; GFX1250: ; %bb.0:545; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1546; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0547; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0548; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)549; GFX1250-NEXT: v_and_b32_e32 v4, 0x1ff8, v0550; GFX1250-NEXT: s_wait_kmcnt 0x0551; GFX1250-NEXT: v_add_nc_u32_e32 v2, s2, v4552; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:1553; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v2 offset0:14 offset1:15554; GFX1250-NEXT: s_wait_dscnt 0x0555; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0556; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]557; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]558; GFX1250-NEXT: s_endpgm559 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1560 %arrayidx0 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %x.i561 %val0 = load double, ptr addrspace(3) %arrayidx0, align 4562 %add.x = add nsw i32 %x.i, 7563 %arrayidx1 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %add.x564 %val1 = load double, ptr addrspace(3) %arrayidx1, align 4565 %sum = fadd double %val0, %val1566 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i567 store double %sum, ptr addrspace(1) %out.gep, align 4568 ret void569}570 571@foo = addrspace(3) global [4 x i32] poison, align 4572 573define amdgpu_kernel void @load_constant_adjacent_offsets(ptr addrspace(1) %out) {574; GFX1250-LABEL: load_constant_adjacent_offsets:575; GFX1250: ; %bb.0:576; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1577; GFX1250-NEXT: v_mov_b32_e32 v2, 0578; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0579; GFX1250-NEXT: ds_load_b64 v[0:1], v2580; GFX1250-NEXT: s_wait_dscnt 0x0581; GFX1250-NEXT: v_add_nc_u32_e32 v0, v0, v1582; GFX1250-NEXT: s_wait_kmcnt 0x0583; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]584; GFX1250-NEXT: s_endpgm585 %val0 = load i32, ptr addrspace(3) @foo, align 4586 %val1 = load i32, ptr addrspace(3) getelementptr inbounds ([4 x i32], ptr addrspace(3) @foo, i32 0, i32 1), align 4587 %sum = add i32 %val0, %val1588 store i32 %sum, ptr addrspace(1) %out, align 4589 ret void590}591 592define amdgpu_kernel void @load_constant_disjoint_offsets(ptr addrspace(1) %out) {593; GFX1250-LABEL: load_constant_disjoint_offsets:594; GFX1250: ; %bb.0:595; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1596; GFX1250-NEXT: v_mov_b32_e32 v2, 0597; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0598; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:2599; GFX1250-NEXT: s_wait_dscnt 0x0600; GFX1250-NEXT: v_add_nc_u32_e32 v0, v0, v1601; GFX1250-NEXT: s_wait_kmcnt 0x0602; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1]603; GFX1250-NEXT: s_endpgm604 %val0 = load i32, ptr addrspace(3) @foo, align 4605 %val1 = load i32, ptr addrspace(3) getelementptr inbounds ([4 x i32], ptr addrspace(3) @foo, i32 0, i32 2), align 4606 %sum = add i32 %val0, %val1607 store i32 %sum, ptr addrspace(1) %out, align 4608 ret void609}610 611@bar = addrspace(3) global [4 x i64] poison, align 4612 613define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %out) {614; GFX1250-LABEL: load_misaligned64_constant_offsets:615; GFX1250: ; %bb.0:616; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1617; GFX1250-NEXT: v_mov_b32_e32 v4, 0618; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0619; GFX1250-NEXT: ds_load_b128 v[0:3], v4620; GFX1250-NEXT: s_wait_dscnt 0x0621; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]622; GFX1250-NEXT: s_wait_kmcnt 0x0623; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]624; GFX1250-NEXT: s_endpgm625 %val0 = load i64, ptr addrspace(3) @bar, align 4626 %val1 = load i64, ptr addrspace(3) getelementptr inbounds ([4 x i64], ptr addrspace(3) @bar, i32 0, i32 1), align 4627 %sum = add i64 %val0, %val1628 store i64 %sum, ptr addrspace(1) %out, align 8629 ret void630}631 632@bar.large = addrspace(3) global [4096 x i64] poison, align 4633 634define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspace(1) %out) {635; GFX1250-LABEL: load_misaligned64_constant_large_offsets:636; GFX1250: ; %bb.0:637; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1638; GFX1250-NEXT: v_mov_b32_e32 v4, 0639; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0640; GFX1250-NEXT: ds_load_b64 v[0:1], v4 offset:16384641; GFX1250-NEXT: ds_load_b64 v[2:3], v4 offset:32760642; GFX1250-NEXT: s_wait_dscnt 0x0643; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]644; GFX1250-NEXT: s_wait_kmcnt 0x0645; GFX1250-NEXT: global_store_b64 v4, v[0:1], s[0:1]646; GFX1250-NEXT: s_endpgm647 %val0 = load i64, ptr addrspace(3) getelementptr inbounds ([4096 x i64], ptr addrspace(3) @bar.large, i32 0, i32 2048), align 4648 %val1 = load i64, ptr addrspace(3) getelementptr inbounds ([4096 x i64], ptr addrspace(3) @bar.large, i32 0, i32 4095), align 4649 %sum = add i64 %val0, %val1650 store i64 %sum, ptr addrspace(1) %out, align 8651 ret void652}653 654@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] poison, align 4655@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] poison, align 4656 657define amdgpu_kernel void @sgemm_inner_loop_read2_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb) #0 {658; GFX1250-LABEL: sgemm_inner_loop_read2_sequence:659; GFX1250: ; %bb.0:660; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1661; GFX1250-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c662; GFX1250-NEXT: s_and_b32 s1, ttmp6, 15663; GFX1250-NEXT: s_add_co_i32 s0, s0, 1664; GFX1250-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4)665; GFX1250-NEXT: s_mul_i32 s0, ttmp9, s0666; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)667; GFX1250-NEXT: s_add_co_i32 s1, s1, s0668; GFX1250-NEXT: s_cmp_eq_u32 s2, 0669; GFX1250-NEXT: s_cselect_b32 s0, ttmp9, s1670; GFX1250-NEXT: s_lshl_b32 s0, s0, 2671; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)672; GFX1250-NEXT: s_add_co_i32 s1, s0, 0xc20673; GFX1250-NEXT: s_addk_co_i32 s0, 0xc60674; GFX1250-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v4, s0675; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0676; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v1 offset1:1677; GFX1250-NEXT: ds_load_2addr_b32 v[4:5], v4 offset1:1678; GFX1250-NEXT: s_wait_dscnt 0x1679; GFX1250-NEXT: v_dual_lshrrev_b32 v0, 8, v0 :: v_dual_add_f32 v2, v2, v3680; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)681; GFX1250-NEXT: v_and_b32_e32 v8, 0xffc, v0682; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v8 offset1:1683; GFX1250-NEXT: ds_load_2addr_b32 v[6:7], v8 offset0:32 offset1:33684; GFX1250-NEXT: s_wait_dscnt 0x2685; GFX1250-NEXT: v_add_f32_e32 v2, v2, v4686; GFX1250-NEXT: v_add_f32_e32 v4, v2, v5687; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v8 offset0:64 offset1:65688; GFX1250-NEXT: s_wait_dscnt 0x2689; GFX1250-NEXT: v_add_f32_e32 v0, v4, v0690; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)691; GFX1250-NEXT: v_dual_add_f32 v0, v0, v1 :: v_dual_mov_b32 v1, 0692; GFX1250-NEXT: s_wait_dscnt 0x1693; GFX1250-NEXT: v_add_f32_e32 v0, v0, v6694; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)695; GFX1250-NEXT: v_add_f32_e32 v0, v0, v7696; GFX1250-NEXT: s_wait_dscnt 0x0697; GFX1250-NEXT: v_add_f32_e32 v0, v0, v2698; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)699; GFX1250-NEXT: v_add_f32_e32 v0, v0, v3700; GFX1250-NEXT: s_wait_kmcnt 0x0701; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]702; GFX1250-NEXT: s_endpgm703 %x.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #1704 %y.i = tail call i32 @llvm.amdgcn.workitem.id.y() #1705 %arrayidx44 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %x.i706 %tmp16 = load float, ptr addrspace(3) %arrayidx44, align 4707 %add47 = add nsw i32 %x.i, 1708 %arrayidx48 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add47709 %tmp17 = load float, ptr addrspace(3) %arrayidx48, align 4710 %add51 = add nsw i32 %x.i, 16711 %arrayidx52 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add51712 %tmp18 = load float, ptr addrspace(3) %arrayidx52, align 4713 %add55 = add nsw i32 %x.i, 17714 %arrayidx56 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add55715 %tmp19 = load float, ptr addrspace(3) %arrayidx56, align 4716 %arrayidx60 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %y.i717 %tmp20 = load float, ptr addrspace(3) %arrayidx60, align 4718 %add63 = add nsw i32 %y.i, 1719 %arrayidx64 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add63720 %tmp21 = load float, ptr addrspace(3) %arrayidx64, align 4721 %add67 = add nsw i32 %y.i, 32722 %arrayidx68 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add67723 %tmp22 = load float, ptr addrspace(3) %arrayidx68, align 4724 %add71 = add nsw i32 %y.i, 33725 %arrayidx72 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add71726 %tmp23 = load float, ptr addrspace(3) %arrayidx72, align 4727 %add75 = add nsw i32 %y.i, 64728 %arrayidx76 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add75729 %tmp24 = load float, ptr addrspace(3) %arrayidx76, align 4730 %add79 = add nsw i32 %y.i, 65731 %arrayidx80 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add79732 %tmp25 = load float, ptr addrspace(3) %arrayidx80, align 4733 %sum.0 = fadd float %tmp16, %tmp17734 %sum.1 = fadd float %sum.0, %tmp18735 %sum.2 = fadd float %sum.1, %tmp19736 %sum.3 = fadd float %sum.2, %tmp20737 %sum.4 = fadd float %sum.3, %tmp21738 %sum.5 = fadd float %sum.4, %tmp22739 %sum.6 = fadd float %sum.5, %tmp23740 %sum.7 = fadd float %sum.6, %tmp24741 %sum.8 = fadd float %sum.7, %tmp25742 store float %sum.8, ptr addrspace(1) %C, align 4743 ret void744}745 746define amdgpu_kernel void @misaligned_read2_v2i32(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {747; GFX1250-LABEL: misaligned_read2_v2i32:748; GFX1250: ; %bb.0:749; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1750; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0751; GFX1250-NEXT: s_wait_kmcnt 0x0752; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2753; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:1754; GFX1250-NEXT: s_wait_dscnt 0x0755; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]756; GFX1250-NEXT: s_endpgm757 %load = load <2 x i32>, ptr addrspace(3) %in, align 4758 store <2 x i32> %load, ptr addrspace(1) %out, align 8759 ret void760}761 762define amdgpu_kernel void @misaligned_read2_i64(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {763; GFX1250-LABEL: misaligned_read2_i64:764; GFX1250: ; %bb.0:765; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1766; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x0767; GFX1250-NEXT: s_wait_kmcnt 0x0768; GFX1250-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2769; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:1770; GFX1250-NEXT: s_wait_dscnt 0x0771; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]772; GFX1250-NEXT: s_endpgm773 %load = load i64, ptr addrspace(3) %in, align 4774 store i64 %load, ptr addrspace(1) %out, align 8775 ret void776}777 778define amdgpu_kernel void @ds_read_diff_base_interleaving(779; GFX1250-LABEL: ds_read_diff_base_interleaving:780; GFX1250: ; %bb.0: ; %bb781; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1782; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8783; GFX1250-NEXT: v_dual_lshrrev_b32 v1, 6, v0 :: v_dual_lshlrev_b32 v0, 2, v0784; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)785; GFX1250-NEXT: v_and_b32_e32 v1, 0x3ff0, v1786; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0787; GFX1250-NEXT: s_wait_kmcnt 0x0788; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)789; GFX1250-NEXT: v_dual_add_nc_u32 v2, s0, v1 :: v_dual_add_nc_u32 v3, s1, v0790; GFX1250-NEXT: v_dual_add_nc_u32 v4, s2, v1 :: v_dual_add_nc_u32 v6, s3, v0791; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0792; GFX1250-NEXT: ds_load_2addr_b32 v[0:1], v2 offset1:1793; GFX1250-NEXT: ds_load_2addr_b32 v[2:3], v3 offset1:4794; GFX1250-NEXT: ds_load_2addr_b32 v[4:5], v4 offset1:1795; GFX1250-NEXT: ds_load_2addr_b32 v[6:7], v6 offset1:4796; GFX1250-NEXT: s_wait_dscnt 0x2797; GFX1250-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3798; GFX1250-NEXT: s_wait_dscnt 0x0799; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)800; GFX1250-NEXT: v_dual_mul_f32 v2, v4, v6 :: v_dual_add_f32 v0, 2.0, v0801; GFX1250-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_mov_b32 v2, 0802; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)803; GFX1250-NEXT: v_dual_sub_f32 v0, v0, v1 :: v_dual_mul_f32 v1, v5, v7804; GFX1250-NEXT: v_sub_f32_e32 v0, v0, v1805; GFX1250-NEXT: s_wait_kmcnt 0x0806; GFX1250-NEXT: global_store_b32 v2, v0, s[0:1] offset:40807; GFX1250-NEXT: s_endpgm808 ptr addrspace(1) nocapture %arg,809 ptr addrspace(3) %arg1,810 ptr addrspace(3) %arg2,811 ptr addrspace(3) %arg3,812 ptr addrspace(3) %arg4) #1 {813bb:814 %tmp = getelementptr float, ptr addrspace(1) %arg, i64 10815 %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.x() #2816 %tmp6 = tail call i32 @llvm.amdgcn.workitem.id.y() #2817 %tmp7 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg1, i32 0, i32 %tmp6, i32 0818 %tmp8 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg2, i32 0, i32 0, i32 %tmp5819 %tmp9 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg3, i32 0, i32 %tmp6, i32 0820 %tmp10 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg4, i32 0, i32 0, i32 %tmp5821 %tmp11 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg1, i32 0, i32 %tmp6, i32 1822 %tmp12 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg2, i32 0, i32 1, i32 %tmp5823 %tmp13 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg3, i32 0, i32 %tmp6, i32 1824 %tmp14 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg4, i32 0, i32 1, i32 %tmp5825 %tmp15 = load float, ptr addrspace(3) %tmp7826 %tmp16 = load float, ptr addrspace(3) %tmp8827 %tmp17 = fmul float %tmp15, %tmp16828 %tmp18 = fadd float 2.000000e+00, %tmp17829 %tmp19 = load float, ptr addrspace(3) %tmp9830 %tmp20 = load float, ptr addrspace(3) %tmp10831 %tmp21 = fmul float %tmp19, %tmp20832 %tmp22 = fsub float %tmp18, %tmp21833 %tmp23 = load float, ptr addrspace(3) %tmp11834 %tmp24 = load float, ptr addrspace(3) %tmp12835 %tmp25 = fmul float %tmp23, %tmp24836 %tmp26 = fsub float %tmp22, %tmp25837 %tmp27 = load float, ptr addrspace(3) %tmp13838 %tmp28 = load float, ptr addrspace(3) %tmp14839 %tmp29 = fmul float %tmp27, %tmp28840 %tmp30 = fsub float %tmp26, %tmp29841 store float %tmp30, ptr addrspace(1) %tmp842 ret void843}844 845define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspace(3) %arg) {846; GFX1250-LABEL: ds_read_call_read:847; GFX1250: ; %bb.0:848; GFX1250-NEXT: s_mov_b32 s32, 0849; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1850; GFX1250-NEXT: s_load_b96 s[36:38], s[4:5], 0x0851; GFX1250-NEXT: v_and_b32_e32 v1, 0x3ff, v0852; GFX1250-NEXT: v_dual_mov_b32 v42, 0 :: v_dual_mov_b32 v31, v0853; GFX1250-NEXT: s_mov_b64 s[10:11], s[6:7]854; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[4:5], 12855; GFX1250-NEXT: s_mov_b64 s[12:13], void_func_void@abs64856; GFX1250-NEXT: s_wait_xcnt 0x0857; GFX1250-NEXT: s_mov_b64 s[4:5], s[0:1]858; GFX1250-NEXT: s_mov_b64 s[6:7], s[2:3]859; GFX1250-NEXT: s_wait_kmcnt 0x0860; GFX1250-NEXT: v_lshl_add_u32 v40, v1, 2, s38861; GFX1250-NEXT: ds_load_b32 v41, v40862; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[12:13]863; GFX1250-NEXT: ds_load_b32 v0, v40 offset:4864; GFX1250-NEXT: s_wait_dscnt 0x0865; GFX1250-NEXT: v_add_nc_u32_e32 v0, v41, v0866; GFX1250-NEXT: global_store_b32 v42, v0, s[36:37]867; GFX1250-NEXT: s_endpgm868 %x = call i32 @llvm.amdgcn.workitem.id.x()869 %arrayidx0 = getelementptr i32, ptr addrspace(3) %arg, i32 %x870 %arrayidx1 = getelementptr i32, ptr addrspace(3) %arrayidx0, i32 1871 %v0 = load i32, ptr addrspace(3) %arrayidx0, align 4872 call void @void_func_void()873 %v1 = load i32, ptr addrspace(3) %arrayidx1, align 4874 %r = add i32 %v0, %v1875 store i32 %r, ptr addrspace(1) %out, align 4876 ret void877}878 879@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] poison, align 1880 881define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out) {882; GFX1250-LABEL: read2_v2i32_align1_odd_offset:883; GFX1250: ; %bb.0: ; %entry884; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1885; GFX1250-NEXT: v_mov_b32_e32 v2, 0886; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0887; GFX1250-NEXT: ds_load_b64 v[0:1], v2 offset:65888; GFX1250-NEXT: s_wait_dscnt 0x0889; GFX1250-NEXT: s_wait_kmcnt 0x0890; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]891; GFX1250-NEXT: s_endpgm892entry:893 %load = load <2 x i32>, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @v2i32_align1, i32 65), align 1894 store <2 x i32> %load, ptr addrspace(1) %out895 ret void896}897 898declare void @void_func_void() #3899 900declare i32 @llvm.amdgcn.workgroup.id.x() #1901declare i32 @llvm.amdgcn.workgroup.id.y() #1902declare i32 @llvm.amdgcn.workitem.id.x() #1903declare i32 @llvm.amdgcn.workitem.id.y() #1904 905declare void @llvm.amdgcn.s.barrier() #2906 907attributes #0 = { nounwind }908attributes #1 = { nounwind readnone speculatable }909attributes #2 = { convergent nounwind }910attributes #3 = { nounwind noinline }911 912;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:913; GFX1250-UNALIGNED: {{.*}}914