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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -enable-var-scope --check-prefix=CI %s3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=+load-store-opt,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s4; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s5 6; FIXME: We don't get cases where the address was an SGPR because we7; get a copy to the address register for each one.8 9@lds = addrspace(3) global [512 x float] poison, align 410@lds.f64 = addrspace(3) global [512 x double] poison, align 811 12define amdgpu_kernel void @simple_read2_f32(ptr addrspace(1) %out) #0 {13; CI-LABEL: simple_read2_f32:14; CI: ; %bb.0:15; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v016; CI-NEXT: s_mov_b32 m0, -117; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:818; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x019; CI-NEXT: s_mov_b32 s3, 0xf00020; CI-NEXT: s_mov_b32 s2, 021; CI-NEXT: s_waitcnt lgkmcnt(0)22; CI-NEXT: v_add_f32_e32 v2, v1, v223; CI-NEXT: v_mov_b32_e32 v1, 024; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr6425; CI-NEXT: s_endpgm26;27; GFX9-LABEL: simple_read2_f32:28; GFX9: ; %bb.0:29; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v030; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:831; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x032; GFX9-NEXT: s_waitcnt lgkmcnt(0)33; GFX9-NEXT: v_add_f32_e32 v0, v0, v134; GFX9-NEXT: global_store_dword v2, v0, s[0:1]35; GFX9-NEXT: s_endpgm36 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #137 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i38 %val0 = load float, ptr addrspace(3) %arrayidx0, align 439 %add.x = add nsw i32 %x.i, 840 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x41 %val1 = load float, ptr addrspace(3) %arrayidx1, align 442 %sum = fadd float %val0, %val143 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i44 store float %sum, ptr addrspace(1) %out.gep, align 445 ret void46}47 48define amdgpu_kernel void @simple_read2_f32_max_offset(ptr addrspace(1) %out) #0 {49; CI-LABEL: simple_read2_f32_max_offset:50; CI: ; %bb.0:51; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v052; CI-NEXT: s_mov_b32 m0, -153; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:25554; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x055; CI-NEXT: s_mov_b32 s3, 0xf00056; CI-NEXT: s_mov_b32 s2, 057; CI-NEXT: s_waitcnt lgkmcnt(0)58; CI-NEXT: v_add_f32_e32 v2, v1, v259; CI-NEXT: v_mov_b32_e32 v1, 060; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr6461; CI-NEXT: s_endpgm62;63; GFX9-LABEL: simple_read2_f32_max_offset:64; GFX9: ; %bb.0:65; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v066; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:25567; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x068; GFX9-NEXT: s_waitcnt lgkmcnt(0)69; GFX9-NEXT: v_add_f32_e32 v0, v0, v170; GFX9-NEXT: global_store_dword v2, v0, s[0:1]71; GFX9-NEXT: s_endpgm72 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #173 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i74 %val0 = load float, ptr addrspace(3) %arrayidx0, align 475 %add.x = add nsw i32 %x.i, 25576 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x77 %val1 = load float, ptr addrspace(3) %arrayidx1, align 478 %sum = fadd float %val0, %val179 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i80 store float %sum, ptr addrspace(1) %out.gep, align 481 ret void82}83 84define amdgpu_kernel void @simple_read2_f32_too_far(ptr addrspace(1) %out) #0 {85; CI-LABEL: simple_read2_f32_too_far:86; CI: ; %bb.0:87; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v088; CI-NEXT: s_mov_b32 m0, -189; CI-NEXT: ds_read_b32 v1, v090; CI-NEXT: ds_read_b32 v2, v0 offset:102891; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x092; CI-NEXT: s_mov_b32 s3, 0xf00093; CI-NEXT: s_mov_b32 s2, 094; CI-NEXT: s_waitcnt lgkmcnt(0)95; CI-NEXT: v_add_f32_e32 v2, v1, v296; CI-NEXT: v_mov_b32_e32 v1, 097; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr6498; CI-NEXT: s_endpgm99;100; GFX9-LABEL: simple_read2_f32_too_far:101; GFX9: ; %bb.0:102; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0103; GFX9-NEXT: ds_read_b32 v1, v0104; GFX9-NEXT: ds_read_b32 v2, v0 offset:1028105; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0106; GFX9-NEXT: s_waitcnt lgkmcnt(0)107; GFX9-NEXT: v_add_f32_e32 v1, v1, v2108; GFX9-NEXT: global_store_dword v0, v1, s[0:1]109; GFX9-NEXT: s_endpgm110 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1111 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i112 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4113 %add.x = add nsw i32 %x.i, 257114 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x115 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4116 %sum = fadd float %val0, %val1117 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i118 store float %sum, ptr addrspace(1) %out.gep, align 4119 ret void120}121 122define amdgpu_kernel void @simple_read2_f32_x2(ptr addrspace(1) %out) #0 {123; CI-LABEL: simple_read2_f32_x2:124; CI: ; %bb.0:125; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0126; CI-NEXT: s_mov_b32 m0, -1127; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8128; CI-NEXT: ds_read2_b32 v[3:4], v0 offset0:11 offset1:27129; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0130; CI-NEXT: s_mov_b32 s3, 0xf000131; CI-NEXT: s_mov_b32 s2, 0132; CI-NEXT: s_waitcnt lgkmcnt(0)133; CI-NEXT: v_add_f32_e32 v1, v1, v2134; CI-NEXT: v_add_f32_e32 v2, v3, v4135; CI-NEXT: v_add_f32_e32 v2, v1, v2136; CI-NEXT: v_mov_b32_e32 v1, 0137; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64138; CI-NEXT: s_endpgm139;140; GFX9-LABEL: simple_read2_f32_x2:141; GFX9: ; %bb.0:142; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0143; GFX9-NEXT: ds_read2_b32 v[0:1], v4 offset1:8144; GFX9-NEXT: ds_read2_b32 v[2:3], v4 offset0:11 offset1:27145; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0146; GFX9-NEXT: s_waitcnt lgkmcnt(0)147; GFX9-NEXT: v_add_f32_e32 v0, v0, v1148; GFX9-NEXT: v_add_f32_e32 v1, v2, v3149; GFX9-NEXT: v_add_f32_e32 v0, v0, v1150; GFX9-NEXT: global_store_dword v4, v0, s[0:1]151; GFX9-NEXT: s_endpgm152 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1153 %idx.0 = add nsw i32 %tid.x, 0154 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0155 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4156 157 %idx.1 = add nsw i32 %tid.x, 8158 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1159 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4160 %sum.0 = fadd float %val0, %val1161 162 %idx.2 = add nsw i32 %tid.x, 11163 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2164 %val2 = load float, ptr addrspace(3) %arrayidx2, align 4165 166 %idx.3 = add nsw i32 %tid.x, 27167 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3168 %val3 = load float, ptr addrspace(3) %arrayidx3, align 4169 %sum.1 = fadd float %val2, %val3170 171 %sum = fadd float %sum.0, %sum.1172 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %idx.0173 store float %sum, ptr addrspace(1) %out.gep, align 4174 ret void175}176 177; Make sure there is an instruction between the two sets of reads.178define amdgpu_kernel void @simple_read2_f32_x2_barrier(ptr addrspace(1) %out) #0 {179; CI-LABEL: simple_read2_f32_x2_barrier:180; CI: ; %bb.0:181; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0182; CI-NEXT: s_mov_b32 m0, -1183; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8184; CI-NEXT: s_waitcnt lgkmcnt(0)185; CI-NEXT: s_barrier186; CI-NEXT: ds_read2_b32 v[3:4], v0 offset0:11 offset1:27187; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0188; CI-NEXT: s_mov_b32 s3, 0xf000189; CI-NEXT: v_add_f32_e32 v1, v1, v2190; CI-NEXT: s_mov_b32 s2, 0191; CI-NEXT: s_waitcnt lgkmcnt(0)192; CI-NEXT: v_add_f32_e32 v2, v3, v4193; CI-NEXT: v_add_f32_e32 v2, v1, v2194; CI-NEXT: v_mov_b32_e32 v1, 0195; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64196; CI-NEXT: s_endpgm197;198; GFX9-LABEL: simple_read2_f32_x2_barrier:199; GFX9: ; %bb.0:200; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0201; GFX9-NEXT: ds_read2_b32 v[0:1], v4 offset1:8202; GFX9-NEXT: s_waitcnt lgkmcnt(0)203; GFX9-NEXT: s_barrier204; GFX9-NEXT: ds_read2_b32 v[2:3], v4 offset0:11 offset1:27205; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0206; GFX9-NEXT: v_add_f32_e32 v0, v0, v1207; GFX9-NEXT: s_waitcnt lgkmcnt(0)208; GFX9-NEXT: v_add_f32_e32 v1, v2, v3209; GFX9-NEXT: v_add_f32_e32 v0, v0, v1210; GFX9-NEXT: global_store_dword v4, v0, s[0:1]211; GFX9-NEXT: s_endpgm212 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1213 %idx.0 = add nsw i32 %tid.x, 0214 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0215 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4216 217 %idx.1 = add nsw i32 %tid.x, 8218 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1219 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4220 %sum.0 = fadd float %val0, %val1221 222 call void @llvm.amdgcn.s.barrier() #2223 224 %idx.2 = add nsw i32 %tid.x, 11225 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2226 %val2 = load float, ptr addrspace(3) %arrayidx2, align 4227 228 %idx.3 = add nsw i32 %tid.x, 27229 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3230 %val3 = load float, ptr addrspace(3) %arrayidx3, align 4231 %sum.1 = fadd float %val2, %val3232 233 %sum = fadd float %sum.0, %sum.1234 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %idx.0235 store float %sum, ptr addrspace(1) %out.gep, align 4236 ret void237}238 239; For some reason adding something to the base address for the first240; element results in only folding the inner pair.241define amdgpu_kernel void @simple_read2_f32_x2_nonzero_base(ptr addrspace(1) %out) #0 {242; CI-LABEL: simple_read2_f32_x2_nonzero_base:243; CI: ; %bb.0:244; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0245; CI-NEXT: s_mov_b32 m0, -1246; CI-NEXT: ds_read2_b32 v[1:2], v0 offset0:2 offset1:8247; CI-NEXT: ds_read2_b32 v[3:4], v0 offset0:11 offset1:27248; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0249; CI-NEXT: s_mov_b32 s3, 0xf000250; CI-NEXT: s_mov_b32 s2, 0251; CI-NEXT: s_waitcnt lgkmcnt(0)252; CI-NEXT: v_add_f32_e32 v1, v1, v2253; CI-NEXT: v_add_f32_e32 v2, v3, v4254; CI-NEXT: v_add_f32_e32 v2, v1, v2255; CI-NEXT: v_mov_b32_e32 v1, 0256; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 offset:8257; CI-NEXT: s_endpgm258;259; GFX9-LABEL: simple_read2_f32_x2_nonzero_base:260; GFX9: ; %bb.0:261; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0262; GFX9-NEXT: ds_read2_b32 v[0:1], v4 offset0:2 offset1:8263; GFX9-NEXT: ds_read2_b32 v[2:3], v4 offset0:11 offset1:27264; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0265; GFX9-NEXT: s_waitcnt lgkmcnt(0)266; GFX9-NEXT: v_add_f32_e32 v0, v0, v1267; GFX9-NEXT: v_add_f32_e32 v1, v2, v3268; GFX9-NEXT: v_add_f32_e32 v0, v0, v1269; GFX9-NEXT: global_store_dword v4, v0, s[0:1] offset:8270; GFX9-NEXT: s_endpgm271 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1272 %idx.0 = add nsw i32 %tid.x, 2273 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0274 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4275 276 %idx.1 = add nsw i32 %tid.x, 8277 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1278 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4279 %sum.0 = fadd float %val0, %val1280 281 %idx.2 = add nsw i32 %tid.x, 11282 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2283 %val2 = load float, ptr addrspace(3) %arrayidx2, align 4284 285 %idx.3 = add nsw i32 %tid.x, 27286 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3287 %val3 = load float, ptr addrspace(3) %arrayidx3, align 4288 %sum.1 = fadd float %val2, %val3289 290 %sum = fadd float %sum.0, %sum.1291 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %idx.0292 store float %sum, ptr addrspace(1) %out.gep, align 4293 ret void294}295 296; Be careful of vectors of pointers. We don't know if the 2 pointers297; in the vectors are really the same base, so this is not safe to298; merge.299; Base pointers come from different subregister of same super300; register. We can't safely merge this.301define amdgpu_kernel void @read2_ptr_is_subreg_arg_f32(ptr addrspace(1) %out, <2 x ptr addrspace(3)> %lds.ptr) #0 {302; CI-LABEL: read2_ptr_is_subreg_arg_f32:303; CI: ; %bb.0:304; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0305; CI-NEXT: s_mov_b32 m0, -1306; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0307; CI-NEXT: s_waitcnt lgkmcnt(0)308; CI-NEXT: v_mov_b32_e32 v1, s2309; CI-NEXT: v_mov_b32_e32 v2, s3310; CI-NEXT: ds_read_b32 v1, v1 offset:32311; CI-NEXT: ds_read_b32 v2, v2312; CI-NEXT: s_mov_b32 s3, 0xf000313; CI-NEXT: s_mov_b32 s2, 0314; CI-NEXT: s_waitcnt lgkmcnt(0)315; CI-NEXT: v_add_f32_e32 v2, v1, v2316; CI-NEXT: v_mov_b32_e32 v1, 0317; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64318; CI-NEXT: s_endpgm319;320; GFX9-LABEL: read2_ptr_is_subreg_arg_f32:321; GFX9: ; %bb.0:322; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0323; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0324; GFX9-NEXT: s_waitcnt lgkmcnt(0)325; GFX9-NEXT: v_mov_b32_e32 v1, s2326; GFX9-NEXT: v_mov_b32_e32 v2, s3327; GFX9-NEXT: ds_read_b32 v1, v1 offset:32328; GFX9-NEXT: ds_read_b32 v2, v2329; GFX9-NEXT: s_waitcnt lgkmcnt(0)330; GFX9-NEXT: v_add_f32_e32 v1, v1, v2331; GFX9-NEXT: global_store_dword v0, v1, s[0:1]332; GFX9-NEXT: s_endpgm333 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1334 %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0335 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0336 %gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1337 %gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0338 %gep.1 = extractelement <2 x ptr addrspace(3)> %gep, i32 1339 %val0 = load float, ptr addrspace(3) %gep.0, align 4340 %val1 = load float, ptr addrspace(3) %gep.1, align 4341 %add.x = add nsw i32 %x.i, 8342 %sum = fadd float %val0, %val1343 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i344 store float %sum, ptr addrspace(1) %out.gep, align 4345 ret void346}347 348; Apply a constant scalar offset after the pointer vector extract. We349; are rejecting merges that have the same, constant 0 offset, so make350; sure we are really rejecting it because of the different351; subregisters.352define amdgpu_kernel void @read2_ptr_is_subreg_arg_offset_f32(ptr addrspace(1) %out, <2 x ptr addrspace(3)> %lds.ptr) #0 {353; CI-LABEL: read2_ptr_is_subreg_arg_offset_f32:354; CI: ; %bb.0:355; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0356; CI-NEXT: s_mov_b32 m0, -1357; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0358; CI-NEXT: s_waitcnt lgkmcnt(0)359; CI-NEXT: v_mov_b32_e32 v1, s2360; CI-NEXT: v_mov_b32_e32 v2, s3361; CI-NEXT: ds_read_b32 v1, v1 offset:32362; CI-NEXT: ds_read_b32 v2, v2 offset:32363; CI-NEXT: s_mov_b32 s3, 0xf000364; CI-NEXT: s_mov_b32 s2, 0365; CI-NEXT: s_waitcnt lgkmcnt(0)366; CI-NEXT: v_add_f32_e32 v2, v1, v2367; CI-NEXT: v_mov_b32_e32 v1, 0368; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64369; CI-NEXT: s_endpgm370;371; GFX9-LABEL: read2_ptr_is_subreg_arg_offset_f32:372; GFX9: ; %bb.0:373; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0374; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0375; GFX9-NEXT: s_waitcnt lgkmcnt(0)376; GFX9-NEXT: v_mov_b32_e32 v1, s2377; GFX9-NEXT: v_mov_b32_e32 v2, s3378; GFX9-NEXT: ds_read_b32 v1, v1 offset:32379; GFX9-NEXT: ds_read_b32 v2, v2 offset:32380; GFX9-NEXT: s_waitcnt lgkmcnt(0)381; GFX9-NEXT: v_add_f32_e32 v1, v1, v2382; GFX9-NEXT: global_store_dword v0, v1, s[0:1]383; GFX9-NEXT: s_endpgm384 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1385 %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0386 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0387 %gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1388 %gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0389 %gep.1 = extractelement <2 x ptr addrspace(3)> %gep, i32 1390 391 ; Apply an additional offset after the vector that will be more obviously folded.392 %gep.1.offset = getelementptr float, ptr addrspace(3) %gep.1, i32 8393 394 %val0 = load float, ptr addrspace(3) %gep.0, align 4395 %val1 = load float, ptr addrspace(3) %gep.1.offset, align 4396 %add.x = add nsw i32 %x.i, 8397 %sum = fadd float %val0, %val1398 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i399 store float %sum, ptr addrspace(1) %out.gep, align 4400 ret void401}402 403define amdgpu_kernel void @read2_ptr_is_subreg_f32(ptr addrspace(1) %out) #0 {404; CI-LABEL: read2_ptr_is_subreg_f32:405; CI: ; %bb.0:406; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0407; CI-NEXT: s_mov_b32 m0, -1408; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8409; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0410; CI-NEXT: s_mov_b32 s3, 0xf000411; CI-NEXT: s_mov_b32 s2, 0412; CI-NEXT: s_waitcnt lgkmcnt(0)413; CI-NEXT: v_add_f32_e32 v2, v1, v2414; CI-NEXT: v_mov_b32_e32 v1, 0415; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64416; CI-NEXT: s_endpgm417;418; GFX9-LABEL: read2_ptr_is_subreg_f32:419; GFX9: ; %bb.0:420; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0421; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:8422; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0423; GFX9-NEXT: s_waitcnt lgkmcnt(0)424; GFX9-NEXT: v_add_f32_e32 v0, v0, v1425; GFX9-NEXT: global_store_dword v2, v0, s[0:1]426; GFX9-NEXT: s_endpgm427 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1428 %ptr.0 = insertelement <2 x ptr addrspace(3)> poison, ptr addrspace(3) @lds, i32 0429 %ptr.1 = insertelement <2 x ptr addrspace(3)> %ptr.0, ptr addrspace(3) @lds, i32 1430 %x.i.v.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0431 %x.i.v.1 = insertelement <2 x i32> %x.i.v.0, i32 %x.i, i32 1432 %idx = add <2 x i32> %x.i.v.1, <i32 0, i32 8>433 %gep = getelementptr inbounds [512 x float], <2 x ptr addrspace(3)> %ptr.1, <2 x i32> <i32 0, i32 0>, <2 x i32> %idx434 %gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0435 %gep.1 = extractelement <2 x ptr addrspace(3)> %gep, i32 1436 %val0 = load float, ptr addrspace(3) %gep.0, align 4437 %val1 = load float, ptr addrspace(3) %gep.1, align 4438 %add.x = add nsw i32 %x.i, 8439 %sum = fadd float %val0, %val1440 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i441 store float %sum, ptr addrspace(1) %out.gep, align 4442 ret void443}444 445define amdgpu_kernel void @simple_read2_f32_volatile_0(ptr addrspace(1) %out) #0 {446; CI-LABEL: simple_read2_f32_volatile_0:447; CI: ; %bb.0:448; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0449; CI-NEXT: s_mov_b32 m0, -1450; CI-NEXT: ds_read_b32 v1, v0451; CI-NEXT: ds_read_b32 v2, v0 offset:32452; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0453; CI-NEXT: s_mov_b32 s3, 0xf000454; CI-NEXT: s_mov_b32 s2, 0455; CI-NEXT: s_waitcnt lgkmcnt(0)456; CI-NEXT: v_add_f32_e32 v2, v1, v2457; CI-NEXT: v_mov_b32_e32 v1, 0458; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64459; CI-NEXT: s_endpgm460;461; GFX9-LABEL: simple_read2_f32_volatile_0:462; GFX9: ; %bb.0:463; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0464; GFX9-NEXT: ds_read_b32 v1, v0465; GFX9-NEXT: ds_read_b32 v2, v0 offset:32466; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0467; GFX9-NEXT: s_waitcnt lgkmcnt(0)468; GFX9-NEXT: v_add_f32_e32 v1, v1, v2469; GFX9-NEXT: global_store_dword v0, v1, s[0:1]470; GFX9-NEXT: s_endpgm471 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1472 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i473 %val0 = load volatile float, ptr addrspace(3) %arrayidx0, align 4474 %add.x = add nsw i32 %x.i, 8475 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x476 %val1 = load float, ptr addrspace(3) %arrayidx1, align 4477 %sum = fadd float %val0, %val1478 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i479 store float %sum, ptr addrspace(1) %out.gep, align 4480 ret void481}482 483define amdgpu_kernel void @simple_read2_f32_volatile_1(ptr addrspace(1) %out) #0 {484; CI-LABEL: simple_read2_f32_volatile_1:485; CI: ; %bb.0:486; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0487; CI-NEXT: s_mov_b32 m0, -1488; CI-NEXT: ds_read_b32 v1, v0489; CI-NEXT: ds_read_b32 v2, v0 offset:32490; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0491; CI-NEXT: s_mov_b32 s3, 0xf000492; CI-NEXT: s_mov_b32 s2, 0493; CI-NEXT: s_waitcnt lgkmcnt(0)494; CI-NEXT: v_add_f32_e32 v2, v1, v2495; CI-NEXT: v_mov_b32_e32 v1, 0496; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64497; CI-NEXT: s_endpgm498;499; GFX9-LABEL: simple_read2_f32_volatile_1:500; GFX9: ; %bb.0:501; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0502; GFX9-NEXT: ds_read_b32 v1, v0503; GFX9-NEXT: ds_read_b32 v2, v0 offset:32504; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0505; GFX9-NEXT: s_waitcnt lgkmcnt(0)506; GFX9-NEXT: v_add_f32_e32 v1, v1, v2507; GFX9-NEXT: global_store_dword v0, v1, s[0:1]508; GFX9-NEXT: s_endpgm509 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1510 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i511 %val0 = load float, ptr addrspace(3) %arrayidx0, align 4512 %add.x = add nsw i32 %x.i, 8513 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x514 %val1 = load volatile float, ptr addrspace(3) %arrayidx1, align 4515 %sum = fadd float %val0, %val1516 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i517 store float %sum, ptr addrspace(1) %out.gep, align 4518 ret void519}520 521; Can't fold since not correctly aligned.522define amdgpu_kernel void @unaligned_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {523; CI-LABEL: unaligned_read2_f32:524; CI: ; %bb.0:525; CI-NEXT: s_load_dword s2, s[4:5], 0x2526; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0527; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0528; CI-NEXT: s_mov_b32 m0, -1529; CI-NEXT: s_mov_b32 s3, 0xf000530; CI-NEXT: s_waitcnt lgkmcnt(0)531; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v0532; CI-NEXT: ds_read_u8 v2, v1 offset:1533; CI-NEXT: ds_read_u8 v3, v1 offset:34534; CI-NEXT: ds_read_u8 v4, v1 offset:32535; CI-NEXT: ds_read_u8 v5, v1 offset:2536; CI-NEXT: ds_read_u8 v6, v1537; CI-NEXT: ds_read_u8 v7, v1 offset:3538; CI-NEXT: ds_read_u8 v8, v1 offset:33539; CI-NEXT: ds_read_u8 v1, v1 offset:35540; CI-NEXT: s_waitcnt lgkmcnt(7)541; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2542; CI-NEXT: s_waitcnt lgkmcnt(3)543; CI-NEXT: v_or_b32_e32 v2, v2, v6544; CI-NEXT: s_waitcnt lgkmcnt(2)545; CI-NEXT: v_lshlrev_b32_e32 v6, 8, v7546; CI-NEXT: v_or_b32_e32 v5, v6, v5547; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5548; CI-NEXT: s_waitcnt lgkmcnt(0)549; CI-NEXT: v_lshlrev_b32_e32 v1, 8, v1550; CI-NEXT: v_or_b32_e32 v2, v5, v2551; CI-NEXT: v_lshlrev_b32_e32 v5, 8, v8552; CI-NEXT: v_or_b32_e32 v1, v1, v3553; CI-NEXT: v_or_b32_e32 v4, v5, v4554; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1555; CI-NEXT: v_or_b32_e32 v1, v1, v4556; CI-NEXT: v_add_f32_e32 v2, v2, v1557; CI-NEXT: s_mov_b32 s2, 0558; CI-NEXT: v_mov_b32_e32 v1, 0559; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64560; CI-NEXT: s_endpgm561;562; GFX9-ALIGNED-LABEL: unaligned_read2_f32:563; GFX9-ALIGNED: ; %bb.0:564; GFX9-ALIGNED-NEXT: s_load_dword s2, s[4:5], 0x8565; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0566; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v0, 2, v0567; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)568; GFX9-ALIGNED-NEXT: v_add_u32_e32 v1, s2, v0569; GFX9-ALIGNED-NEXT: ds_read_u8 v2, v1570; GFX9-ALIGNED-NEXT: ds_read_u8 v3, v1 offset:1571; GFX9-ALIGNED-NEXT: ds_read_u8 v4, v1 offset:2572; GFX9-ALIGNED-NEXT: ds_read_u8 v5, v1 offset:3573; GFX9-ALIGNED-NEXT: ds_read_u8 v6, v1 offset:32574; GFX9-ALIGNED-NEXT: ds_read_u8 v7, v1 offset:33575; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v1 offset:34576; GFX9-ALIGNED-NEXT: ds_read_u8 v1, v1 offset:35577; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(6)578; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v2, v3, 8, v2579; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(4)580; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v3, v5, 8, v4581; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v2, v3, 16, v2582; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(2)583; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v3, v7, 8, v6584; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)585; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v1, 8, v8586; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v1, 16, v3587; GFX9-ALIGNED-NEXT: v_add_f32_e32 v1, v2, v1588; GFX9-ALIGNED-NEXT: global_store_dword v0, v1, s[0:1]589; GFX9-ALIGNED-NEXT: s_endpgm590;591; GFX9-UNALIGNED-LABEL: unaligned_read2_f32:592; GFX9-UNALIGNED: ; %bb.0:593; GFX9-UNALIGNED-NEXT: s_load_dword s0, s[4:5], 0x8594; GFX9-UNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 2, v0595; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)596; GFX9-UNALIGNED-NEXT: v_add_u32_e32 v0, s0, v2597; GFX9-UNALIGNED-NEXT: ds_read2_b32 v[0:1], v0 offset1:8598; GFX9-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0599; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)600; GFX9-UNALIGNED-NEXT: v_add_f32_e32 v0, v0, v1601; GFX9-UNALIGNED-NEXT: global_store_dword v2, v0, s[0:1]602; GFX9-UNALIGNED-NEXT: s_endpgm603 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1604 %arrayidx0 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %x.i605 %val0 = load float, ptr addrspace(3) %arrayidx0, align 1606 %add.x = add nsw i32 %x.i, 8607 %arrayidx1 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %add.x608 %val1 = load float, ptr addrspace(3) %arrayidx1, align 1609 %sum = fadd float %val0, %val1610 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i611 store float %sum, ptr addrspace(1) %out.gep, align 4612 ret void613}614 615define amdgpu_kernel void @unaligned_offset_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {616; CI-LABEL: unaligned_offset_read2_f32:617; CI: ; %bb.0:618; CI-NEXT: s_load_dword s2, s[4:5], 0x2619; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0620; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0621; CI-NEXT: s_mov_b32 m0, -1622; CI-NEXT: s_mov_b32 s3, 0xf000623; CI-NEXT: s_waitcnt lgkmcnt(0)624; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v0625; CI-NEXT: ds_read_u8 v2, v1 offset:6626; CI-NEXT: ds_read_u8 v3, v1 offset:11627; CI-NEXT: ds_read_u8 v4, v1 offset:9628; CI-NEXT: ds_read_u8 v5, v1 offset:7629; CI-NEXT: ds_read_u8 v6, v1 offset:5630; CI-NEXT: ds_read_u8 v7, v1 offset:8631; CI-NEXT: ds_read_u8 v8, v1 offset:10632; CI-NEXT: ds_read_u8 v1, v1 offset:12633; CI-NEXT: s_waitcnt lgkmcnt(7)634; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2635; CI-NEXT: s_waitcnt lgkmcnt(3)636; CI-NEXT: v_or_b32_e32 v2, v2, v6637; CI-NEXT: s_waitcnt lgkmcnt(2)638; CI-NEXT: v_lshlrev_b32_e32 v6, 8, v7639; CI-NEXT: v_or_b32_e32 v5, v6, v5640; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5641; CI-NEXT: s_waitcnt lgkmcnt(0)642; CI-NEXT: v_lshlrev_b32_e32 v1, 8, v1643; CI-NEXT: v_or_b32_e32 v2, v5, v2644; CI-NEXT: v_lshlrev_b32_e32 v5, 8, v8645; CI-NEXT: v_or_b32_e32 v1, v1, v3646; CI-NEXT: v_or_b32_e32 v4, v5, v4647; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1648; CI-NEXT: v_or_b32_e32 v1, v1, v4649; CI-NEXT: v_add_f32_e32 v2, v2, v1650; CI-NEXT: s_mov_b32 s2, 0651; CI-NEXT: v_mov_b32_e32 v1, 0652; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64653; CI-NEXT: s_endpgm654;655; GFX9-ALIGNED-LABEL: unaligned_offset_read2_f32:656; GFX9-ALIGNED: ; %bb.0:657; GFX9-ALIGNED-NEXT: s_load_dword s2, s[4:5], 0x8658; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0659; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v0, 2, v0660; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)661; GFX9-ALIGNED-NEXT: v_add_u32_e32 v1, s2, v0662; GFX9-ALIGNED-NEXT: ds_read_u8 v2, v1 offset:5663; GFX9-ALIGNED-NEXT: ds_read_u8 v3, v1 offset:6664; GFX9-ALIGNED-NEXT: ds_read_u8 v4, v1 offset:7665; GFX9-ALIGNED-NEXT: ds_read_u8 v5, v1 offset:8666; GFX9-ALIGNED-NEXT: ds_read_u8 v6, v1 offset:9667; GFX9-ALIGNED-NEXT: ds_read_u8 v7, v1 offset:10668; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v1 offset:11669; GFX9-ALIGNED-NEXT: ds_read_u8 v1, v1 offset:12670; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(6)671; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v2, v3, 8, v2672; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(4)673; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v3, v5, 8, v4674; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v2, v3, 16, v2675; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(2)676; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v3, v7, 8, v6677; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)678; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v1, 8, v8679; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v1, 16, v3680; GFX9-ALIGNED-NEXT: v_add_f32_e32 v1, v2, v1681; GFX9-ALIGNED-NEXT: global_store_dword v0, v1, s[0:1]682; GFX9-ALIGNED-NEXT: s_endpgm683;684; GFX9-UNALIGNED-LABEL: unaligned_offset_read2_f32:685; GFX9-UNALIGNED: ; %bb.0:686; GFX9-UNALIGNED-NEXT: s_load_dword s0, s[4:5], 0x8687; GFX9-UNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 2, v0688; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)689; GFX9-UNALIGNED-NEXT: v_add_u32_e32 v0, s0, v2690; GFX9-UNALIGNED-NEXT: ds_read_b64 v[0:1], v0 offset:5691; GFX9-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0692; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)693; GFX9-UNALIGNED-NEXT: v_add_f32_e32 v0, v0, v1694; GFX9-UNALIGNED-NEXT: global_store_dword v2, v0, s[0:1]695; GFX9-UNALIGNED-NEXT: s_endpgm696 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1697 %base = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %x.i698 %addr0.i8 = getelementptr inbounds i8, ptr addrspace(3) %base, i32 5699 %val0 = load float, ptr addrspace(3) %addr0.i8, align 1700 %addr1.i8 = getelementptr inbounds i8, ptr addrspace(3) %base, i32 9701 %val1 = load float, ptr addrspace(3) %addr1.i8, align 1702 %sum = fadd float %val0, %val1703 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i704 store float %sum, ptr addrspace(1) %out.gep, align 4705 ret void706}707 708define amdgpu_kernel void @misaligned_2_simple_read2_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {709; CI-LABEL: misaligned_2_simple_read2_f32:710; CI: ; %bb.0:711; CI-NEXT: s_load_dword s0, s[4:5], 0x2712; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0713; CI-NEXT: s_mov_b32 m0, -1714; CI-NEXT: s_mov_b32 s3, 0xf000715; CI-NEXT: s_mov_b32 s2, 0716; CI-NEXT: s_waitcnt lgkmcnt(0)717; CI-NEXT: v_add_i32_e32 v1, vcc, s0, v0718; CI-NEXT: ds_read_u16 v2, v1 offset:2719; CI-NEXT: ds_read_u16 v3, v1 offset:32720; CI-NEXT: ds_read_u16 v4, v1721; CI-NEXT: ds_read_u16 v1, v1 offset:34722; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0723; CI-NEXT: s_waitcnt lgkmcnt(0)724; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2725; CI-NEXT: v_or_b32_e32 v2, v2, v4726; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1727; CI-NEXT: v_or_b32_e32 v1, v1, v3728; CI-NEXT: v_add_f32_e32 v2, v2, v1729; CI-NEXT: v_mov_b32_e32 v1, 0730; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64731; CI-NEXT: s_endpgm732;733; GFX9-ALIGNED-LABEL: misaligned_2_simple_read2_f32:734; GFX9-ALIGNED: ; %bb.0:735; GFX9-ALIGNED-NEXT: s_load_dword s0, s[4:5], 0x8736; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v0, 2, v0737; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)738; GFX9-ALIGNED-NEXT: v_add_u32_e32 v1, s0, v0739; GFX9-ALIGNED-NEXT: ds_read_u16 v2, v1740; GFX9-ALIGNED-NEXT: ds_read_u16 v3, v1 offset:2741; GFX9-ALIGNED-NEXT: ds_read_u16 v4, v1 offset:32742; GFX9-ALIGNED-NEXT: ds_read_u16 v1, v1 offset:34743; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0744; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)745; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v2, v3, 16, v2746; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v1, 16, v4747; GFX9-ALIGNED-NEXT: v_add_f32_e32 v1, v2, v1748; GFX9-ALIGNED-NEXT: global_store_dword v0, v1, s[0:1]749; GFX9-ALIGNED-NEXT: s_endpgm750;751; GFX9-UNALIGNED-LABEL: misaligned_2_simple_read2_f32:752; GFX9-UNALIGNED: ; %bb.0:753; GFX9-UNALIGNED-NEXT: s_load_dword s0, s[4:5], 0x8754; GFX9-UNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 2, v0755; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)756; GFX9-UNALIGNED-NEXT: v_add_u32_e32 v0, s0, v2757; GFX9-UNALIGNED-NEXT: ds_read2_b32 v[0:1], v0 offset1:8758; GFX9-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0759; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)760; GFX9-UNALIGNED-NEXT: v_add_f32_e32 v0, v0, v1761; GFX9-UNALIGNED-NEXT: global_store_dword v2, v0, s[0:1]762; GFX9-UNALIGNED-NEXT: s_endpgm763 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1764 %arrayidx0 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %x.i765 %val0 = load float, ptr addrspace(3) %arrayidx0, align 2766 %add.x = add nsw i32 %x.i, 8767 %arrayidx1 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %add.x768 %val1 = load float, ptr addrspace(3) %arrayidx1, align 2769 %sum = fadd float %val0, %val1770 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i771 store float %sum, ptr addrspace(1) %out.gep, align 4772 ret void773}774 775define amdgpu_kernel void @simple_read2_f64(ptr addrspace(1) %out) #0 {776; CI-LABEL: simple_read2_f64:777; CI: ; %bb.0:778; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v0779; CI-NEXT: s_mov_b32 m0, -1780; CI-NEXT: ds_read2_b64 v[0:3], v4 offset1:8781; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0782; CI-NEXT: s_mov_b32 s3, 0xf000783; CI-NEXT: s_mov_b32 s2, 0784; CI-NEXT: v_mov_b32_e32 v5, 0785; CI-NEXT: s_waitcnt lgkmcnt(0)786; CI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]787; CI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64788; CI-NEXT: s_endpgm789;790; GFX9-LABEL: simple_read2_f64:791; GFX9: ; %bb.0:792; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0793; GFX9-NEXT: ds_read2_b64 v[0:3], v4 offset1:8794; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0795; GFX9-NEXT: s_waitcnt lgkmcnt(0)796; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]797; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]798; GFX9-NEXT: s_endpgm799 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1800 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i801 %val0 = load double, ptr addrspace(3) %arrayidx0, align 8802 %add.x = add nsw i32 %x.i, 8803 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x804 %val1 = load double, ptr addrspace(3) %arrayidx1, align 8805 %sum = fadd double %val0, %val1806 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i807 store double %sum, ptr addrspace(1) %out.gep, align 8808 ret void809}810 811define amdgpu_kernel void @simple_read2_f64_max_offset(ptr addrspace(1) %out) #0 {812; CI-LABEL: simple_read2_f64_max_offset:813; CI: ; %bb.0:814; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v0815; CI-NEXT: s_mov_b32 m0, -1816; CI-NEXT: ds_read2_b64 v[0:3], v4 offset1:255817; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0818; CI-NEXT: s_mov_b32 s3, 0xf000819; CI-NEXT: s_mov_b32 s2, 0820; CI-NEXT: v_mov_b32_e32 v5, 0821; CI-NEXT: s_waitcnt lgkmcnt(0)822; CI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]823; CI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64824; CI-NEXT: s_endpgm825;826; GFX9-LABEL: simple_read2_f64_max_offset:827; GFX9: ; %bb.0:828; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0829; GFX9-NEXT: ds_read2_b64 v[0:3], v4 offset1:255830; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0831; GFX9-NEXT: s_waitcnt lgkmcnt(0)832; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]833; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]834; GFX9-NEXT: s_endpgm835 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1836 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i837 %val0 = load double, ptr addrspace(3) %arrayidx0, align 8838 %add.x = add nsw i32 %x.i, 255839 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x840 %val1 = load double, ptr addrspace(3) %arrayidx1, align 8841 %sum = fadd double %val0, %val1842 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i843 store double %sum, ptr addrspace(1) %out.gep, align 8844 ret void845}846 847define amdgpu_kernel void @simple_read2_f64_too_far(ptr addrspace(1) %out) #0 {848; CI-LABEL: simple_read2_f64_too_far:849; CI: ; %bb.0:850; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0851; CI-NEXT: s_mov_b32 m0, -1852; CI-NEXT: ds_read_b64 v[1:2], v0853; CI-NEXT: ds_read_b64 v[3:4], v0 offset:2056854; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0855; CI-NEXT: s_mov_b32 s3, 0xf000856; CI-NEXT: s_mov_b32 s2, 0857; CI-NEXT: s_waitcnt lgkmcnt(0)858; CI-NEXT: v_add_f64 v[2:3], v[1:2], v[3:4]859; CI-NEXT: v_mov_b32_e32 v1, 0860; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64861; CI-NEXT: s_endpgm862;863; GFX9-LABEL: simple_read2_f64_too_far:864; GFX9: ; %bb.0:865; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0866; GFX9-NEXT: ds_read_b64 v[0:1], v4867; GFX9-NEXT: ds_read_b64 v[2:3], v4 offset:2056868; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0869; GFX9-NEXT: s_waitcnt lgkmcnt(0)870; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]871; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]872; GFX9-NEXT: s_endpgm873 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1874 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i875 %val0 = load double, ptr addrspace(3) %arrayidx0, align 8876 %add.x = add nsw i32 %x.i, 257877 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x878 %val1 = load double, ptr addrspace(3) %arrayidx1, align 8879 %sum = fadd double %val0, %val1880 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i881 store double %sum, ptr addrspace(1) %out.gep, align 8882 ret void883}884 885; Alignment only 4886define amdgpu_kernel void @misaligned_read2_f64(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {887; CI-LABEL: misaligned_read2_f64:888; CI: ; %bb.0:889; CI-NEXT: s_load_dword s0, s[4:5], 0x2890; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0891; CI-NEXT: s_mov_b32 m0, -1892; CI-NEXT: s_mov_b32 s3, 0xf000893; CI-NEXT: s_mov_b32 s2, 0894; CI-NEXT: s_waitcnt lgkmcnt(0)895; CI-NEXT: v_add_i32_e32 v3, vcc, s0, v0896; CI-NEXT: ds_read2_b32 v[1:2], v3 offset1:1897; CI-NEXT: ds_read2_b32 v[3:4], v3 offset0:14 offset1:15898; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0899; CI-NEXT: s_waitcnt lgkmcnt(0)900; CI-NEXT: v_add_f64 v[2:3], v[1:2], v[3:4]901; CI-NEXT: v_mov_b32_e32 v1, 0902; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64903; CI-NEXT: s_endpgm904;905; GFX9-LABEL: misaligned_read2_f64:906; GFX9: ; %bb.0:907; GFX9-NEXT: s_load_dword s0, s[4:5], 0x8908; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0909; GFX9-NEXT: s_waitcnt lgkmcnt(0)910; GFX9-NEXT: v_add_u32_e32 v2, s0, v4911; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:1912; GFX9-NEXT: ds_read2_b32 v[2:3], v2 offset0:14 offset1:15913; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0914; GFX9-NEXT: s_waitcnt lgkmcnt(0)915; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]916; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]917; GFX9-NEXT: s_endpgm918 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1919 %arrayidx0 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %x.i920 %val0 = load double, ptr addrspace(3) %arrayidx0, align 4921 %add.x = add nsw i32 %x.i, 7922 %arrayidx1 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %add.x923 %val1 = load double, ptr addrspace(3) %arrayidx1, align 4924 %sum = fadd double %val0, %val1925 %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i32 %x.i926 store double %sum, ptr addrspace(1) %out.gep, align 4927 ret void928}929 930@foo = addrspace(3) global [4 x i32] poison, align 4931 932define amdgpu_kernel void @load_constant_adjacent_offsets(ptr addrspace(1) %out) {933; CI-LABEL: load_constant_adjacent_offsets:934; CI: ; %bb.0:935; CI-NEXT: v_mov_b32_e32 v0, 0936; CI-NEXT: s_mov_b32 m0, -1937; CI-NEXT: ds_read_b64 v[0:1], v0938; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0939; CI-NEXT: s_mov_b32 s3, 0xf000940; CI-NEXT: s_mov_b32 s2, -1941; CI-NEXT: s_waitcnt lgkmcnt(0)942; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v1943; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0944; CI-NEXT: s_endpgm945;946; GFX9-LABEL: load_constant_adjacent_offsets:947; GFX9: ; %bb.0:948; GFX9-NEXT: v_mov_b32_e32 v2, 0949; GFX9-NEXT: ds_read_b64 v[0:1], v2950; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0951; GFX9-NEXT: s_waitcnt lgkmcnt(0)952; GFX9-NEXT: v_add_u32_e32 v0, v0, v1953; GFX9-NEXT: global_store_dword v2, v0, s[0:1]954; GFX9-NEXT: s_endpgm955 %val0 = load i32, ptr addrspace(3) @foo, align 4956 %val1 = load i32, ptr addrspace(3) getelementptr inbounds ([4 x i32], ptr addrspace(3) @foo, i32 0, i32 1), align 4957 %sum = add i32 %val0, %val1958 store i32 %sum, ptr addrspace(1) %out, align 4959 ret void960}961 962define amdgpu_kernel void @load_constant_disjoint_offsets(ptr addrspace(1) %out) {963; CI-LABEL: load_constant_disjoint_offsets:964; CI: ; %bb.0:965; CI-NEXT: v_mov_b32_e32 v0, 0966; CI-NEXT: s_mov_b32 m0, -1967; CI-NEXT: ds_read2_b32 v[0:1], v0 offset1:2968; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0969; CI-NEXT: s_mov_b32 s3, 0xf000970; CI-NEXT: s_mov_b32 s2, -1971; CI-NEXT: s_waitcnt lgkmcnt(0)972; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v1973; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0974; CI-NEXT: s_endpgm975;976; GFX9-LABEL: load_constant_disjoint_offsets:977; GFX9: ; %bb.0:978; GFX9-NEXT: v_mov_b32_e32 v2, 0979; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:2980; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0981; GFX9-NEXT: s_waitcnt lgkmcnt(0)982; GFX9-NEXT: v_add_u32_e32 v0, v0, v1983; GFX9-NEXT: global_store_dword v2, v0, s[0:1]984; GFX9-NEXT: s_endpgm985 %val0 = load i32, ptr addrspace(3) @foo, align 4986 %val1 = load i32, ptr addrspace(3) getelementptr inbounds ([4 x i32], ptr addrspace(3) @foo, i32 0, i32 2), align 4987 %sum = add i32 %val0, %val1988 store i32 %sum, ptr addrspace(1) %out, align 4989 ret void990}991 992@bar = addrspace(3) global [4 x i64] poison, align 4993 994define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %out) {995; CI-LABEL: load_misaligned64_constant_offsets:996; CI: ; %bb.0:997; CI-NEXT: v_mov_b32_e32 v0, 0998; CI-NEXT: s_mov_b32 m0, -1999; CI-NEXT: ds_read_b128 v[0:3], v01000; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01001; CI-NEXT: s_mov_b32 s3, 0xf0001002; CI-NEXT: s_mov_b32 s2, -11003; CI-NEXT: s_waitcnt lgkmcnt(0)1004; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v21005; CI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc1006; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01007; CI-NEXT: s_endpgm1008;1009; GFX9-LABEL: load_misaligned64_constant_offsets:1010; GFX9: ; %bb.0:1011; GFX9-NEXT: v_mov_b32_e32 v4, 01012; GFX9-NEXT: ds_read_b128 v[0:3], v41013; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01014; GFX9-NEXT: s_waitcnt lgkmcnt(0)1015; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v21016; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc1017; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]1018; GFX9-NEXT: s_endpgm1019 %val0 = load i64, ptr addrspace(3) @bar, align 41020 %val1 = load i64, ptr addrspace(3) getelementptr inbounds ([4 x i64], ptr addrspace(3) @bar, i32 0, i32 1), align 41021 %sum = add i64 %val0, %val11022 store i64 %sum, ptr addrspace(1) %out, align 81023 ret void1024}1025 1026@bar.large = addrspace(3) global [4096 x i64] poison, align 41027 1028define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspace(1) %out) {1029; CI-LABEL: load_misaligned64_constant_large_offsets:1030; CI: ; %bb.0:1031; CI-NEXT: v_mov_b32_e32 v2, 01032; CI-NEXT: s_mov_b32 m0, -11033; CI-NEXT: ds_read_b64 v[0:1], v2 offset:163841034; CI-NEXT: ds_read_b64 v[2:3], v2 offset:327601035; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01036; CI-NEXT: s_mov_b32 s3, 0xf0001037; CI-NEXT: s_mov_b32 s2, -11038; CI-NEXT: s_waitcnt lgkmcnt(0)1039; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v21040; CI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc1041; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01042; CI-NEXT: s_endpgm1043;1044; GFX9-LABEL: load_misaligned64_constant_large_offsets:1045; GFX9: ; %bb.0:1046; GFX9-NEXT: v_mov_b32_e32 v4, 01047; GFX9-NEXT: ds_read_b64 v[0:1], v4 offset:163841048; GFX9-NEXT: ds_read_b64 v[2:3], v4 offset:327601049; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01050; GFX9-NEXT: s_waitcnt lgkmcnt(0)1051; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v21052; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc1053; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]1054; GFX9-NEXT: s_endpgm1055 %val0 = load i64, ptr addrspace(3) getelementptr inbounds ([4096 x i64], ptr addrspace(3) @bar.large, i32 0, i32 2048), align 41056 %val1 = load i64, ptr addrspace(3) getelementptr inbounds ([4096 x i64], ptr addrspace(3) @bar.large, i32 0, i32 4095), align 41057 %sum = add i64 %val0, %val11058 store i64 %sum, ptr addrspace(1) %out, align 81059 ret void1060}1061 1062@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] poison, align 41063@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] poison, align 41064 1065define amdgpu_kernel void @sgemm_inner_loop_read2_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb) #0 {1066; CI-LABEL: sgemm_inner_loop_read2_sequence:1067; CI: ; %bb.0:1068; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01069; CI-NEXT: s_lshl_b32 s4, s8, 21070; CI-NEXT: s_add_i32 s5, s4, 0xc201071; CI-NEXT: s_addk_i32 s4, 0xc601072; CI-NEXT: v_mov_b32_e32 v0, s51073; CI-NEXT: v_mov_b32_e32 v2, s41074; CI-NEXT: v_lshlrev_b32_e32 v8, 2, v11075; CI-NEXT: s_mov_b32 m0, -11076; CI-NEXT: ds_read2_b32 v[0:1], v0 offset1:11077; CI-NEXT: ds_read2_b32 v[2:3], v2 offset1:11078; CI-NEXT: ds_read2_b32 v[4:5], v8 offset1:11079; CI-NEXT: ds_read2_b32 v[6:7], v8 offset0:32 offset1:331080; CI-NEXT: ds_read2_b32 v[8:9], v8 offset0:64 offset1:651081; CI-NEXT: s_waitcnt lgkmcnt(0)1082; CI-NEXT: v_add_f32_e32 v0, v0, v11083; CI-NEXT: v_add_f32_e32 v0, v0, v21084; CI-NEXT: v_add_f32_e32 v0, v0, v31085; CI-NEXT: v_add_f32_e32 v0, v0, v41086; CI-NEXT: v_add_f32_e32 v0, v0, v51087; CI-NEXT: v_add_f32_e32 v0, v0, v61088; CI-NEXT: v_add_f32_e32 v0, v0, v71089; CI-NEXT: v_add_f32_e32 v0, v0, v81090; CI-NEXT: s_mov_b32 s3, 0xf0001091; CI-NEXT: s_mov_b32 s2, -11092; CI-NEXT: v_add_f32_e32 v0, v0, v91093; CI-NEXT: buffer_store_dword v0, off, s[0:3], 01094; CI-NEXT: s_endpgm1095;1096; GFX9-LABEL: sgemm_inner_loop_read2_sequence:1097; GFX9: ; %bb.0:1098; GFX9-NEXT: s_lshl_b32 s2, s8, 21099; GFX9-NEXT: s_add_i32 s3, s2, 0xc201100; GFX9-NEXT: s_addk_i32 s2, 0xc601101; GFX9-NEXT: v_mov_b32_e32 v0, s31102; GFX9-NEXT: v_mov_b32_e32 v2, s21103; GFX9-NEXT: v_lshlrev_b32_e32 v8, 2, v11104; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:11105; GFX9-NEXT: ds_read2_b32 v[2:3], v2 offset1:11106; GFX9-NEXT: ds_read2_b32 v[4:5], v8 offset1:11107; GFX9-NEXT: ds_read2_b32 v[6:7], v8 offset0:32 offset1:331108; GFX9-NEXT: ds_read2_b32 v[8:9], v8 offset0:64 offset1:651109; GFX9-NEXT: s_waitcnt lgkmcnt(4)1110; GFX9-NEXT: v_add_f32_e32 v0, v0, v11111; GFX9-NEXT: s_waitcnt lgkmcnt(3)1112; GFX9-NEXT: v_add_f32_e32 v0, v0, v21113; GFX9-NEXT: v_add_f32_e32 v0, v0, v31114; GFX9-NEXT: s_waitcnt lgkmcnt(2)1115; GFX9-NEXT: v_add_f32_e32 v0, v0, v41116; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01117; GFX9-NEXT: v_add_f32_e32 v0, v0, v51118; GFX9-NEXT: s_waitcnt lgkmcnt(0)1119; GFX9-NEXT: v_add_f32_e32 v0, v0, v61120; GFX9-NEXT: v_add_f32_e32 v0, v0, v71121; GFX9-NEXT: v_add_f32_e32 v0, v0, v81122; GFX9-NEXT: v_mov_b32_e32 v10, 01123; GFX9-NEXT: v_add_f32_e32 v0, v0, v91124; GFX9-NEXT: global_store_dword v10, v0, s[0:1]1125; GFX9-NEXT: s_endpgm1126 %x.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #11127 %y.i = tail call i32 @llvm.amdgcn.workitem.id.y() #11128 %arrayidx44 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %x.i1129 %tmp16 = load float, ptr addrspace(3) %arrayidx44, align 41130 %add47 = add nsw i32 %x.i, 11131 %arrayidx48 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add471132 %tmp17 = load float, ptr addrspace(3) %arrayidx48, align 41133 %add51 = add nsw i32 %x.i, 161134 %arrayidx52 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add511135 %tmp18 = load float, ptr addrspace(3) %arrayidx52, align 41136 %add55 = add nsw i32 %x.i, 171137 %arrayidx56 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add551138 %tmp19 = load float, ptr addrspace(3) %arrayidx56, align 41139 %arrayidx60 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %y.i1140 %tmp20 = load float, ptr addrspace(3) %arrayidx60, align 41141 %add63 = add nsw i32 %y.i, 11142 %arrayidx64 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add631143 %tmp21 = load float, ptr addrspace(3) %arrayidx64, align 41144 %add67 = add nsw i32 %y.i, 321145 %arrayidx68 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add671146 %tmp22 = load float, ptr addrspace(3) %arrayidx68, align 41147 %add71 = add nsw i32 %y.i, 331148 %arrayidx72 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add711149 %tmp23 = load float, ptr addrspace(3) %arrayidx72, align 41150 %add75 = add nsw i32 %y.i, 641151 %arrayidx76 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add751152 %tmp24 = load float, ptr addrspace(3) %arrayidx76, align 41153 %add79 = add nsw i32 %y.i, 651154 %arrayidx80 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add791155 %tmp25 = load float, ptr addrspace(3) %arrayidx80, align 41156 %sum.0 = fadd float %tmp16, %tmp171157 %sum.1 = fadd float %sum.0, %tmp181158 %sum.2 = fadd float %sum.1, %tmp191159 %sum.3 = fadd float %sum.2, %tmp201160 %sum.4 = fadd float %sum.3, %tmp211161 %sum.5 = fadd float %sum.4, %tmp221162 %sum.6 = fadd float %sum.5, %tmp231163 %sum.7 = fadd float %sum.6, %tmp241164 %sum.8 = fadd float %sum.7, %tmp251165 store float %sum.8, ptr addrspace(1) %C, align 41166 ret void1167}1168 1169define amdgpu_kernel void @misaligned_read2_v2i32(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {1170; CI-LABEL: misaligned_read2_v2i32:1171; CI: ; %bb.0:1172; CI-NEXT: s_load_dword s2, s[4:5], 0x21173; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01174; CI-NEXT: s_mov_b32 m0, -11175; CI-NEXT: s_mov_b32 s3, 0xf0001176; CI-NEXT: s_waitcnt lgkmcnt(0)1177; CI-NEXT: v_mov_b32_e32 v0, s21178; CI-NEXT: ds_read2_b32 v[0:1], v0 offset1:11179; CI-NEXT: s_mov_b32 s2, -11180; CI-NEXT: s_waitcnt lgkmcnt(0)1181; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01182; CI-NEXT: s_endpgm1183;1184; GFX9-LABEL: misaligned_read2_v2i32:1185; GFX9: ; %bb.0:1186; GFX9-NEXT: s_load_dword s2, s[4:5], 0x81187; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01188; GFX9-NEXT: v_mov_b32_e32 v2, 01189; GFX9-NEXT: s_waitcnt lgkmcnt(0)1190; GFX9-NEXT: v_mov_b32_e32 v0, s21191; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:11192; GFX9-NEXT: s_waitcnt lgkmcnt(0)1193; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]1194; GFX9-NEXT: s_endpgm1195 %load = load <2 x i32>, ptr addrspace(3) %in, align 41196 store <2 x i32> %load, ptr addrspace(1) %out, align 81197 ret void1198}1199 1200define amdgpu_kernel void @misaligned_read2_i64(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {1201; CI-LABEL: misaligned_read2_i64:1202; CI: ; %bb.0:1203; CI-NEXT: s_load_dword s2, s[4:5], 0x21204; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01205; CI-NEXT: s_mov_b32 m0, -11206; CI-NEXT: s_mov_b32 s3, 0xf0001207; CI-NEXT: s_waitcnt lgkmcnt(0)1208; CI-NEXT: v_mov_b32_e32 v0, s21209; CI-NEXT: ds_read2_b32 v[0:1], v0 offset1:11210; CI-NEXT: s_mov_b32 s2, -11211; CI-NEXT: s_waitcnt lgkmcnt(0)1212; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01213; CI-NEXT: s_endpgm1214;1215; GFX9-LABEL: misaligned_read2_i64:1216; GFX9: ; %bb.0:1217; GFX9-NEXT: s_load_dword s2, s[4:5], 0x81218; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01219; GFX9-NEXT: v_mov_b32_e32 v2, 01220; GFX9-NEXT: s_waitcnt lgkmcnt(0)1221; GFX9-NEXT: v_mov_b32_e32 v0, s21222; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:11223; GFX9-NEXT: s_waitcnt lgkmcnt(0)1224; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]1225; GFX9-NEXT: s_endpgm1226 %load = load i64, ptr addrspace(3) %in, align 41227 store i64 %load, ptr addrspace(1) %out, align 81228 ret void1229}1230 1231define amdgpu_kernel void @ds_read_diff_base_interleaving(1232; CI-LABEL: ds_read_diff_base_interleaving:1233; CI: ; %bb.0: ; %bb1234; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x21235; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x01236; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v11237; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v01238; CI-NEXT: s_mov_b32 m0, -11239; CI-NEXT: s_waitcnt lgkmcnt(0)1240; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v11241; CI-NEXT: v_add_i32_e32 v3, vcc, s1, v01242; CI-NEXT: v_add_i32_e32 v4, vcc, s2, v11243; CI-NEXT: v_add_i32_e32 v6, vcc, s3, v01244; CI-NEXT: ds_read2_b32 v[0:1], v2 offset1:11245; CI-NEXT: ds_read2_b32 v[2:3], v3 offset1:41246; CI-NEXT: ds_read2_b32 v[4:5], v4 offset1:11247; CI-NEXT: ds_read2_b32 v[6:7], v6 offset1:41248; CI-NEXT: s_mov_b32 s7, 0xf0001249; CI-NEXT: s_mov_b32 s6, -11250; CI-NEXT: s_waitcnt lgkmcnt(2)1251; CI-NEXT: v_mul_f32_e32 v0, v0, v21252; CI-NEXT: v_add_f32_e32 v0, 2.0, v01253; CI-NEXT: s_waitcnt lgkmcnt(0)1254; CI-NEXT: v_mul_f32_e32 v2, v4, v61255; CI-NEXT: v_sub_f32_e32 v0, v0, v21256; CI-NEXT: v_mul_f32_e32 v1, v1, v31257; CI-NEXT: v_sub_f32_e32 v0, v0, v11258; CI-NEXT: v_mul_f32_e32 v1, v5, v71259; CI-NEXT: v_sub_f32_e32 v0, v0, v11260; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:401261; CI-NEXT: s_endpgm1262;1263; GFX9-LABEL: ds_read_diff_base_interleaving:1264; GFX9: ; %bb.0: ; %bb1265; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x81266; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v11267; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v01268; GFX9-NEXT: v_mov_b32_e32 v8, 01269; GFX9-NEXT: s_waitcnt lgkmcnt(0)1270; GFX9-NEXT: v_add_u32_e32 v2, s0, v11271; GFX9-NEXT: v_add_u32_e32 v3, s1, v01272; GFX9-NEXT: v_add_u32_e32 v4, s2, v11273; GFX9-NEXT: v_add_u32_e32 v6, s3, v01274; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:11275; GFX9-NEXT: ds_read2_b32 v[2:3], v3 offset1:41276; GFX9-NEXT: ds_read2_b32 v[4:5], v4 offset1:11277; GFX9-NEXT: ds_read2_b32 v[6:7], v6 offset1:41278; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01279; GFX9-NEXT: s_waitcnt lgkmcnt(0)1280; GFX9-NEXT: v_mul_f32_e32 v0, v0, v21281; GFX9-NEXT: v_add_f32_e32 v0, 2.0, v01282; GFX9-NEXT: v_mul_f32_e32 v2, v4, v61283; GFX9-NEXT: v_sub_f32_e32 v0, v0, v21284; GFX9-NEXT: v_mul_f32_e32 v1, v1, v31285; GFX9-NEXT: v_sub_f32_e32 v0, v0, v11286; GFX9-NEXT: v_mul_f32_e32 v1, v5, v71287; GFX9-NEXT: v_sub_f32_e32 v0, v0, v11288; GFX9-NEXT: global_store_dword v8, v0, s[0:1] offset:401289; GFX9-NEXT: s_endpgm1290 ptr addrspace(1) nocapture %arg,1291 ptr addrspace(3) %arg1,1292 ptr addrspace(3) %arg2,1293 ptr addrspace(3) %arg3,1294 ptr addrspace(3) %arg4) #1 {1295bb:1296 %tmp = getelementptr float, ptr addrspace(1) %arg, i64 101297 %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.x() #21298 %tmp6 = tail call i32 @llvm.amdgcn.workitem.id.y() #21299 %tmp7 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg1, i32 0, i32 %tmp6, i32 01300 %tmp8 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg2, i32 0, i32 0, i32 %tmp51301 %tmp9 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg3, i32 0, i32 %tmp6, i32 01302 %tmp10 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg4, i32 0, i32 0, i32 %tmp51303 %tmp11 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg1, i32 0, i32 %tmp6, i32 11304 %tmp12 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg2, i32 0, i32 1, i32 %tmp51305 %tmp13 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg3, i32 0, i32 %tmp6, i32 11306 %tmp14 = getelementptr [4 x [4 x float]], ptr addrspace(3) %arg4, i32 0, i32 1, i32 %tmp51307 %tmp15 = load float, ptr addrspace(3) %tmp71308 %tmp16 = load float, ptr addrspace(3) %tmp81309 %tmp17 = fmul float %tmp15, %tmp161310 %tmp18 = fadd float 2.000000e+00, %tmp171311 %tmp19 = load float, ptr addrspace(3) %tmp91312 %tmp20 = load float, ptr addrspace(3) %tmp101313 %tmp21 = fmul float %tmp19, %tmp201314 %tmp22 = fsub float %tmp18, %tmp211315 %tmp23 = load float, ptr addrspace(3) %tmp111316 %tmp24 = load float, ptr addrspace(3) %tmp121317 %tmp25 = fmul float %tmp23, %tmp241318 %tmp26 = fsub float %tmp22, %tmp251319 %tmp27 = load float, ptr addrspace(3) %tmp131320 %tmp28 = load float, ptr addrspace(3) %tmp141321 %tmp29 = fmul float %tmp27, %tmp281322 %tmp30 = fsub float %tmp26, %tmp291323 store float %tmp30, ptr addrspace(1) %tmp1324 ret void1325}1326 1327define amdgpu_kernel void @ds_read_call_read(ptr addrspace(1) %out, ptr addrspace(3) %arg) {1328; CI-LABEL: ds_read_call_read:1329; CI: ; %bb.0:1330; CI-NEXT: s_getpc_b64 s[48:49]1331; CI-NEXT: s_mov_b32 s48, s01332; CI-NEXT: s_load_dwordx4 s[48:51], s[48:49], 0x01333; CI-NEXT: s_mov_b32 s14, s101334; CI-NEXT: v_lshlrev_b32_e32 v3, 2, v01335; CI-NEXT: s_mov_b32 m0, -11336; CI-NEXT: s_mov_b32 s12, s81337; CI-NEXT: s_waitcnt lgkmcnt(0)1338; CI-NEXT: s_add_u32 s48, s48, s111339; CI-NEXT: s_mov_b64 s[10:11], s[6:7]1340; CI-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x01341; CI-NEXT: s_load_dword s6, s[4:5], 0x21342; CI-NEXT: s_addc_u32 s49, s49, 01343; CI-NEXT: s_add_u32 s8, s4, 121344; CI-NEXT: v_lshlrev_b32_e32 v1, 10, v11345; CI-NEXT: s_mov_b32 s13, s91346; CI-NEXT: s_waitcnt lgkmcnt(0)1347; CI-NEXT: v_add_i32_e32 v40, vcc, s6, v31348; CI-NEXT: ds_read_b32 v41, v401349; CI-NEXT: s_addc_u32 s9, s5, 01350; CI-NEXT: v_lshlrev_b32_e32 v2, 20, v21351; CI-NEXT: v_or_b32_e32 v0, v0, v11352; CI-NEXT: s_mov_b64 s[4:5], s[0:1]1353; CI-NEXT: s_mov_b64 s[6:7], s[2:3]1354; CI-NEXT: s_mov_b64 s[0:1], s[48:49]1355; CI-NEXT: s_mov_b32 s17, void_func_void@abs32@hi1356; CI-NEXT: s_mov_b32 s16, void_func_void@abs32@lo1357; CI-NEXT: v_or_b32_e32 v31, v0, v21358; CI-NEXT: s_mov_b64 s[2:3], s[50:51]1359; CI-NEXT: s_mov_b32 s32, 01360; CI-NEXT: s_mov_b32 s39, 0xf0001361; CI-NEXT: s_mov_b32 s38, -11362; CI-NEXT: s_swappc_b64 s[30:31], s[16:17]1363; CI-NEXT: ds_read_b32 v0, v40 offset:41364; CI-NEXT: s_waitcnt lgkmcnt(0)1365; CI-NEXT: v_add_i32_e32 v0, vcc, v41, v01366; CI-NEXT: buffer_store_dword v0, off, s[36:39], 01367; CI-NEXT: s_endpgm1368;1369; GFX9-LABEL: ds_read_call_read:1370; GFX9: ; %bb.0:1371; GFX9-NEXT: s_getpc_b64 s[36:37]1372; GFX9-NEXT: s_mov_b32 s36, s01373; GFX9-NEXT: s_load_dwordx4 s[36:39], s[36:37], 0x01374; GFX9-NEXT: s_mov_b32 s14, s101375; GFX9-NEXT: s_mov_b32 s12, s81376; GFX9-NEXT: s_mov_b32 s13, s91377; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v21378; GFX9-NEXT: s_waitcnt lgkmcnt(0)1379; GFX9-NEXT: s_add_u32 s36, s36, s111380; GFX9-NEXT: s_mov_b64 s[10:11], s[6:7]1381; GFX9-NEXT: s_load_dword s6, s[4:5], 0x81382; GFX9-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x01383; GFX9-NEXT: s_addc_u32 s37, s37, 01384; GFX9-NEXT: s_add_u32 s8, s4, 121385; GFX9-NEXT: s_addc_u32 s9, s5, 01386; GFX9-NEXT: s_waitcnt lgkmcnt(0)1387; GFX9-NEXT: v_lshl_add_u32 v41, v0, 2, s61388; GFX9-NEXT: ds_read_b32 v42, v411389; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v11390; GFX9-NEXT: s_mov_b64 s[4:5], s[0:1]1391; GFX9-NEXT: s_mov_b64 s[6:7], s[2:3]1392; GFX9-NEXT: s_mov_b64 s[0:1], s[36:37]1393; GFX9-NEXT: s_mov_b32 s17, void_func_void@abs32@hi1394; GFX9-NEXT: s_mov_b32 s16, void_func_void@abs32@lo1395; GFX9-NEXT: v_or3_b32 v31, v0, v1, v21396; GFX9-NEXT: s_mov_b64 s[2:3], s[38:39]1397; GFX9-NEXT: s_mov_b32 s32, 01398; GFX9-NEXT: v_mov_b32_e32 v40, 01399; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17]1400; GFX9-NEXT: ds_read_b32 v0, v41 offset:41401; GFX9-NEXT: s_waitcnt lgkmcnt(0)1402; GFX9-NEXT: v_add_u32_e32 v0, v42, v01403; GFX9-NEXT: global_store_dword v40, v0, s[34:35]1404; GFX9-NEXT: s_endpgm1405 %x = call i32 @llvm.amdgcn.workitem.id.x()1406 %arrayidx0 = getelementptr i32, ptr addrspace(3) %arg, i32 %x1407 %arrayidx1 = getelementptr i32, ptr addrspace(3) %arrayidx0, i32 11408 %v0 = load i32, ptr addrspace(3) %arrayidx0, align 41409 call void @void_func_void()1410 %v1 = load i32, ptr addrspace(3) %arrayidx1, align 41411 %r = add i32 %v0, %v11412 store i32 %r, ptr addrspace(1) %out, align 41413 ret void1414}1415 1416define amdgpu_ps <2 x float> @ds_read_interp_read(i32 inreg %prims, ptr addrspace(3) %inptr) {1417; CI-LABEL: ds_read_interp_read:1418; CI: ; %bb.0:1419; CI-NEXT: s_mov_b32 m0, -11420; CI-NEXT: ds_read_b32 v2, v01421; CI-NEXT: s_mov_b32 m0, s01422; CI-NEXT: v_interp_mov_f32 v1, p10, attr0.x1423; CI-NEXT: s_mov_b32 m0, -11424; CI-NEXT: ds_read_b32 v0, v0 offset:161425; CI-NEXT: s_waitcnt lgkmcnt(0)1426; CI-NEXT: v_add_f32_e32 v1, v0, v11427; CI-NEXT: v_mov_b32_e32 v0, v21428; CI-NEXT: ; return to shader part epilog1429;1430; GFX9-LABEL: ds_read_interp_read:1431; GFX9: ; %bb.0:1432; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset1:41433; GFX9-NEXT: s_mov_b32 m0, s01434; GFX9-NEXT: s_nop 01435; GFX9-NEXT: v_interp_mov_f32_e32 v2, p10, attr0.x1436; GFX9-NEXT: s_waitcnt lgkmcnt(0)1437; GFX9-NEXT: v_add_f32_e32 v1, v1, v21438; GFX9-NEXT: ; return to shader part epilog1439 %v0 = load float, ptr addrspace(3) %inptr, align 41440 %intrp = call float @llvm.amdgcn.interp.mov(i32 0, i32 0, i32 0, i32 %prims)1441 %ptr1 = getelementptr float, ptr addrspace(3) %inptr, i32 41442 %v1 = load float, ptr addrspace(3) %ptr1, align 41443 %v1b = fadd float %v1, %intrp1444 %r0 = insertelement <2 x float> poison, float %v0, i32 01445 %r1 = insertelement <2 x float> %r0, float %v1b, i32 11446 ret <2 x float> %r11447}1448 1449@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] poison, align 11450 1451define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out) {1452; CI-LABEL: read2_v2i32_align1_odd_offset:1453; CI: ; %bb.0: ; %entry1454; CI-NEXT: v_mov_b32_e32 v0, 01455; CI-NEXT: s_mov_b32 m0, -11456; CI-NEXT: ds_read_u8 v1, v0 offset:701457; CI-NEXT: ds_read_u8 v2, v0 offset:721458; CI-NEXT: ds_read_u8 v3, v0 offset:711459; CI-NEXT: ds_read_u8 v4, v0 offset:691460; CI-NEXT: ds_read_u8 v5, v0 offset:681461; CI-NEXT: s_waitcnt lgkmcnt(4)1462; CI-NEXT: v_lshlrev_b32_e32 v1, 8, v11463; CI-NEXT: s_waitcnt lgkmcnt(3)1464; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v21465; CI-NEXT: s_waitcnt lgkmcnt(2)1466; CI-NEXT: v_or_b32_e32 v2, v2, v31467; CI-NEXT: s_waitcnt lgkmcnt(1)1468; CI-NEXT: v_or_b32_e32 v1, v1, v41469; CI-NEXT: ds_read_u8 v4, v0 offset:661470; CI-NEXT: ds_read_u8 v6, v0 offset:671471; CI-NEXT: ds_read_u8 v0, v0 offset:651472; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v21473; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01474; CI-NEXT: v_or_b32_e32 v1, v2, v11475; CI-NEXT: s_waitcnt lgkmcnt(0)1476; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v41477; CI-NEXT: v_or_b32_e32 v0, v2, v01478; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v51479; CI-NEXT: v_or_b32_e32 v2, v2, v61480; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v21481; CI-NEXT: s_mov_b32 s3, 0xf0001482; CI-NEXT: s_mov_b32 s2, -11483; CI-NEXT: v_or_b32_e32 v0, v2, v01484; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01485; CI-NEXT: s_endpgm1486;1487; GFX9-ALIGNED-LABEL: read2_v2i32_align1_odd_offset:1488; GFX9-ALIGNED: ; %bb.0: ; %entry1489; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v2, 01490; GFX9-ALIGNED-NEXT: ds_read_u8 v0, v2 offset:651491; GFX9-ALIGNED-NEXT: ds_read_u8 v3, v2 offset:661492; GFX9-ALIGNED-NEXT: ds_read_u8 v4, v2 offset:671493; GFX9-ALIGNED-NEXT: ds_read_u8 v5, v2 offset:681494; GFX9-ALIGNED-NEXT: ds_read_u8 v1, v2 offset:701495; GFX9-ALIGNED-NEXT: ds_read_u8 v6, v2 offset:691496; GFX9-ALIGNED-NEXT: ds_read_u8 v7, v2 offset:721497; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v2 offset:711498; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01499; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)1500; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v11501; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v31502; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v1, v61503; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v6, 8, v71504; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v01505; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v51506; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1507; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1508; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v6, v11509; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v01510; GFX9-ALIGNED-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]1511; GFX9-ALIGNED-NEXT: s_endpgm1512;1513; GFX9-UNALIGNED-LABEL: read2_v2i32_align1_odd_offset:1514; GFX9-UNALIGNED: ; %bb.0: ; %entry1515; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v2, 01516; GFX9-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x01517; GFX9-UNALIGNED-NEXT: ds_read_b64 v[0:1], v2 offset:651518; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)1519; GFX9-UNALIGNED-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]1520; GFX9-UNALIGNED-NEXT: s_endpgm1521entry:1522 %load = load <2 x i32>, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @v2i32_align1, i32 65), align 11523 store <2 x i32> %load, ptr addrspace(1) %out1524 ret void1525}1526 1527declare void @void_func_void() #31528 1529declare i32 @llvm.amdgcn.workgroup.id.x() #11530declare i32 @llvm.amdgcn.workgroup.id.y() #11531declare i32 @llvm.amdgcn.workitem.id.x() #11532declare i32 @llvm.amdgcn.workitem.id.y() #11533 1534declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) nounwind readnone1535 1536declare void @llvm.amdgcn.s.barrier() #21537 1538attributes #0 = { nounwind }1539attributes #1 = { nounwind readnone speculatable }1540attributes #2 = { convergent nounwind }1541attributes #3 = { nounwind noinline }1542 1543