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1; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt,-enable-ds128 < %s | FileCheck --check-prefix=CI %s2 3@lds = addrspace(3) global [512 x float] poison, align 44@lds.v2 = addrspace(3) global [512 x <2 x float>] poison, align 45@lds.v3 = addrspace(3) global [512 x <3 x float>] poison, align 46@lds.v4 = addrspace(3) global [512 x <4 x float>] poison, align 47@lds.v8 = addrspace(3) global [512 x <8 x float>] poison, align 48@lds.v16 = addrspace(3) global [512 x <16 x float>] poison, align 49 10; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4:11; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}12; CI: s_waitcnt lgkmcnt(0)13; CI: buffer_store_dwordx2 [[RESULT]]14; CI: s_endpgm15define amdgpu_kernel void @simple_read2_v2f32_superreg_align4(ptr addrspace(1) %out) #0 {16 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #117 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], ptr addrspace(3) @lds.v2, i32 0, i32 %x.i18 %val0 = load <2 x float>, ptr addrspace(3) %arrayidx0, align 419 %out.gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %out, i32 %x.i20 store <2 x float> %val0, ptr addrspace(1) %out.gep21 ret void22}23 24; CI-LABEL: {{^}}simple_read2_v2f32_superreg:25; CI: ds_read_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}26; CI: s_waitcnt lgkmcnt(0)27; CI: buffer_store_dwordx2 [[RESULT]]28; CI: s_endpgm29define amdgpu_kernel void @simple_read2_v2f32_superreg(ptr addrspace(1) %out) #0 {30 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #131 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], ptr addrspace(3) @lds.v2, i32 0, i32 %x.i32 %val0 = load <2 x float>, ptr addrspace(3) %arrayidx033 %out.gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %out, i32 %x.i34 store <2 x float> %val0, ptr addrspace(1) %out.gep35 ret void36}37 38; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4:39; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}40; CI-DAG: ds_read2_b32 v[[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}41; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]42; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[REG_W]]43; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD0]], v[[ADD1]]44; CI: buffer_store_dword v[[ADD2]]45; CI: s_endpgm46define amdgpu_kernel void @simple_read2_v4f32_superreg_align4(ptr addrspace(1) %out) #0 {47 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #148 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], ptr addrspace(3) @lds.v4, i32 0, i32 %x.i49 %val0 = load <4 x float>, ptr addrspace(3) %arrayidx0, align 450 %elt0 = extractelement <4 x float> %val0, i32 051 %elt1 = extractelement <4 x float> %val0, i32 152 %elt2 = extractelement <4 x float> %val0, i32 253 %elt3 = extractelement <4 x float> %val0, i32 354 55 %add0 = fadd float %elt0, %elt256 %add1 = fadd float %elt1, %elt357 %add2 = fadd float %add0, %add158 59 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i60 store float %add2, ptr addrspace(1) %out.gep61 ret void62}63 64; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4:65; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}66; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}67; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]68; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[ADD0]], v[[REG_Y]]69; CI: buffer_store_dword v[[ADD1]]70; CI: s_endpgm71define amdgpu_kernel void @simple_read2_v3f32_superreg_align4(ptr addrspace(1) %out) #0 {72 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #173 %arrayidx0 = getelementptr inbounds [512 x <3 x float>], ptr addrspace(3) @lds.v3, i32 0, i32 %x.i74 %val0 = load <3 x float>, ptr addrspace(3) %arrayidx0, align 475 %elt0 = extractelement <3 x float> %val0, i32 076 %elt1 = extractelement <3 x float> %val0, i32 177 %elt2 = extractelement <3 x float> %val0, i32 278 79 %add0 = fadd float %elt0, %elt280 %add1 = fadd float %add0, %elt181 82 %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i32 %x.i83 store float %add1, ptr addrspace(1) %out.gep84 ret void85}86 87; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8:88; CI: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}89; CI: buffer_store_dwordx4 [[REG_ZW]]90; CI: s_endpgm91define amdgpu_kernel void @simple_read2_v4f32_superreg_align8(ptr addrspace(1) %out) #0 {92 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #193 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], ptr addrspace(3) @lds.v4, i32 0, i32 %x.i94 %val0 = load <4 x float>, ptr addrspace(3) %arrayidx0, align 895 %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i32 %x.i96 store <4 x float> %val0, ptr addrspace(1) %out.gep97 ret void98}99 100; CI-LABEL: {{^}}simple_read2_v4f32_superreg:101; CI-DAG: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}102; CI: buffer_store_dwordx4 [[REG_ZW]]103; CI: s_endpgm104define amdgpu_kernel void @simple_read2_v4f32_superreg(ptr addrspace(1) %out) #0 {105 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1106 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], ptr addrspace(3) @lds.v4, i32 0, i32 %x.i107 %val0 = load <4 x float>, ptr addrspace(3) %arrayidx0108 %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i32 %x.i109 store <4 x float> %val0, ptr addrspace(1) %out.gep110 ret void111}112 113; FIXME: Extra moves shuffling superregister114; CI-LABEL: {{^}}simple_read2_v8f32_superreg:115; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}116; CI-DAG: ds_read2_b64 [[VEC_LO:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}117; CI-DAG: buffer_store_dwordx4 [[VEC_HI]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16118; CI-DAG: buffer_store_dwordx4 [[VEC_LO]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}}119; CI: s_endpgm120define amdgpu_kernel void @simple_read2_v8f32_superreg(ptr addrspace(1) %out) #0 {121 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1122 %arrayidx0 = getelementptr inbounds [512 x <8 x float>], ptr addrspace(3) @lds.v8, i32 0, i32 %x.i123 %val0 = load <8 x float>, ptr addrspace(3) %arrayidx0124 %out.gep = getelementptr inbounds <8 x float>, ptr addrspace(1) %out, i32 %x.i125 store <8 x float> %val0, ptr addrspace(1) %out.gep126 ret void127}128 129; FIXME: Extra moves shuffling superregister130; CI-LABEL: {{^}}simple_read2_v16f32_superreg:131; CI-DAG: ds_read2_b64 [[VEC0_3:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}132; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}133; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}}134; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}}135; CI: s_waitcnt lgkmcnt(0)136; CI-DAG: buffer_store_dwordx4 [[VEC0_3]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}}137; CI-DAG: buffer_store_dwordx4 [[VEC4_7]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16138; CI-DAG: buffer_store_dwordx4 [[VEC8_11]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32139; CI-DAG: buffer_store_dwordx4 [[VEC12_15]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48140; CI: s_endpgm141define amdgpu_kernel void @simple_read2_v16f32_superreg(ptr addrspace(1) %out) #0 {142 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1143 %arrayidx0 = getelementptr inbounds [512 x <16 x float>], ptr addrspace(3) @lds.v16, i32 0, i32 %x.i144 %val0 = load <16 x float>, ptr addrspace(3) %arrayidx0145 %out.gep = getelementptr inbounds <16 x float>, ptr addrspace(1) %out, i32 %x.i146 store <16 x float> %val0, ptr addrspace(1) %out.gep147 ret void148}149 150; Do scalar loads into the super register we need.151; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4:152; CI-DAG: ds_read2_b32 v[[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}153; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}}154; CI: buffer_store_dwordx2 v[[[REG_ELT0]]:[[REG_ELT1]]]155; CI: s_endpgm156define amdgpu_kernel void @simple_read2_v2f32_superreg_scalar_loads_align4(ptr addrspace(1) %out) #0 {157 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1158 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i159 %arrayidx1 = getelementptr inbounds float, ptr addrspace(3) %arrayidx0, i32 1160 161 %val0 = load float, ptr addrspace(3) %arrayidx0162 %val1 = load float, ptr addrspace(3) %arrayidx1163 164 %vec.0 = insertelement <2 x float> poison, float %val0, i32 0165 %vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1166 167 %out.gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %out, i32 %x.i168 store <2 x float> %vec.1, ptr addrspace(1) %out.gep169 ret void170}171 172; Do scalar loads into the super register we need.173; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4:174; CI-DAG: ds_read2_b32 v[[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}175; CI-DAG: ds_read2_b32 v[[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}176; CI-NOT: v_mov {{v[0-9]+}}, {{[sv][0-9]+}}177; CI: buffer_store_dwordx4 v[[[REG_ELT0]]:[[REG_ELT3]]]178; CI: s_endpgm179define amdgpu_kernel void @simple_read2_v4f32_superreg_scalar_loads_align4(ptr addrspace(1) %out) #0 {180 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1181 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i182 %arrayidx1 = getelementptr inbounds float, ptr addrspace(3) %arrayidx0, i32 1183 %arrayidx2 = getelementptr inbounds float, ptr addrspace(3) %arrayidx0, i32 2184 %arrayidx3 = getelementptr inbounds float, ptr addrspace(3) %arrayidx0, i32 3185 186 %val0 = load float, ptr addrspace(3) %arrayidx0187 %val1 = load float, ptr addrspace(3) %arrayidx1188 %val2 = load float, ptr addrspace(3) %arrayidx2189 %val3 = load float, ptr addrspace(3) %arrayidx3190 191 %vec.0 = insertelement <4 x float> poison, float %val0, i32 0192 %vec.1 = insertelement <4 x float> %vec.0, float %val1, i32 1193 %vec.2 = insertelement <4 x float> %vec.1, float %val2, i32 2194 %vec.3 = insertelement <4 x float> %vec.2, float %val3, i32 3195 196 %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i32 %x.i197 store <4 x float> %vec.3, ptr addrspace(1) %out.gep198 ret void199}200 201; Function Attrs: nounwind readnone202declare i32 @llvm.amdgcn.workitem.id.x() #1203 204; Function Attrs: nounwind readnone205declare i32 @llvm.amdgcn.workitem.id.y() #1206 207attributes #0 = { nounwind }208attributes #1 = { nounwind readnone }209attributes #2 = { convergent nounwind }210