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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -enable-var-scope --check-prefix=CI %s3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=+load-store-opt,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s4; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s5; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1250 -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-UNALIGNED %s6 7@lds = addrspace(3) global [512 x float] poison, align 48@lds.f64 = addrspace(3) global [512 x double] poison, align 89 10define amdgpu_kernel void @simple_write2_one_val_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {11; CI-LABEL: simple_write2_one_val_f32:12; CI: ; %bb.0:13; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x214; CI-NEXT: s_mov_b32 s3, 0xf00015; CI-NEXT: s_mov_b32 s2, 016; CI-NEXT: v_mov_b32_e32 v1, 017; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v018; CI-NEXT: s_waitcnt lgkmcnt(0)19; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr6420; CI-NEXT: s_mov_b32 m0, -121; CI-NEXT: s_waitcnt vmcnt(0)22; CI-NEXT: ds_write2_b32 v0, v1, v1 offset1:823; CI-NEXT: s_endpgm24;25; GFX9-LABEL: simple_write2_one_val_f32:26; GFX9: ; %bb.0:27; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x828; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v029; GFX9-NEXT: s_waitcnt lgkmcnt(0)30; GFX9-NEXT: global_load_dword v1, v0, s[0:1]31; GFX9-NEXT: s_waitcnt vmcnt(0)32; GFX9-NEXT: ds_write2_b32 v0, v1, v1 offset1:833; GFX9-NEXT: s_endpgm34;35; GFX1250-LABEL: simple_write2_one_val_f32:36; GFX1250: ; %bb.0:37; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 138; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x839; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v040; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)41; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v042; GFX1250-NEXT: s_wait_kmcnt 0x043; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1]44; GFX1250-NEXT: s_wait_loadcnt 0x045; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v1 offset1:846; GFX1250-NEXT: s_endpgm47 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #148 %in.gep = getelementptr float, ptr addrspace(1) %in, i32 %x.i49 %val = load float, ptr addrspace(1) %in.gep, align 450 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i51 store float %val, ptr addrspace(3) %arrayidx0, align 452 %add.x = add nsw i32 %x.i, 853 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x54 store float %val, ptr addrspace(3) %arrayidx1, align 455 ret void56}57 58define amdgpu_kernel void @simple_write2_two_val_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {59; CI-LABEL: simple_write2_two_val_f32:60; CI: ; %bb.0:61; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x262; CI-NEXT: s_mov_b32 s3, 0xf00063; CI-NEXT: s_mov_b32 s2, 064; CI-NEXT: v_mov_b32_e32 v1, 065; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v066; CI-NEXT: s_waitcnt lgkmcnt(0)67; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc68; CI-NEXT: s_waitcnt vmcnt(0)69; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 offset:4 glc70; CI-NEXT: s_waitcnt vmcnt(0)71; CI-NEXT: s_mov_b32 m0, -172; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:873; CI-NEXT: s_endpgm74;75; GFX9-LABEL: simple_write2_two_val_f32:76; GFX9: ; %bb.0:77; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x878; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v079; GFX9-NEXT: s_waitcnt lgkmcnt(0)80; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc81; GFX9-NEXT: s_waitcnt vmcnt(0)82; GFX9-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc83; GFX9-NEXT: s_waitcnt vmcnt(0)84; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:885; GFX9-NEXT: s_endpgm86;87; GFX1250-LABEL: simple_write2_two_val_f32:88; GFX1250: ; %bb.0:89; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 190; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x891; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v092; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)93; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v094; GFX1250-NEXT: s_wait_kmcnt 0x095; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS96; GFX1250-NEXT: s_wait_loadcnt 0x097; GFX1250-NEXT: global_load_b32 v2, v0, s[0:1] offset:4 scope:SCOPE_SYS98; GFX1250-NEXT: s_wait_loadcnt 0x099; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v2 offset1:8100; GFX1250-NEXT: s_endpgm101 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1102 %in.gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %x.i103 %in.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 1104 %val0 = load volatile float, ptr addrspace(1) %in.gep.0, align 4105 %val1 = load volatile float, ptr addrspace(1) %in.gep.1, align 4106 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i107 store float %val0, ptr addrspace(3) %arrayidx0, align 4108 %add.x = add nsw i32 %x.i, 8109 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x110 store float %val1, ptr addrspace(3) %arrayidx1, align 4111 ret void112}113 114define amdgpu_kernel void @simple_write2_two_val_f32_volatile_0(ptr addrspace(1) %C, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {115; CI-LABEL: simple_write2_two_val_f32_volatile_0:116; CI: ; %bb.0:117; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2118; CI-NEXT: s_mov_b32 s7, 0xf000119; CI-NEXT: s_mov_b32 s6, 0120; CI-NEXT: v_mov_b32_e32 v1, 0121; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0122; CI-NEXT: s_waitcnt lgkmcnt(0)123; CI-NEXT: s_mov_b64 s[4:5], s[0:1]124; CI-NEXT: s_mov_b64 s[0:1], s[2:3]125; CI-NEXT: s_mov_b64 s[2:3], s[6:7]126; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc127; CI-NEXT: s_waitcnt vmcnt(0)128; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 glc129; CI-NEXT: s_waitcnt vmcnt(0)130; CI-NEXT: s_mov_b32 m0, -1131; CI-NEXT: ds_write_b32 v0, v2132; CI-NEXT: ds_write_b32 v0, v1 offset:32133; CI-NEXT: s_endpgm134;135; GFX9-LABEL: simple_write2_two_val_f32_volatile_0:136; GFX9: ; %bb.0:137; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8138; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0139; GFX9-NEXT: s_waitcnt lgkmcnt(0)140; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc141; GFX9-NEXT: s_waitcnt vmcnt(0)142; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc143; GFX9-NEXT: s_waitcnt vmcnt(0)144; GFX9-NEXT: ds_write_b32 v0, v1145; GFX9-NEXT: ds_write_b32 v0, v2 offset:32146; GFX9-NEXT: s_endpgm147;148; GFX1250-LABEL: simple_write2_two_val_f32_volatile_0:149; GFX1250: ; %bb.0:150; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1151; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8152; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0153; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)154; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0155; GFX1250-NEXT: s_wait_kmcnt 0x0156; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS157; GFX1250-NEXT: s_wait_loadcnt 0x0158; GFX1250-NEXT: global_load_b32 v2, v0, s[2:3] scope:SCOPE_SYS159; GFX1250-NEXT: s_wait_loadcnt 0x0160; GFX1250-NEXT: ds_store_b32 v0, v1161; GFX1250-NEXT: ds_store_b32 v0, v2 offset:32162; GFX1250-NEXT: s_endpgm163 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1164 %in0.gep = getelementptr float, ptr addrspace(1) %in0, i32 %x.i165 %in1.gep = getelementptr float, ptr addrspace(1) %in1, i32 %x.i166 %val0 = load volatile float, ptr addrspace(1) %in0.gep, align 4167 %val1 = load volatile float, ptr addrspace(1) %in1.gep, align 4168 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i169 store volatile float %val0, ptr addrspace(3) %arrayidx0, align 4170 %add.x = add nsw i32 %x.i, 8171 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x172 store float %val1, ptr addrspace(3) %arrayidx1, align 4173 ret void174}175 176define amdgpu_kernel void @simple_write2_two_val_f32_volatile_1(ptr addrspace(1) %C, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {177; CI-LABEL: simple_write2_two_val_f32_volatile_1:178; CI: ; %bb.0:179; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2180; CI-NEXT: s_mov_b32 s7, 0xf000181; CI-NEXT: s_mov_b32 s6, 0182; CI-NEXT: v_mov_b32_e32 v1, 0183; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0184; CI-NEXT: s_waitcnt lgkmcnt(0)185; CI-NEXT: s_mov_b64 s[4:5], s[0:1]186; CI-NEXT: s_mov_b64 s[0:1], s[2:3]187; CI-NEXT: s_mov_b64 s[2:3], s[6:7]188; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc189; CI-NEXT: s_waitcnt vmcnt(0)190; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 glc191; CI-NEXT: s_waitcnt vmcnt(0)192; CI-NEXT: s_mov_b32 m0, -1193; CI-NEXT: ds_write_b32 v0, v2194; CI-NEXT: ds_write_b32 v0, v1 offset:32195; CI-NEXT: s_endpgm196;197; GFX9-LABEL: simple_write2_two_val_f32_volatile_1:198; GFX9: ; %bb.0:199; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8200; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0201; GFX9-NEXT: s_waitcnt lgkmcnt(0)202; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc203; GFX9-NEXT: s_waitcnt vmcnt(0)204; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc205; GFX9-NEXT: s_waitcnt vmcnt(0)206; GFX9-NEXT: ds_write_b32 v0, v1207; GFX9-NEXT: ds_write_b32 v0, v2 offset:32208; GFX9-NEXT: s_endpgm209;210; GFX1250-LABEL: simple_write2_two_val_f32_volatile_1:211; GFX1250: ; %bb.0:212; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1213; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8214; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0215; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)216; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0217; GFX1250-NEXT: s_wait_kmcnt 0x0218; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS219; GFX1250-NEXT: s_wait_loadcnt 0x0220; GFX1250-NEXT: global_load_b32 v2, v0, s[2:3] scope:SCOPE_SYS221; GFX1250-NEXT: s_wait_loadcnt 0x0222; GFX1250-NEXT: ds_store_b32 v0, v1223; GFX1250-NEXT: ds_store_b32 v0, v2 offset:32224; GFX1250-NEXT: s_endpgm225 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1226 %in0.gep = getelementptr float, ptr addrspace(1) %in0, i32 %x.i227 %in1.gep = getelementptr float, ptr addrspace(1) %in1, i32 %x.i228 %val0 = load volatile float, ptr addrspace(1) %in0.gep, align 4229 %val1 = load volatile float, ptr addrspace(1) %in1.gep, align 4230 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i231 store float %val0, ptr addrspace(3) %arrayidx0, align 4232 %add.x = add nsw i32 %x.i, 8233 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x234 store volatile float %val1, ptr addrspace(3) %arrayidx1, align 4235 ret void236}237 238; 2 data subregisters from different super registers.239; TODO: GFX9 has v_mov_b32_e32 v2, lds@abs32@lo240; This should be an s_mov_b32. The v_mov_b32 gets introduced by an241; early legalization of the constant bus constraint on the v_lshl_add_u32,242; and then SIFoldOperands folds in an unlucky order.243define amdgpu_kernel void @simple_write2_two_val_subreg2_mixed_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {244; CI-LABEL: simple_write2_two_val_subreg2_mixed_f32:245; CI: ; %bb.0:246; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2247; CI-NEXT: s_mov_b32 s3, 0xf000248; CI-NEXT: s_mov_b32 s2, 0249; CI-NEXT: v_lshlrev_b32_e32 v1, 3, v0250; CI-NEXT: v_mov_b32_e32 v2, 0251; CI-NEXT: s_waitcnt lgkmcnt(0)252; CI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[0:3], 0 addr64 glc253; CI-NEXT: s_waitcnt vmcnt(0)254; CI-NEXT: buffer_load_dwordx2 v[1:2], v[1:2], s[0:3], 0 addr64 offset:8 glc255; CI-NEXT: s_waitcnt vmcnt(0)256; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0257; CI-NEXT: s_mov_b32 m0, -1258; CI-NEXT: ds_write2_b32 v0, v3, v2 offset1:8259; CI-NEXT: s_endpgm260;261; GFX9-LABEL: simple_write2_two_val_subreg2_mixed_f32:262; GFX9: ; %bb.0:263; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8264; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0265; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0266; GFX9-NEXT: ; kill: killed $vgpr4267; GFX9-NEXT: ; kill: killed $sgpr0_sgpr1268; GFX9-NEXT: s_waitcnt lgkmcnt(0)269; GFX9-NEXT: global_load_dwordx2 v[1:2], v4, s[0:1] glc270; GFX9-NEXT: s_waitcnt vmcnt(0)271; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[0:1] offset:8 glc272; GFX9-NEXT: s_waitcnt vmcnt(0)273; GFX9-NEXT: ds_write2_b32 v0, v1, v3 offset1:8274; GFX9-NEXT: s_endpgm275;276; GFX1250-LABEL: simple_write2_two_val_subreg2_mixed_f32:277; GFX1250: ; %bb.0:278; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1279; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8280; GFX1250-NEXT: v_and_b32_e32 v4, 0x3ff, v0281; GFX1250-NEXT: s_wait_kmcnt 0x0282; GFX1250-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset scope:SCOPE_SYS283; GFX1250-NEXT: s_wait_loadcnt 0x0284; GFX1250-NEXT: global_load_b64 v[2:3], v4, s[0:1] offset:8 scale_offset scope:SCOPE_SYS285; GFX1250-NEXT: s_wait_loadcnt 0x0286; GFX1250-NEXT: v_lshlrev_b32_e32 v1, 2, v4287; GFX1250-NEXT: ds_store_2addr_b32 v1, v0, v3 offset1:8288; GFX1250-NEXT: s_endpgm289 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1290 %in.gep.0 = getelementptr <2 x float>, ptr addrspace(1) %in, i32 %x.i291 %in.gep.1 = getelementptr <2 x float>, ptr addrspace(1) %in.gep.0, i32 1292 %val0 = load volatile <2 x float>, ptr addrspace(1) %in.gep.0, align 8293 %val1 = load volatile <2 x float>, ptr addrspace(1) %in.gep.1, align 8294 %val0.0 = extractelement <2 x float> %val0, i32 0295 %val1.1 = extractelement <2 x float> %val1, i32 1296 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i297 store float %val0.0, ptr addrspace(3) %arrayidx0, align 4298 %add.x = add nsw i32 %x.i, 8299 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x300 store float %val1.1, ptr addrspace(3) %arrayidx1, align 4301 ret void302}303 304define amdgpu_kernel void @simple_write2_two_val_subreg2_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {305; CI-LABEL: simple_write2_two_val_subreg2_f32:306; CI: ; %bb.0:307; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2308; CI-NEXT: s_mov_b32 s3, 0xf000309; CI-NEXT: s_mov_b32 s2, 0310; CI-NEXT: v_lshlrev_b32_e32 v1, 3, v0311; CI-NEXT: v_mov_b32_e32 v2, 0312; CI-NEXT: s_waitcnt lgkmcnt(0)313; CI-NEXT: buffer_load_dwordx2 v[1:2], v[1:2], s[0:3], 0 addr64314; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0315; CI-NEXT: s_mov_b32 m0, -1316; CI-NEXT: s_waitcnt vmcnt(0)317; CI-NEXT: ds_write2_b32 v0, v1, v2 offset1:8318; CI-NEXT: s_endpgm319;320; GFX9-LABEL: simple_write2_two_val_subreg2_f32:321; GFX9: ; %bb.0:322; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8323; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v0324; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0325; GFX9-NEXT: s_waitcnt lgkmcnt(0)326; GFX9-NEXT: global_load_dwordx2 v[1:2], v1, s[0:1]327; GFX9-NEXT: s_waitcnt vmcnt(0)328; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:8329; GFX9-NEXT: s_endpgm330;331; GFX1250-LABEL: simple_write2_two_val_subreg2_f32:332; GFX1250: ; %bb.0:333; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1334; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8335; GFX1250-NEXT: v_and_b32_e32 v2, 0x3ff, v0336; GFX1250-NEXT: s_wait_kmcnt 0x0337; GFX1250-NEXT: global_load_b64 v[0:1], v2, s[0:1] scale_offset338; GFX1250-NEXT: s_wait_xcnt 0x0339; GFX1250-NEXT: v_lshlrev_b32_e32 v2, 2, v2340; GFX1250-NEXT: s_wait_loadcnt 0x0341; GFX1250-NEXT: ds_store_2addr_b32 v2, v0, v1 offset1:8342; GFX1250-NEXT: s_endpgm343 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1344 %in.gep = getelementptr <2 x float>, ptr addrspace(1) %in, i32 %x.i345 %val = load <2 x float>, ptr addrspace(1) %in.gep, align 8346 %val0 = extractelement <2 x float> %val, i32 0347 %val1 = extractelement <2 x float> %val, i32 1348 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i349 store float %val0, ptr addrspace(3) %arrayidx0, align 4350 %add.x = add nsw i32 %x.i, 8351 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x352 store float %val1, ptr addrspace(3) %arrayidx1, align 4353 ret void354}355 356define amdgpu_kernel void @simple_write2_two_val_subreg4_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {357; CI-LABEL: simple_write2_two_val_subreg4_f32:358; CI: ; %bb.0:359; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2360; CI-NEXT: s_mov_b32 s3, 0xf000361; CI-NEXT: s_mov_b32 s2, 0362; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v0363; CI-NEXT: v_mov_b32_e32 v2, 0364; CI-NEXT: s_waitcnt lgkmcnt(0)365; CI-NEXT: buffer_load_dwordx4 v[1:4], v[1:2], s[0:3], 0 addr64366; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0367; CI-NEXT: s_mov_b32 m0, -1368; CI-NEXT: s_waitcnt vmcnt(0)369; CI-NEXT: ds_write2_b32 v0, v1, v4 offset1:8370; CI-NEXT: s_endpgm371;372; GFX9-LABEL: simple_write2_two_val_subreg4_f32:373; GFX9: ; %bb.0:374; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8375; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v0376; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0377; GFX9-NEXT: s_waitcnt lgkmcnt(0)378; GFX9-NEXT: global_load_dwordx4 v[1:4], v1, s[0:1]379; GFX9-NEXT: s_waitcnt vmcnt(0)380; GFX9-NEXT: ds_write2_b32 v0, v1, v4 offset1:8381; GFX9-NEXT: s_endpgm382;383; GFX1250-LABEL: simple_write2_two_val_subreg4_f32:384; GFX1250: ; %bb.0:385; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1386; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8387; GFX1250-NEXT: v_and_b32_e32 v4, 0x3ff, v0388; GFX1250-NEXT: s_wait_kmcnt 0x0389; GFX1250-NEXT: global_load_b128 v[0:3], v4, s[0:1] scale_offset390; GFX1250-NEXT: s_wait_loadcnt 0x0391; GFX1250-NEXT: v_lshlrev_b32_e32 v1, 2, v4392; GFX1250-NEXT: ds_store_2addr_b32 v1, v0, v3 offset1:8393; GFX1250-NEXT: s_endpgm394 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1395 %in.gep = getelementptr <4 x float>, ptr addrspace(1) %in, i32 %x.i396 %val = load <4 x float>, ptr addrspace(1) %in.gep, align 16397 %val0 = extractelement <4 x float> %val, i32 0398 %val1 = extractelement <4 x float> %val, i32 3399 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i400 store float %val0, ptr addrspace(3) %arrayidx0, align 4401 %add.x = add nsw i32 %x.i, 8402 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x403 store float %val1, ptr addrspace(3) %arrayidx1, align 4404 ret void405}406 407define amdgpu_kernel void @simple_write2_two_val_max_offset_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {408; CI-LABEL: simple_write2_two_val_max_offset_f32:409; CI: ; %bb.0:410; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2411; CI-NEXT: s_mov_b32 s3, 0xf000412; CI-NEXT: s_mov_b32 s2, 0413; CI-NEXT: v_mov_b32_e32 v1, 0414; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0415; CI-NEXT: s_waitcnt lgkmcnt(0)416; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc417; CI-NEXT: s_waitcnt vmcnt(0)418; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 offset:4 glc419; CI-NEXT: s_waitcnt vmcnt(0)420; CI-NEXT: s_mov_b32 m0, -1421; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:255422; CI-NEXT: s_endpgm423;424; GFX9-LABEL: simple_write2_two_val_max_offset_f32:425; GFX9: ; %bb.0:426; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8427; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0428; GFX9-NEXT: s_waitcnt lgkmcnt(0)429; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc430; GFX9-NEXT: s_waitcnt vmcnt(0)431; GFX9-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc432; GFX9-NEXT: s_waitcnt vmcnt(0)433; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:255434; GFX9-NEXT: s_endpgm435;436; GFX1250-LABEL: simple_write2_two_val_max_offset_f32:437; GFX1250: ; %bb.0:438; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1439; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8440; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0441; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)442; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0443; GFX1250-NEXT: s_wait_kmcnt 0x0444; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS445; GFX1250-NEXT: s_wait_loadcnt 0x0446; GFX1250-NEXT: global_load_b32 v2, v0, s[0:1] offset:4 scope:SCOPE_SYS447; GFX1250-NEXT: s_wait_loadcnt 0x0448; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v2 offset1:255449; GFX1250-NEXT: s_endpgm450 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1451 %in.gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %x.i452 %in.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 1453 %val0 = load volatile float, ptr addrspace(1) %in.gep.0, align 4454 %val1 = load volatile float, ptr addrspace(1) %in.gep.1, align 4455 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i456 store float %val0, ptr addrspace(3) %arrayidx0, align 4457 %add.x = add nsw i32 %x.i, 255458 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x459 store float %val1, ptr addrspace(3) %arrayidx1, align 4460 ret void461}462 463define amdgpu_kernel void @simple_write2_two_val_too_far_f32(ptr addrspace(1) %C, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {464; CI-LABEL: simple_write2_two_val_too_far_f32:465; CI: ; %bb.0:466; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2467; CI-NEXT: s_mov_b32 s7, 0xf000468; CI-NEXT: s_mov_b32 s6, 0469; CI-NEXT: v_mov_b32_e32 v1, 0470; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0471; CI-NEXT: s_waitcnt lgkmcnt(0)472; CI-NEXT: s_mov_b64 s[4:5], s[0:1]473; CI-NEXT: s_mov_b64 s[0:1], s[2:3]474; CI-NEXT: s_mov_b64 s[2:3], s[6:7]475; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64476; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64477; CI-NEXT: s_mov_b32 m0, -1478; CI-NEXT: s_waitcnt vmcnt(1)479; CI-NEXT: ds_write_b32 v0, v2480; CI-NEXT: s_waitcnt vmcnt(0)481; CI-NEXT: ds_write_b32 v0, v1 offset:1028482; CI-NEXT: s_endpgm483;484; GFX9-LABEL: simple_write2_two_val_too_far_f32:485; GFX9: ; %bb.0:486; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8487; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0488; GFX9-NEXT: s_waitcnt lgkmcnt(0)489; GFX9-NEXT: global_load_dword v1, v0, s[0:1]490; GFX9-NEXT: global_load_dword v2, v0, s[2:3]491; GFX9-NEXT: s_waitcnt vmcnt(1)492; GFX9-NEXT: ds_write_b32 v0, v1493; GFX9-NEXT: s_waitcnt vmcnt(0)494; GFX9-NEXT: ds_write_b32 v0, v2 offset:1028495; GFX9-NEXT: s_endpgm496;497; GFX1250-LABEL: simple_write2_two_val_too_far_f32:498; GFX1250: ; %bb.0:499; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1500; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8501; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0502; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)503; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0504; GFX1250-NEXT: s_wait_kmcnt 0x0505; GFX1250-NEXT: s_clause 0x1506; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1]507; GFX1250-NEXT: global_load_b32 v2, v0, s[2:3]508; GFX1250-NEXT: s_wait_loadcnt 0x1509; GFX1250-NEXT: ds_store_b32 v0, v1510; GFX1250-NEXT: s_wait_loadcnt 0x0511; GFX1250-NEXT: ds_store_b32 v0, v2 offset:1028512; GFX1250-NEXT: s_endpgm513 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1514 %in0.gep = getelementptr float, ptr addrspace(1) %in0, i32 %x.i515 %in1.gep = getelementptr float, ptr addrspace(1) %in1, i32 %x.i516 %val0 = load float, ptr addrspace(1) %in0.gep, align 4517 %val1 = load float, ptr addrspace(1) %in1.gep, align 4518 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i519 store float %val0, ptr addrspace(3) %arrayidx0, align 4520 %add.x = add nsw i32 %x.i, 257521 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x522 store float %val1, ptr addrspace(3) %arrayidx1, align 4523 ret void524}525 526define amdgpu_kernel void @simple_write2_two_val_f32_x2(ptr addrspace(1) %C, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {527; CI-LABEL: simple_write2_two_val_f32_x2:528; CI: ; %bb.0:529; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2530; CI-NEXT: s_mov_b32 s7, 0xf000531; CI-NEXT: s_mov_b32 s6, 0532; CI-NEXT: v_mov_b32_e32 v1, 0533; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0534; CI-NEXT: s_waitcnt lgkmcnt(0)535; CI-NEXT: s_mov_b64 s[4:5], s[0:1]536; CI-NEXT: s_mov_b64 s[0:1], s[2:3]537; CI-NEXT: s_mov_b64 s[2:3], s[6:7]538; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64539; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64540; CI-NEXT: s_mov_b32 m0, -1541; CI-NEXT: s_waitcnt vmcnt(0)542; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:8543; CI-NEXT: ds_write2_b32 v0, v2, v1 offset0:11 offset1:27544; CI-NEXT: s_endpgm545;546; GFX9-LABEL: simple_write2_two_val_f32_x2:547; GFX9: ; %bb.0:548; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8549; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0550; GFX9-NEXT: s_waitcnt lgkmcnt(0)551; GFX9-NEXT: global_load_dword v1, v0, s[0:1]552; GFX9-NEXT: global_load_dword v2, v0, s[2:3]553; GFX9-NEXT: s_waitcnt vmcnt(0)554; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:8555; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset0:11 offset1:27556; GFX9-NEXT: s_endpgm557;558; GFX1250-LABEL: simple_write2_two_val_f32_x2:559; GFX1250: ; %bb.0:560; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1561; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8562; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0563; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)564; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0565; GFX1250-NEXT: s_wait_kmcnt 0x0566; GFX1250-NEXT: s_clause 0x1567; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1]568; GFX1250-NEXT: global_load_b32 v2, v0, s[2:3]569; GFX1250-NEXT: s_wait_loadcnt 0x0570; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v2 offset1:8571; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v2 offset0:11 offset1:27572; GFX1250-NEXT: s_endpgm573 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1574 %in0.gep = getelementptr float, ptr addrspace(1) %in0, i32 %tid.x575 %in1.gep = getelementptr float, ptr addrspace(1) %in1, i32 %tid.x576 %val0 = load float, ptr addrspace(1) %in0.gep, align 4577 %val1 = load float, ptr addrspace(1) %in1.gep, align 4578 579 %idx.0 = add nsw i32 %tid.x, 0580 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0581 store float %val0, ptr addrspace(3) %arrayidx0, align 4582 583 %idx.1 = add nsw i32 %tid.x, 8584 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1585 store float %val1, ptr addrspace(3) %arrayidx1, align 4586 587 %idx.2 = add nsw i32 %tid.x, 11588 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2589 store float %val0, ptr addrspace(3) %arrayidx2, align 4590 591 %idx.3 = add nsw i32 %tid.x, 27592 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3593 store float %val1, ptr addrspace(3) %arrayidx3, align 4594 595 ret void596}597 598define amdgpu_kernel void @simple_write2_two_val_f32_x2_nonzero_base(ptr addrspace(1) %C, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {599; CI-LABEL: simple_write2_two_val_f32_x2_nonzero_base:600; CI: ; %bb.0:601; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2602; CI-NEXT: s_mov_b32 s7, 0xf000603; CI-NEXT: s_mov_b32 s6, 0604; CI-NEXT: v_mov_b32_e32 v1, 0605; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0606; CI-NEXT: s_waitcnt lgkmcnt(0)607; CI-NEXT: s_mov_b64 s[4:5], s[0:1]608; CI-NEXT: s_mov_b64 s[0:1], s[2:3]609; CI-NEXT: s_mov_b64 s[2:3], s[6:7]610; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64611; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64612; CI-NEXT: s_mov_b32 m0, -1613; CI-NEXT: s_waitcnt vmcnt(0)614; CI-NEXT: ds_write2_b32 v0, v2, v1 offset0:3 offset1:8615; CI-NEXT: ds_write2_b32 v0, v2, v1 offset0:11 offset1:27616; CI-NEXT: s_endpgm617;618; GFX9-LABEL: simple_write2_two_val_f32_x2_nonzero_base:619; GFX9: ; %bb.0:620; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8621; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0622; GFX9-NEXT: s_waitcnt lgkmcnt(0)623; GFX9-NEXT: global_load_dword v1, v0, s[0:1]624; GFX9-NEXT: global_load_dword v2, v0, s[2:3]625; GFX9-NEXT: s_waitcnt vmcnt(0)626; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset0:3 offset1:8627; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset0:11 offset1:27628; GFX9-NEXT: s_endpgm629;630; GFX1250-LABEL: simple_write2_two_val_f32_x2_nonzero_base:631; GFX1250: ; %bb.0:632; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1633; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8634; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 2, v0635; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)636; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v0637; GFX1250-NEXT: s_wait_kmcnt 0x0638; GFX1250-NEXT: s_clause 0x1639; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1]640; GFX1250-NEXT: global_load_b32 v2, v0, s[2:3]641; GFX1250-NEXT: s_wait_loadcnt 0x0642; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v2 offset0:3 offset1:8643; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v2 offset0:11 offset1:27644; GFX1250-NEXT: s_endpgm645 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1646 %in0.gep = getelementptr float, ptr addrspace(1) %in0, i32 %tid.x647 %in1.gep = getelementptr float, ptr addrspace(1) %in1, i32 %tid.x648 %val0 = load float, ptr addrspace(1) %in0.gep, align 4649 %val1 = load float, ptr addrspace(1) %in1.gep, align 4650 651 %idx.0 = add nsw i32 %tid.x, 3652 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.0653 store float %val0, ptr addrspace(3) %arrayidx0, align 4654 655 %idx.1 = add nsw i32 %tid.x, 8656 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.1657 store float %val1, ptr addrspace(3) %arrayidx1, align 4658 659 %idx.2 = add nsw i32 %tid.x, 11660 %arrayidx2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.2661 store float %val0, ptr addrspace(3) %arrayidx2, align 4662 663 %idx.3 = add nsw i32 %tid.x, 27664 %arrayidx3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %idx.3665 store float %val1, ptr addrspace(3) %arrayidx3, align 4666 667 ret void668}669 670define amdgpu_kernel void @write2_ptr_subreg_arg_two_val_f32(ptr addrspace(1) %C, ptr addrspace(1) %in0, ptr addrspace(1) %in1, <2 x ptr addrspace(3)> %lds.ptr) #0 {671; CI-LABEL: write2_ptr_subreg_arg_two_val_f32:672; CI: ; %bb.0:673; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2674; CI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x6675; CI-NEXT: s_mov_b32 s7, 0xf000676; CI-NEXT: s_mov_b32 s6, 0677; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0678; CI-NEXT: s_waitcnt lgkmcnt(0)679; CI-NEXT: s_mov_b64 s[4:5], s[0:1]680; CI-NEXT: v_mov_b32_e32 v1, 0681; CI-NEXT: s_mov_b64 s[0:1], s[2:3]682; CI-NEXT: s_mov_b64 s[2:3], s[6:7]683; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64684; CI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64685; CI-NEXT: v_mov_b32_e32 v1, s8686; CI-NEXT: s_mov_b32 m0, -1687; CI-NEXT: v_mov_b32_e32 v3, s9688; CI-NEXT: s_waitcnt vmcnt(1)689; CI-NEXT: ds_write_b32 v1, v2 offset:32690; CI-NEXT: s_waitcnt vmcnt(0)691; CI-NEXT: ds_write_b32 v3, v0 offset:32692; CI-NEXT: s_endpgm693;694; GFX9-LABEL: write2_ptr_subreg_arg_two_val_f32:695; GFX9: ; %bb.0:696; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x8697; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x18698; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0699; GFX9-NEXT: s_waitcnt lgkmcnt(0)700; GFX9-NEXT: global_load_dword v1, v0, s[0:1]701; GFX9-NEXT: global_load_dword v2, v0, s[2:3]702; GFX9-NEXT: v_mov_b32_e32 v0, s6703; GFX9-NEXT: v_mov_b32_e32 v3, s7704; GFX9-NEXT: s_waitcnt vmcnt(1)705; GFX9-NEXT: ds_write_b32 v0, v1 offset:32706; GFX9-NEXT: s_waitcnt vmcnt(0)707; GFX9-NEXT: ds_write_b32 v3, v2 offset:32708; GFX9-NEXT: s_endpgm709;710; GFX1250-LABEL: write2_ptr_subreg_arg_two_val_f32:711; GFX1250: ; %bb.0:712; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1713; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x8714; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0715; GFX1250-NEXT: s_wait_xcnt 0x0716; GFX1250-NEXT: s_load_b64 s[4:5], s[4:5], 0x18717; GFX1250-NEXT: s_wait_kmcnt 0x0718; GFX1250-NEXT: s_clause 0x1719; GFX1250-NEXT: global_load_b32 v1, v0, s[0:1] scale_offset720; GFX1250-NEXT: global_load_b32 v2, v0, s[2:3] scale_offset721; GFX1250-NEXT: s_wait_xcnt 0x0722; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s5723; GFX1250-NEXT: s_wait_loadcnt 0x1724; GFX1250-NEXT: ds_store_b32 v0, v1 offset:32725; GFX1250-NEXT: s_wait_loadcnt 0x0726; GFX1250-NEXT: ds_store_b32 v3, v2 offset:32727; GFX1250-NEXT: s_endpgm728 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1729 %in0.gep = getelementptr float, ptr addrspace(1) %in0, i32 %x.i730 %in1.gep = getelementptr float, ptr addrspace(1) %in1, i32 %x.i731 %val0 = load float, ptr addrspace(1) %in0.gep, align 4732 %val1 = load float, ptr addrspace(1) %in1.gep, align 4733 734 %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0735 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0736 %gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1737 %gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0738 %gep.1 = extractelement <2 x ptr addrspace(3)> %gep, i32 1739 740 ; Apply an additional offset after the vector that will be more obviously folded.741 %gep.1.offset = getelementptr float, ptr addrspace(3) %gep.1, i32 8742 store float %val0, ptr addrspace(3) %gep.0, align 4743 744 %add.x = add nsw i32 %x.i, 8745 store float %val1, ptr addrspace(3) %gep.1.offset, align 4746 ret void747}748 749define amdgpu_kernel void @simple_write2_one_val_f64(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {750; CI-LABEL: simple_write2_one_val_f64:751; CI: ; %bb.0:752; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2753; CI-NEXT: s_mov_b32 s3, 0xf000754; CI-NEXT: s_mov_b32 s2, 0755; CI-NEXT: v_mov_b32_e32 v1, 0756; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0757; CI-NEXT: s_waitcnt lgkmcnt(0)758; CI-NEXT: buffer_load_dwordx2 v[1:2], v[0:1], s[0:3], 0 addr64759; CI-NEXT: s_mov_b32 m0, -1760; CI-NEXT: s_waitcnt vmcnt(0)761; CI-NEXT: ds_write2_b64 v0, v[1:2], v[1:2] offset1:8762; CI-NEXT: s_endpgm763;764; GFX9-LABEL: simple_write2_one_val_f64:765; GFX9: ; %bb.0:766; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8767; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0768; GFX9-NEXT: s_waitcnt lgkmcnt(0)769; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]770; GFX9-NEXT: s_waitcnt vmcnt(0)771; GFX9-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:8772; GFX9-NEXT: s_endpgm773;774; GFX1250-LABEL: simple_write2_one_val_f64:775; GFX1250: ; %bb.0:776; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1777; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8778; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0779; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)780; GFX1250-NEXT: v_and_b32_e32 v2, 0x1ff8, v0781; GFX1250-NEXT: s_wait_kmcnt 0x0782; GFX1250-NEXT: global_load_b64 v[0:1], v2, s[0:1]783; GFX1250-NEXT: s_wait_loadcnt 0x0784; GFX1250-NEXT: ds_store_2addr_b64 v2, v[0:1], v[0:1] offset1:8785; GFX1250-NEXT: s_endpgm786 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1787 %in.gep = getelementptr double, ptr addrspace(1) %in, i32 %x.i788 %val = load double, ptr addrspace(1) %in.gep, align 8789 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i790 store double %val, ptr addrspace(3) %arrayidx0, align 8791 %add.x = add nsw i32 %x.i, 8792 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x793 store double %val, ptr addrspace(3) %arrayidx1, align 8794 ret void795}796 797define amdgpu_kernel void @misaligned_simple_write2_one_val_f64(ptr addrspace(1) %C, ptr addrspace(1) %in, ptr addrspace(3) %lds) #0 {798; CI-LABEL: misaligned_simple_write2_one_val_f64:799; CI: ; %bb.0:800; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2801; CI-NEXT: s_load_dword s4, s[4:5], 0x4802; CI-NEXT: s_mov_b32 s3, 0xf000803; CI-NEXT: s_mov_b32 s2, 0804; CI-NEXT: v_mov_b32_e32 v1, 0805; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0806; CI-NEXT: s_waitcnt lgkmcnt(0)807; CI-NEXT: buffer_load_dwordx2 v[1:2], v[0:1], s[0:3], 0 addr64808; CI-NEXT: v_add_i32_e32 v0, vcc, s4, v0809; CI-NEXT: s_mov_b32 m0, -1810; CI-NEXT: s_waitcnt vmcnt(0)811; CI-NEXT: ds_write2_b32 v0, v1, v2 offset1:1812; CI-NEXT: ds_write2_b32 v0, v1, v2 offset0:14 offset1:15813; CI-NEXT: s_endpgm814;815; GFX9-LABEL: misaligned_simple_write2_one_val_f64:816; GFX9: ; %bb.0:817; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8818; GFX9-NEXT: s_load_dword s2, s[4:5], 0x10819; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0820; GFX9-NEXT: s_waitcnt lgkmcnt(0)821; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]822; GFX9-NEXT: v_add_u32_e32 v2, s2, v2823; GFX9-NEXT: s_waitcnt vmcnt(0)824; GFX9-NEXT: ds_write2_b32 v2, v0, v1 offset1:1825; GFX9-NEXT: ds_write2_b32 v2, v0, v1 offset0:14 offset1:15826; GFX9-NEXT: s_endpgm827;828; GFX1250-LABEL: misaligned_simple_write2_one_val_f64:829; GFX1250: ; %bb.0:830; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1831; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x8832; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0833; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)834; GFX1250-NEXT: v_and_b32_e32 v2, 0x1ff8, v0835; GFX1250-NEXT: s_wait_kmcnt 0x0836; GFX1250-NEXT: global_load_b64 v[0:1], v2, s[0:1]837; GFX1250-NEXT: s_wait_xcnt 0x0838; GFX1250-NEXT: v_add_nc_u32_e32 v2, s2, v2839; GFX1250-NEXT: s_wait_loadcnt 0x0840; GFX1250-NEXT: ds_store_2addr_b32 v2, v0, v1 offset1:1841; GFX1250-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:14 offset1:15842; GFX1250-NEXT: s_endpgm843 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1844 %in.gep = getelementptr double, ptr addrspace(1) %in, i32 %x.i845 %val = load double, ptr addrspace(1) %in.gep, align 8846 %arrayidx0 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %x.i847 store double %val, ptr addrspace(3) %arrayidx0, align 4848 %add.x = add nsw i32 %x.i, 7849 %arrayidx1 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %add.x850 store double %val, ptr addrspace(3) %arrayidx1, align 4851 ret void852}853 854define amdgpu_kernel void @unaligned_offset_simple_write2_one_val_f64(ptr addrspace(1) %C, ptr addrspace(1) %in, ptr addrspace(3) %lds) #0 {855; CI-LABEL: unaligned_offset_simple_write2_one_val_f64:856; CI: ; %bb.0:857; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2858; CI-NEXT: s_load_dword s4, s[4:5], 0x4859; CI-NEXT: s_mov_b32 s3, 0xf000860; CI-NEXT: s_mov_b32 s2, 0861; CI-NEXT: v_mov_b32_e32 v1, 0862; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0863; CI-NEXT: s_waitcnt lgkmcnt(0)864; CI-NEXT: buffer_load_dwordx2 v[1:2], v[0:1], s[0:3], 0 addr64865; CI-NEXT: v_add_i32_e32 v0, vcc, s4, v0866; CI-NEXT: s_mov_b32 m0, -1867; CI-NEXT: s_waitcnt vmcnt(0)868; CI-NEXT: ds_write_b8 v0, v1 offset:9869; CI-NEXT: ds_write_b8 v0, v2 offset:13870; CI-NEXT: v_lshrrev_b32_e32 v3, 24, v1871; CI-NEXT: ds_write_b8 v0, v1 offset:5872; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v1873; CI-NEXT: v_lshrrev_b32_e32 v5, 8, v1874; CI-NEXT: v_lshrrev_b32_e32 v1, 24, v2875; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2876; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2877; CI-NEXT: ds_write_b8 v0, v3 offset:8878; CI-NEXT: ds_write_b8 v0, v4 offset:7879; CI-NEXT: ds_write_b8 v0, v5 offset:6880; CI-NEXT: ds_write_b8 v0, v3 offset:12881; CI-NEXT: ds_write_b8 v0, v4 offset:11882; CI-NEXT: ds_write_b8 v0, v5 offset:10883; CI-NEXT: ds_write_b8 v0, v1 offset:16884; CI-NEXT: ds_write_b8 v0, v6 offset:15885; CI-NEXT: ds_write_b8 v0, v2 offset:14886; CI-NEXT: s_endpgm887;888; GFX9-ALIGNED-LABEL: unaligned_offset_simple_write2_one_val_f64:889; GFX9-ALIGNED: ; %bb.0:890; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8891; GFX9-ALIGNED-NEXT: s_load_dword s2, s[4:5], 0x10892; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v2, 3, v0893; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)894; GFX9-ALIGNED-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]895; GFX9-ALIGNED-NEXT: v_add_u32_e32 v2, s2, v2896; GFX9-ALIGNED-NEXT: s_waitcnt vmcnt(0)897; GFX9-ALIGNED-NEXT: ds_write_b8_d16_hi v2, v0 offset:7898; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v0 offset:5899; GFX9-ALIGNED-NEXT: v_lshrrev_b32_e32 v3, 24, v0900; GFX9-ALIGNED-NEXT: v_lshrrev_b32_e32 v4, 8, v0901; GFX9-ALIGNED-NEXT: ds_write_b8_d16_hi v2, v0 offset:11902; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v0 offset:9903; GFX9-ALIGNED-NEXT: ds_write_b8_d16_hi v2, v1 offset:15904; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v1 offset:13905; GFX9-ALIGNED-NEXT: v_lshrrev_b32_e32 v0, 24, v1906; GFX9-ALIGNED-NEXT: v_lshrrev_b32_e32 v1, 8, v1907; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v3 offset:8908; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v4 offset:6909; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v3 offset:12910; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v4 offset:10911; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v0 offset:16912; GFX9-ALIGNED-NEXT: ds_write_b8 v2, v1 offset:14913; GFX9-ALIGNED-NEXT: s_endpgm914;915; GFX9-UNALIGNED-LABEL: unaligned_offset_simple_write2_one_val_f64:916; GFX9-UNALIGNED: ; %bb.0:917; GFX9-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8918; GFX9-UNALIGNED-NEXT: s_load_dword s2, s[4:5], 0x10919; GFX9-UNALIGNED-NEXT: v_lshlrev_b32_e32 v2, 3, v0920; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)921; GFX9-UNALIGNED-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]922; GFX9-UNALIGNED-NEXT: v_add_u32_e32 v2, s2, v2923; GFX9-UNALIGNED-NEXT: s_waitcnt vmcnt(0)924; GFX9-UNALIGNED-NEXT: ds_write_b64 v2, v[0:1] offset:5925; GFX9-UNALIGNED-NEXT: ds_write_b64 v2, v[0:1] offset:9926; GFX9-UNALIGNED-NEXT: s_endpgm927;928; GFX1250-LABEL: unaligned_offset_simple_write2_one_val_f64:929; GFX1250: ; %bb.0:930; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1931; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x8932; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0933; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)934; GFX1250-NEXT: v_and_b32_e32 v2, 0x1ff8, v0935; GFX1250-NEXT: s_wait_kmcnt 0x0936; GFX1250-NEXT: global_load_b64 v[0:1], v2, s[0:1]937; GFX1250-NEXT: s_wait_xcnt 0x0938; GFX1250-NEXT: v_add_nc_u32_e32 v2, s2, v2939; GFX1250-NEXT: s_wait_loadcnt 0x0940; GFX1250-NEXT: ds_store_b64 v2, v[0:1] offset:5941; GFX1250-NEXT: ds_store_b64 v2, v[0:1] offset:9942; GFX1250-NEXT: s_endpgm943 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1944 %in.gep = getelementptr double, ptr addrspace(1) %in, i32 %x.i945 %val = load double, ptr addrspace(1) %in.gep, align 8946 %base = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %x.i947 %addr0.i8 = getelementptr inbounds i8, ptr addrspace(3) %base, i32 5948 store double %val, ptr addrspace(3) %addr0.i8, align 1949 %addr1.i8 = getelementptr inbounds i8, ptr addrspace(3) %base, i32 9950 store double %val, ptr addrspace(3) %addr1.i8, align 1951 ret void952}953 954define amdgpu_kernel void @simple_write2_two_val_f64(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {955; CI-LABEL: simple_write2_two_val_f64:956; CI: ; %bb.0:957; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2958; CI-NEXT: s_mov_b32 s3, 0xf000959; CI-NEXT: s_mov_b32 s2, 0960; CI-NEXT: v_mov_b32_e32 v1, 0961; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0962; CI-NEXT: s_waitcnt lgkmcnt(0)963; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc964; CI-NEXT: s_waitcnt vmcnt(0)965; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc966; CI-NEXT: s_waitcnt vmcnt(0)967; CI-NEXT: s_mov_b32 m0, -1968; CI-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset1:8969; CI-NEXT: s_endpgm970;971; GFX9-LABEL: simple_write2_two_val_f64:972; GFX9: ; %bb.0:973; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8974; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0975; GFX9-NEXT: s_waitcnt lgkmcnt(0)976; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1] glc977; GFX9-NEXT: s_waitcnt vmcnt(0)978; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[0:1] offset:8 glc979; GFX9-NEXT: s_waitcnt vmcnt(0)980; GFX9-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:8981; GFX9-NEXT: s_endpgm982;983; GFX1250-LABEL: simple_write2_two_val_f64:984; GFX1250: ; %bb.0:985; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1986; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8987; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 3, v0988; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)989; GFX1250-NEXT: v_and_b32_e32 v4, 0x1ff8, v0990; GFX1250-NEXT: s_wait_kmcnt 0x0991; GFX1250-NEXT: global_load_b64 v[0:1], v4, s[0:1] scope:SCOPE_SYS992; GFX1250-NEXT: s_wait_loadcnt 0x0993; GFX1250-NEXT: global_load_b64 v[2:3], v4, s[0:1] offset:8 scope:SCOPE_SYS994; GFX1250-NEXT: s_wait_loadcnt 0x0995; GFX1250-NEXT: ds_store_2addr_b64 v4, v[0:1], v[2:3] offset1:8996; GFX1250-NEXT: s_endpgm997 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1998 %in.gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %x.i999 %in.gep.1 = getelementptr double, ptr addrspace(1) %in.gep.0, i32 11000 %val0 = load volatile double, ptr addrspace(1) %in.gep.0, align 81001 %val1 = load volatile double, ptr addrspace(1) %in.gep.1, align 81002 %arrayidx0 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %x.i1003 store double %val0, ptr addrspace(3) %arrayidx0, align 81004 %add.x = add nsw i32 %x.i, 81005 %arrayidx1 = getelementptr inbounds [512 x double], ptr addrspace(3) @lds.f64, i32 0, i32 %add.x1006 store double %val1, ptr addrspace(3) %arrayidx1, align 81007 ret void1008}1009 1010@foo = addrspace(3) global [4 x i32] poison, align 41011 1012define amdgpu_kernel void @store_constant_adjacent_offsets() {1013; CI-LABEL: store_constant_adjacent_offsets:1014; CI: ; %bb.0:1015; CI-NEXT: v_mov_b32_e32 v0, 0x7b1016; CI-NEXT: v_mov_b32_e32 v1, v01017; CI-NEXT: v_mov_b32_e32 v2, 01018; CI-NEXT: s_mov_b32 m0, -11019; CI-NEXT: ds_write_b64 v2, v[0:1]1020; CI-NEXT: s_endpgm1021;1022; GFX9-LABEL: store_constant_adjacent_offsets:1023; GFX9: ; %bb.0:1024; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b1025; GFX9-NEXT: v_mov_b32_e32 v1, v01026; GFX9-NEXT: v_mov_b32_e32 v2, 01027; GFX9-NEXT: ds_write_b64 v2, v[0:1]1028; GFX9-NEXT: s_endpgm1029;1030; GFX1250-LABEL: store_constant_adjacent_offsets:1031; GFX1250: ; %bb.0:1032; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11033; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0x7b0000007b1034; GFX1250-NEXT: v_mov_b32_e32 v2, 01035; GFX1250-NEXT: ds_store_b64 v2, v[0:1]1036; GFX1250-NEXT: s_endpgm1037 store i32 123, ptr addrspace(3) @foo, align 41038 store i32 123, ptr addrspace(3) getelementptr inbounds ([4 x i32], ptr addrspace(3) @foo, i32 0, i32 1), align 41039 ret void1040}1041 1042define amdgpu_kernel void @store_constant_disjoint_offsets() {1043; CI-LABEL: store_constant_disjoint_offsets:1044; CI: ; %bb.0:1045; CI-NEXT: v_mov_b32_e32 v0, 0x7b1046; CI-NEXT: v_mov_b32_e32 v1, 01047; CI-NEXT: s_mov_b32 m0, -11048; CI-NEXT: ds_write2_b32 v1, v0, v0 offset1:21049; CI-NEXT: s_endpgm1050;1051; GFX9-LABEL: store_constant_disjoint_offsets:1052; GFX9: ; %bb.0:1053; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b1054; GFX9-NEXT: v_mov_b32_e32 v1, 01055; GFX9-NEXT: ds_write2_b32 v1, v0, v0 offset1:21056; GFX9-NEXT: s_endpgm1057;1058; GFX1250-LABEL: store_constant_disjoint_offsets:1059; GFX1250: ; %bb.0:1060; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11061; GFX1250-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 01062; GFX1250-NEXT: ds_store_2addr_b32 v1, v0, v0 offset1:21063; GFX1250-NEXT: s_endpgm1064 store i32 123, ptr addrspace(3) @foo, align 41065 store i32 123, ptr addrspace(3) getelementptr inbounds ([4 x i32], ptr addrspace(3) @foo, i32 0, i32 2), align 41066 ret void1067}1068 1069@bar = addrspace(3) global [4 x i64] poison, align 41070 1071define amdgpu_kernel void @store_misaligned64_constant_offsets() {1072; CI-LABEL: store_misaligned64_constant_offsets:1073; CI: ; %bb.0:1074; CI-NEXT: v_mov_b32_e32 v0, 0x7b1075; CI-NEXT: v_mov_b32_e32 v1, 01076; CI-NEXT: v_mov_b32_e32 v2, v01077; CI-NEXT: v_mov_b32_e32 v3, v11078; CI-NEXT: s_mov_b32 m0, -11079; CI-NEXT: ds_write_b128 v1, v[0:3]1080; CI-NEXT: s_endpgm1081;1082; GFX9-LABEL: store_misaligned64_constant_offsets:1083; GFX9: ; %bb.0:1084; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b1085; GFX9-NEXT: v_mov_b32_e32 v1, 01086; GFX9-NEXT: v_mov_b32_e32 v2, v01087; GFX9-NEXT: v_mov_b32_e32 v3, v11088; GFX9-NEXT: ds_write_b128 v1, v[0:3]1089; GFX9-NEXT: s_endpgm1090;1091; GFX1250-LABEL: store_misaligned64_constant_offsets:1092; GFX1250: ; %bb.0:1093; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11094; GFX1250-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 01095; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1096; GFX1250-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, v11097; GFX1250-NEXT: ds_store_b128 v1, v[0:3]1098; GFX1250-NEXT: s_endpgm1099 store i64 123, ptr addrspace(3) @bar, align 41100 store i64 123, ptr addrspace(3) getelementptr inbounds ([4 x i64], ptr addrspace(3) @bar, i32 0, i32 1), align 41101 ret void1102}1103 1104@bar.large = addrspace(3) global [4096 x i64] poison, align 41105 1106define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {1107; CI-LABEL: store_misaligned64_constant_large_offsets:1108; CI: ; %bb.0:1109; CI-NEXT: s_mov_b64 s[0:1], 0x7b1110; CI-NEXT: v_mov_b32_e32 v0, s01111; CI-NEXT: v_mov_b32_e32 v2, 01112; CI-NEXT: v_mov_b32_e32 v1, s11113; CI-NEXT: s_mov_b32 m0, -11114; CI-NEXT: ds_write_b64 v2, v[0:1] offset:163841115; CI-NEXT: ds_write_b64 v2, v[0:1] offset:327601116; CI-NEXT: s_endpgm1117;1118; GFX9-LABEL: store_misaligned64_constant_large_offsets:1119; GFX9: ; %bb.0:1120; GFX9-NEXT: s_mov_b64 s[0:1], 0x7b1121; GFX9-NEXT: v_mov_b32_e32 v0, s01122; GFX9-NEXT: v_mov_b32_e32 v2, 01123; GFX9-NEXT: v_mov_b32_e32 v1, s11124; GFX9-NEXT: ds_write_b64 v2, v[0:1] offset:163841125; GFX9-NEXT: ds_write_b64 v2, v[0:1] offset:327601126; GFX9-NEXT: s_endpgm1127;1128; GFX1250-LABEL: store_misaligned64_constant_large_offsets:1129; GFX1250: ; %bb.0:1130; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11131; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0x7b1132; GFX1250-NEXT: v_mov_b32_e32 v2, 01133; GFX1250-NEXT: ds_store_b64 v2, v[0:1] offset:163841134; GFX1250-NEXT: ds_store_b64 v2, v[0:1] offset:327601135; GFX1250-NEXT: s_endpgm1136 store i64 123, ptr addrspace(3) getelementptr inbounds ([4096 x i64], ptr addrspace(3) @bar.large, i32 0, i32 2048), align 41137 store i64 123, ptr addrspace(3) getelementptr inbounds ([4096 x i64], ptr addrspace(3) @bar.large, i32 0, i32 4095), align 41138 ret void1139}1140 1141@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] poison, align 41142@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] poison, align 41143 1144define amdgpu_kernel void @write2_sgemm_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb, ptr addrspace(1) %in) #0 {1145; CI-LABEL: write2_sgemm_sequence:1146; CI: ; %bb.0:1147; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x41148; CI-NEXT: s_mov_b32 m0, -11149; CI-NEXT: s_waitcnt lgkmcnt(0)1150; CI-NEXT: s_load_dword s0, s[0:1], 0x01151; CI-NEXT: s_lshl_b32 s1, s8, 21152; CI-NEXT: s_add_i32 s2, s1, 0xc201153; CI-NEXT: s_addk_i32 s1, 0xc601154; CI-NEXT: v_mov_b32_e32 v0, s21155; CI-NEXT: s_waitcnt lgkmcnt(0)1156; CI-NEXT: v_mov_b32_e32 v2, s01157; CI-NEXT: v_mov_b32_e32 v3, s01158; CI-NEXT: ds_write2_b32 v0, v2, v3 offset1:11159; CI-NEXT: v_mov_b32_e32 v0, s11160; CI-NEXT: ds_write2_b32 v0, v2, v3 offset1:11161; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v11162; CI-NEXT: ds_write2_b32 v0, v2, v3 offset1:11163; CI-NEXT: ds_write2_b32 v0, v2, v3 offset0:32 offset1:331164; CI-NEXT: ds_write2_b32 v0, v2, v3 offset0:64 offset1:651165; CI-NEXT: s_endpgm1166;1167; GFX9-LABEL: write2_sgemm_sequence:1168; GFX9: ; %bb.0:1169; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x101170; GFX9-NEXT: s_lshl_b32 s2, s8, 21171; GFX9-NEXT: s_waitcnt lgkmcnt(0)1172; GFX9-NEXT: s_load_dword s0, s[0:1], 0x01173; GFX9-NEXT: s_add_i32 s1, s2, 0xc201174; GFX9-NEXT: s_addk_i32 s2, 0xc601175; GFX9-NEXT: v_mov_b32_e32 v0, s11176; GFX9-NEXT: v_mov_b32_e32 v2, s21177; GFX9-NEXT: s_waitcnt lgkmcnt(0)1178; GFX9-NEXT: v_mov_b32_e32 v3, s01179; GFX9-NEXT: v_mov_b32_e32 v4, s01180; GFX9-NEXT: ds_write2_b32 v0, v3, v4 offset1:11181; GFX9-NEXT: ds_write2_b32 v2, v3, v4 offset1:11182; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v11183; GFX9-NEXT: ds_write2_b32 v0, v3, v4 offset1:11184; GFX9-NEXT: ds_write2_b32 v0, v3, v4 offset0:32 offset1:331185; GFX9-NEXT: ds_write2_b32 v0, v3, v4 offset0:64 offset1:651186; GFX9-NEXT: s_endpgm1187;1188; GFX1250-LABEL: write2_sgemm_sequence:1189; GFX1250: ; %bb.0:1190; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11191; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x101192; GFX1250-NEXT: s_and_b32 s2, ttmp6, 151193; GFX1250-NEXT: s_getreg_b32 s3, hwreg(HW_REG_IB_STS2, 6, 4)1194; GFX1250-NEXT: s_wait_kmcnt 0x01195; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0x01196; GFX1250-NEXT: s_wait_xcnt 0x01197; GFX1250-NEXT: s_bfe_u32 s1, ttmp6, 0x4000c1198; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1199; GFX1250-NEXT: s_add_co_i32 s1, s1, 11200; GFX1250-NEXT: s_mul_i32 s1, ttmp9, s11201; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)1202; GFX1250-NEXT: s_add_co_i32 s2, s2, s11203; GFX1250-NEXT: s_cmp_eq_u32 s3, 01204; GFX1250-NEXT: s_cselect_b32 s1, ttmp9, s21205; GFX1250-NEXT: s_lshl_b32 s1, s1, 21206; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1207; GFX1250-NEXT: s_add_co_i32 s2, s1, 0xc201208; GFX1250-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_lshrrev_b32 v0, 8, v01209; GFX1250-NEXT: s_addk_co_i32 s1, 0xc601210; GFX1250-NEXT: s_wait_kmcnt 0x01211; GFX1250-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v2, s01212; GFX1250-NEXT: v_mov_b32_e32 v3, s01213; GFX1250-NEXT: v_and_b32_e32 v0, 0xffc, v01214; GFX1250-NEXT: ds_store_2addr_b32 v1, v2, v3 offset1:11215; GFX1250-NEXT: ds_store_2addr_b32 v4, v2, v3 offset1:11216; GFX1250-NEXT: ds_store_2addr_b32 v0, v2, v3 offset1:11217; GFX1250-NEXT: ds_store_2addr_b32 v0, v2, v3 offset0:32 offset1:331218; GFX1250-NEXT: ds_store_2addr_b32 v0, v2, v3 offset0:64 offset1:651219; GFX1250-NEXT: s_endpgm1220 %x.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #11221 %y.i = tail call i32 @llvm.amdgcn.workitem.id.y() #11222 %val = load float, ptr addrspace(1) %in1223 %arrayidx44 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %x.i1224 store float %val, ptr addrspace(3) %arrayidx44, align 41225 %add47 = add nsw i32 %x.i, 11226 %arrayidx48 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add471227 store float %val, ptr addrspace(3) %arrayidx48, align 41228 %add51 = add nsw i32 %x.i, 161229 %arrayidx52 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add511230 store float %val, ptr addrspace(3) %arrayidx52, align 41231 %add55 = add nsw i32 %x.i, 171232 %arrayidx56 = getelementptr inbounds [264 x float], ptr addrspace(3) @sgemm.lA, i32 0, i32 %add551233 store float %val, ptr addrspace(3) %arrayidx56, align 41234 %arrayidx60 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %y.i1235 store float %val, ptr addrspace(3) %arrayidx60, align 41236 %add63 = add nsw i32 %y.i, 11237 %arrayidx64 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add631238 store float %val, ptr addrspace(3) %arrayidx64, align 41239 %add67 = add nsw i32 %y.i, 321240 %arrayidx68 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add671241 store float %val, ptr addrspace(3) %arrayidx68, align 41242 %add71 = add nsw i32 %y.i, 331243 %arrayidx72 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add711244 store float %val, ptr addrspace(3) %arrayidx72, align 41245 %add75 = add nsw i32 %y.i, 641246 %arrayidx76 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add751247 store float %val, ptr addrspace(3) %arrayidx76, align 41248 %add79 = add nsw i32 %y.i, 651249 %arrayidx80 = getelementptr inbounds [776 x float], ptr addrspace(3) @sgemm.lB, i32 0, i32 %add791250 store float %val, ptr addrspace(3) %arrayidx80, align 41251 ret void1252}1253 1254define amdgpu_kernel void @simple_write2_v4f32_superreg_align4(ptr addrspace(3) %out, ptr addrspace(1) %in) #0 {1255; CI-LABEL: simple_write2_v4f32_superreg_align4:1256; CI: ; %bb.0:1257; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x21258; CI-NEXT: s_load_dword s4, s[4:5], 0x01259; CI-NEXT: v_lshlrev_b32_e32 v0, 4, v01260; CI-NEXT: s_mov_b32 m0, -11261; CI-NEXT: s_waitcnt lgkmcnt(0)1262; CI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x01263; CI-NEXT: v_add_i32_e32 v0, vcc, s4, v01264; CI-NEXT: s_waitcnt lgkmcnt(0)1265; CI-NEXT: v_mov_b32_e32 v1, s01266; CI-NEXT: v_mov_b32_e32 v2, s11267; CI-NEXT: v_mov_b32_e32 v3, s21268; CI-NEXT: ds_write2_b32 v0, v1, v2 offset1:11269; CI-NEXT: v_mov_b32_e32 v1, s31270; CI-NEXT: ds_write2_b32 v0, v3, v1 offset0:2 offset1:31271; CI-NEXT: s_endpgm1272;1273; GFX9-ALIGNED-LABEL: simple_write2_v4f32_superreg_align4:1274; GFX9-ALIGNED: ; %bb.0:1275; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x81276; GFX9-ALIGNED-NEXT: s_load_dword s8, s[4:5], 0x01277; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)1278; GFX9-ALIGNED-NEXT: v_lshl_add_u32 v0, v0, 4, s81279; GFX9-ALIGNED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x01280; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)1281; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v1, s01282; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v2, s11283; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v3, s21284; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v4, s31285; GFX9-ALIGNED-NEXT: ds_write2_b32 v0, v1, v2 offset1:11286; GFX9-ALIGNED-NEXT: ds_write2_b32 v0, v3, v4 offset0:2 offset1:31287; GFX9-ALIGNED-NEXT: s_endpgm1288;1289; GFX9-UNALIGNED-LABEL: simple_write2_v4f32_superreg_align4:1290; GFX9-UNALIGNED: ; %bb.0:1291; GFX9-UNALIGNED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x81292; GFX9-UNALIGNED-NEXT: s_load_dword s8, s[4:5], 0x01293; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)1294; GFX9-UNALIGNED-NEXT: v_lshl_add_u32 v0, v0, 4, s81295; GFX9-UNALIGNED-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x01296; GFX9-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0)1297; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v1, s21298; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v2, s31299; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v3, s01300; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v4, s11301; GFX9-UNALIGNED-NEXT: ds_write2_b32 v0, v1, v2 offset0:2 offset1:31302; GFX9-UNALIGNED-NEXT: ds_write2_b32 v0, v3, v4 offset1:11303; GFX9-UNALIGNED-NEXT: s_endpgm1304;1305; GFX1250-LABEL: simple_write2_v4f32_superreg_align4:1306; GFX1250: ; %bb.0:1307; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11308; GFX1250-NEXT: s_clause 0x11309; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x81310; GFX1250-NEXT: s_load_b32 s8, s[4:5], 0x01311; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v01312; GFX1250-NEXT: s_wait_kmcnt 0x01313; GFX1250-NEXT: s_load_b128 s[0:3], s[6:7], 0x01314; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1315; GFX1250-NEXT: v_lshl_add_u32 v0, v0, 4, s81316; GFX1250-NEXT: s_wait_kmcnt 0x01317; GFX1250-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s31318; GFX1250-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v4, s11319; GFX1250-NEXT: ds_store_2addr_b32 v0, v1, v2 offset0:2 offset1:31320; GFX1250-NEXT: ds_store_2addr_b32 v0, v3, v4 offset1:11321; GFX1250-NEXT: s_endpgm1322 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #11323 %in.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %in1324 %val0 = load <4 x float>, ptr addrspace(1) %in.gep, align 41325 %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(3) %out, i32 %x.i1326 store <4 x float> %val0, ptr addrspace(3) %out.gep, align 41327 ret void1328}1329 1330@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] poison, align 11331 1332define amdgpu_kernel void @write2_v2i32_align1_odd_offset() {1333; CI-LABEL: write2_v2i32_align1_odd_offset:1334; CI: ; %bb.0: ; %entry1335; CI-NEXT: v_mov_b32_e32 v0, 0x7b1336; CI-NEXT: v_mov_b32_e32 v1, 01337; CI-NEXT: s_mov_b32 m0, -11338; CI-NEXT: ds_write_b8 v1, v0 offset:651339; CI-NEXT: v_mov_b32_e32 v0, 11340; CI-NEXT: ds_write_b8 v1, v0 offset:701341; CI-NEXT: v_mov_b32_e32 v0, 0xc81342; CI-NEXT: ds_write_b8 v1, v0 offset:691343; CI-NEXT: ds_write_b8 v1, v1 offset:681344; CI-NEXT: ds_write_b8 v1, v1 offset:671345; CI-NEXT: ds_write_b8 v1, v1 offset:661346; CI-NEXT: ds_write_b8 v1, v1 offset:721347; CI-NEXT: ds_write_b8 v1, v1 offset:711348; CI-NEXT: s_endpgm1349;1350; GFX9-ALIGNED-LABEL: write2_v2i32_align1_odd_offset:1351; GFX9-ALIGNED: ; %bb.0: ; %entry1352; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v0, 0x7b1353; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v1, 01354; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v0 offset:651355; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v0, 11356; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v0 offset:701357; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v0, 0xc81358; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v0 offset:691359; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:681360; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:671361; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:661362; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:721363; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:711364; GFX9-ALIGNED-NEXT: s_endpgm1365;1366; GFX9-UNALIGNED-LABEL: write2_v2i32_align1_odd_offset:1367; GFX9-UNALIGNED: ; %bb.0: ; %entry1368; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v0, 0x7b1369; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v1, 0x1c81370; GFX9-UNALIGNED-NEXT: v_mov_b32_e32 v2, 01371; GFX9-UNALIGNED-NEXT: ds_write_b64 v2, v[0:1] offset:651372; GFX9-UNALIGNED-NEXT: s_endpgm1373;1374; GFX1250-LABEL: write2_v2i32_align1_odd_offset:1375; GFX1250: ; %bb.0: ; %entry1376; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11377; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0x1c80000007b1378; GFX1250-NEXT: v_mov_b32_e32 v2, 01379; GFX1250-NEXT: ds_store_b64 v2, v[0:1] offset:651380; GFX1250-NEXT: s_endpgm1381entry:1382 store <2 x i32> <i32 123, i32 456>, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @v2i32_align1, i32 65), align 11383 ret void1384}1385 1386declare i32 @llvm.amdgcn.workgroup.id.x() #11387declare i32 @llvm.amdgcn.workgroup.id.y() #11388declare i32 @llvm.amdgcn.workitem.id.x() #11389declare i32 @llvm.amdgcn.workitem.id.y() #11390 1391attributes #0 = { nounwind }1392attributes #1 = { nounwind readnone speculatable }1393attributes #2 = { convergent nounwind }1394;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1395; GFX1250-UNALIGNED: {{.*}}1396