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1; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s3 4@lds = addrspace(3) global [512 x float] poison, align 45 6; GCN-LABEL: @simple_write2st64_one_val_f32_0_17; CI-DAG: s_mov_b32 m08; GFX9-NOT: m09 10; GCN-DAG: {{buffer|global}}_load_dword [[VAL:v[0-9]+]]11; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}12; GCN: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:113; GCN: s_endpgm14define amdgpu_kernel void @simple_write2st64_one_val_f32_0_1(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {15 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #116 %in.gep = getelementptr float, ptr addrspace(1) %in, i32 %x.i17 %val = load float, ptr addrspace(1) %in.gep, align 418 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %x.i19 store float %val, ptr addrspace(3) %arrayidx0, align 420 %add.x = add nsw i32 %x.i, 6421 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x22 store float %val, ptr addrspace(3) %arrayidx1, align 423 ret void24}25 26; GCN-LABEL: @simple_write2st64_two_val_f32_2_527; CI-DAG: s_mov_b32 m028; GFX9-NOT: m029 30; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}31; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:432 33; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} glc{{$}}34; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4 glc{{$}}35 36 37; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}38; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:539; GCN: s_endpgm40define amdgpu_kernel void @simple_write2st64_two_val_f32_2_5(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {41 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #142 %in.gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %x.i43 %in.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 144 %val0 = load volatile float, ptr addrspace(1) %in.gep.0, align 445 %val1 = load volatile float, ptr addrspace(1) %in.gep.1, align 446 %add.x.0 = add nsw i32 %x.i, 12847 %arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x.048 store float %val0, ptr addrspace(3) %arrayidx0, align 449 %add.x.1 = add nsw i32 %x.i, 32050 %arrayidx1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 %add.x.151 store float %val1, ptr addrspace(3) %arrayidx1, align 452 ret void53}54 55; GCN-LABEL: @simple_write2st64_two_val_max_offset_f3256; CI-DAG: s_mov_b32 m057; GFX9-NOT: m058 59; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}60; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:461 62; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} glc{{$}}63; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:464 65; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v{{[0-9]+}}66; GCN-DAG: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]]67; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:25568; GCN: s_endpgm69define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f32(ptr addrspace(1) %C, ptr addrspace(1) %in, ptr addrspace(3) %lds) #0 {70 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #171 %in.gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %x.i72 %in.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 173 %val0 = load volatile float, ptr addrspace(1) %in.gep.0, align 474 %val1 = load volatile float, ptr addrspace(1) %in.gep.1, align 475 %arrayidx0 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %x.i76 store float %val0, ptr addrspace(3) %arrayidx0, align 477 %add.x = add nsw i32 %x.i, 1632078 %arrayidx1 = getelementptr inbounds float, ptr addrspace(3) %lds, i32 %add.x79 store float %val1, ptr addrspace(3) %arrayidx1, align 480 ret void81}82 83; GCN-LABEL: @simple_write2st64_two_val_max_offset_f6484; CI-DAG: s_mov_b32 m085; GFX9-NOT: m086 87; CI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}88; CI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:889 90; GFX9-DAG: global_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} glc{{$}}91; GFX9-DAG: global_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:892 93; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 3, v{{[0-9]+}}94; GCN-DAG: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]]95; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:12796; GCN: s_endpgm97define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f64(ptr addrspace(1) %C, ptr addrspace(1) %in, ptr addrspace(3) %lds) #0 {98 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #199 %in.gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %x.i100 %in.gep.1 = getelementptr double, ptr addrspace(1) %in.gep.0, i32 1101 %val0 = load volatile double, ptr addrspace(1) %in.gep.0, align 8102 %val1 = load volatile double, ptr addrspace(1) %in.gep.1, align 8103 %add.x.0 = add nsw i32 %x.i, 256104 %arrayidx0 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %add.x.0105 store double %val0, ptr addrspace(3) %arrayidx0, align 8106 %add.x.1 = add nsw i32 %x.i, 8128107 %arrayidx1 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %add.x.1108 store double %val1, ptr addrspace(3) %arrayidx1, align 8109 ret void110}111 112; GCN-LABEL: @byte_size_only_divisible_64_write2st64_f64113; CI-DAG: s_mov_b32 m0114; GFX9-NOT: m0115 116; GCN-NOT: ds_write2st64_b64117; GCN: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:8118; GCN: s_endpgm119define amdgpu_kernel void @byte_size_only_divisible_64_write2st64_f64(ptr addrspace(1) %C, ptr addrspace(1) %in, ptr addrspace(3) %lds) #0 {120 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1121 %in.gep = getelementptr double, ptr addrspace(1) %in, i32 %x.i122 %val = load double, ptr addrspace(1) %in.gep, align 8123 %arrayidx0 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %x.i124 store double %val, ptr addrspace(3) %arrayidx0, align 8125 %add.x = add nsw i32 %x.i, 8126 %arrayidx1 = getelementptr inbounds double, ptr addrspace(3) %lds, i32 %add.x127 store double %val, ptr addrspace(3) %arrayidx1, align 8128 ret void129}130 131declare i32 @llvm.amdgcn.workitem.id.x() #1132declare i32 @llvm.amdgcn.workitem.id.y() #1133 134attributes #0 = { nounwind }135attributes #1 = { nounwind readnone }136attributes #2 = { convergent nounwind }137