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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=CHECK,CHECK-TRUE16 %s3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=CHECK,CHECK-FAKE16 %s4 5; Make sure we use a stack pointer and allocate 112 * 4 bytes at the beginning of the stack.6 7define amdgpu_cs void @amdgpu_cs() #0 {8; CHECK-LABEL: amdgpu_cs:9; CHECK: ; %bb.0:10; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)11; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)12; CHECK-NEXT: s_cmp_lg_u32 0, s3313; CHECK-NEXT: s_cmovk_i32 s33, 0x1c014; CHECK-NEXT: s_alloc_vgpr 015; CHECK-NEXT: s_endpgm16 ret void17}18 19define amdgpu_kernel void @kernel() #0 {20; CHECK-LABEL: kernel:21; CHECK: ; %bb.0:22; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)23; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)24; CHECK-NEXT: s_cmp_lg_u32 0, s3325; CHECK-NEXT: s_cmovk_i32 s33, 0x1c026; CHECK-NEXT: s_alloc_vgpr 027; CHECK-NEXT: s_endpgm28 ret void29}30 31define amdgpu_cs void @with_local() #0 {32; CHECK-TRUE16-LABEL: with_local:33; CHECK-TRUE16: ; %bb.0:34; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)35; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 1336; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s3337; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c038; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS39; CHECK-TRUE16-NEXT: s_wait_storecnt 0x040; CHECK-TRUE16-NEXT: s_alloc_vgpr 041; CHECK-TRUE16-NEXT: s_endpgm42;43; CHECK-FAKE16-LABEL: with_local:44; CHECK-FAKE16: ; %bb.0:45; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)46; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 1347; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s3348; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c049; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS50; CHECK-FAKE16-NEXT: s_wait_storecnt 0x051; CHECK-FAKE16-NEXT: s_alloc_vgpr 052; CHECK-FAKE16-NEXT: s_endpgm53 %local = alloca i32, addrspace(5)54 store volatile i8 13, ptr addrspace(5) %local55 ret void56}57 58; Check that we generate s_cselect for SP if we can fit59; the offset in an inline constant.60define amdgpu_cs void @with_calls_inline_const() #0 {61; CHECK-TRUE16-LABEL: with_calls_inline_const:62; CHECK-TRUE16: ; %bb.0:63; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)64; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 1565; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s3366; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi67; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c068; CHECK-TRUE16-NEXT: s_mov_b32 s0, callee@abs32@lo69; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS70; CHECK-TRUE16-NEXT: s_wait_storecnt 0x071; CHECK-TRUE16-NEXT: v_mov_b32_e32 v0, 0x4772; CHECK-TRUE16-NEXT: s_cselect_b32 s32, 0x1d0, 1673; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]74; CHECK-TRUE16-NEXT: s_alloc_vgpr 075; CHECK-TRUE16-NEXT: s_endpgm76;77; CHECK-FAKE16-LABEL: with_calls_inline_const:78; CHECK-FAKE16: ; %bb.0:79; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)80; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 1581; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s3382; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi83; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c084; CHECK-FAKE16-NEXT: s_mov_b32 s0, callee@abs32@lo85; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS86; CHECK-FAKE16-NEXT: s_wait_storecnt 0x087; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4788; CHECK-FAKE16-NEXT: s_cselect_b32 s32, 0x1d0, 1689; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]90; CHECK-FAKE16-NEXT: s_alloc_vgpr 091; CHECK-FAKE16-NEXT: s_endpgm92 %local = alloca i32, addrspace(5)93 store volatile i8 15, ptr addrspace(5) %local94 call amdgpu_gfx void @callee(i32 71)95 ret void96}97 98; Check that we generate s_mov + s_cmovk if we can't99; fit the offset for SP in an inline constant.100define amdgpu_cs void @with_calls_no_inline_const() #0 {101; CHECK-TRUE16-LABEL: with_calls_no_inline_const:102; CHECK-TRUE16: ; %bb.0:103; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)104; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15105; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33106; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi107; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0108; CHECK-TRUE16-NEXT: s_mov_b32 s0, callee@abs32@lo109; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS110; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0111; CHECK-TRUE16-NEXT: v_mov_b32_e32 v0, 0x47112; CHECK-TRUE16-NEXT: s_movk_i32 s32, 0x100113; CHECK-TRUE16-NEXT: s_cmovk_i32 s32, 0x2c0114; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]115; CHECK-TRUE16-NEXT: s_alloc_vgpr 0116; CHECK-TRUE16-NEXT: s_endpgm117;118; CHECK-FAKE16-LABEL: with_calls_no_inline_const:119; CHECK-FAKE16: ; %bb.0:120; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)121; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15122; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33123; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi124; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0125; CHECK-FAKE16-NEXT: s_mov_b32 s0, callee@abs32@lo126; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS127; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0128; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 0x47129; CHECK-FAKE16-NEXT: s_movk_i32 s32, 0x100130; CHECK-FAKE16-NEXT: s_cmovk_i32 s32, 0x2c0131; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]132; CHECK-FAKE16-NEXT: s_alloc_vgpr 0133; CHECK-FAKE16-NEXT: s_endpgm134 %local = alloca i32, i32 61, addrspace(5)135 store volatile i8 15, ptr addrspace(5) %local136 call amdgpu_gfx void @callee(i32 71)137 ret void138}139 140define amdgpu_cs void @with_spills() #0 {141; CHECK-LABEL: with_spills:142; CHECK: ; %bb.0:143; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)144; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)145; CHECK-NEXT: s_cmp_lg_u32 0, s33146; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0147; CHECK-NEXT: s_alloc_vgpr 0148; CHECK-NEXT: s_endpgm149 call void asm "; spills", "~{v40},~{v42}"()150 ret void151}152 153define amdgpu_cs void @realign_stack(<32 x i32> %x) #0 {154; CHECK-LABEL: realign_stack:155; CHECK: ; %bb.0:156; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)157; CHECK-NEXT: v_mov_b32_e32 v32, 0158; CHECK-NEXT: s_cmp_lg_u32 0, s33159; CHECK-NEXT: s_mov_b32 s1, callee@abs32@hi160; CHECK-NEXT: s_cmovk_i32 s33, 0x200161; CHECK-NEXT: s_mov_b32 s0, callee@abs32@lo162; CHECK-NEXT: scratch_store_b32 off, v32, s33 scope:SCOPE_SYS163; CHECK-NEXT: s_wait_storecnt 0x0164; CHECK-NEXT: s_clause 0x7165; CHECK-NEXT: scratch_store_b128 off, v[24:27], s33 offset:96166; CHECK-NEXT: scratch_store_b128 off, v[28:31], s33 offset:112167; CHECK-NEXT: scratch_store_b128 off, v[16:19], s33 offset:64168; CHECK-NEXT: scratch_store_b128 off, v[20:23], s33 offset:80169; CHECK-NEXT: scratch_store_b128 off, v[8:11], s33 offset:32170; CHECK-NEXT: scratch_store_b128 off, v[12:15], s33 offset:48171; CHECK-NEXT: scratch_store_b128 off, v[4:7], s33 offset:16172; CHECK-NEXT: scratch_store_b128 off, v[0:3], s33173; CHECK-NEXT: v_mov_b32_e32 v0, 0x47174; CHECK-NEXT: s_movk_i32 s32, 0x100175; CHECK-NEXT: s_cmovk_i32 s32, 0x300176; CHECK-NEXT: s_swappc_b64 s[30:31], s[0:1]177; CHECK-NEXT: s_alloc_vgpr 0178; CHECK-NEXT: s_endpgm179 %v = alloca <32 x i32>, align 128, addrspace(5)180 ; use volatile store to avoid promotion of alloca to registers181 store volatile i32 0, ptr addrspace(5) %v182 store <32 x i32> %x, ptr addrspace(5) %v183 call amdgpu_gfx void @callee(i32 71)184 ret void185}186 187define amdgpu_cs void @frame_pointer_none() #1 {188; CHECK-TRUE16-LABEL: frame_pointer_none:189; CHECK-TRUE16: ; %bb.0:190; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)191; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13192; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33193; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0194; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS195; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0196; CHECK-TRUE16-NEXT: s_alloc_vgpr 0197; CHECK-TRUE16-NEXT: s_endpgm198;199; CHECK-FAKE16-LABEL: frame_pointer_none:200; CHECK-FAKE16: ; %bb.0:201; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)202; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13203; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33204; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0205; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS206; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0207; CHECK-FAKE16-NEXT: s_alloc_vgpr 0208; CHECK-FAKE16-NEXT: s_endpgm209 %local = alloca i32, addrspace(5)210 store volatile i8 13, ptr addrspace(5) %local211 ret void212}213 214define amdgpu_cs void @frame_pointer_all() #2 {215; CHECK-TRUE16-LABEL: frame_pointer_all:216; CHECK-TRUE16: ; %bb.0:217; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)218; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13219; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33220; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0221; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS222; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0223; CHECK-TRUE16-NEXT: s_alloc_vgpr 0224; CHECK-TRUE16-NEXT: s_endpgm225;226; CHECK-FAKE16-LABEL: frame_pointer_all:227; CHECK-FAKE16: ; %bb.0:228; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)229; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13230; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33231; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0232; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS233; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0234; CHECK-FAKE16-NEXT: s_alloc_vgpr 0235; CHECK-FAKE16-NEXT: s_endpgm236 %local = alloca i32, addrspace(5)237 store volatile i8 13, ptr addrspace(5) %local238 ret void239}240 241; Non-entry functions and graphics shaders don't need to worry about CWSR.242define amdgpu_gs void @amdgpu_gs() #0 {243; CHECK-TRUE16-LABEL: amdgpu_gs:244; CHECK-TRUE16: ; %bb.0:245; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15246; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi247; CHECK-TRUE16-NEXT: s_mov_b32 s0, callee@abs32@lo248; CHECK-TRUE16-NEXT: s_mov_b32 s32, 16249; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, off scope:SCOPE_SYS250; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0251; CHECK-TRUE16-NEXT: v_mov_b32_e32 v0, 0x47252; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]253; CHECK-TRUE16-NEXT: s_alloc_vgpr 0254; CHECK-TRUE16-NEXT: s_endpgm255;256; CHECK-FAKE16-LABEL: amdgpu_gs:257; CHECK-FAKE16: ; %bb.0:258; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15259; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi260; CHECK-FAKE16-NEXT: s_mov_b32 s0, callee@abs32@lo261; CHECK-FAKE16-NEXT: s_mov_b32 s32, 16262; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, off scope:SCOPE_SYS263; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0264; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 0x47265; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]266; CHECK-FAKE16-NEXT: s_alloc_vgpr 0267; CHECK-FAKE16-NEXT: s_endpgm268 %local = alloca i32, addrspace(5)269 store volatile i8 15, ptr addrspace(5) %local270 call amdgpu_gfx void @callee(i32 71)271 ret void272}273 274define amdgpu_gfx void @amdgpu_gfx() #0 {275; CHECK-TRUE16-LABEL: amdgpu_gfx:276; CHECK-TRUE16: ; %bb.0:277; CHECK-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0278; CHECK-TRUE16-NEXT: s_wait_expcnt 0x0279; CHECK-TRUE16-NEXT: s_wait_samplecnt 0x0280; CHECK-TRUE16-NEXT: s_wait_bvhcnt 0x0281; CHECK-TRUE16-NEXT: s_wait_kmcnt 0x0282; CHECK-TRUE16-NEXT: s_mov_b32 s0, s33283; CHECK-TRUE16-NEXT: s_mov_b32 s33, s32284; CHECK-TRUE16-NEXT: s_or_saveexec_b32 s1, -1285; CHECK-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill286; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)287; CHECK-TRUE16-NEXT: s_mov_b32 exec_lo, s1288; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s0, 2289; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15290; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi291; CHECK-TRUE16-NEXT: s_mov_b32 s0, callee@abs32@lo292; CHECK-TRUE16-NEXT: s_add_co_i32 s32, s32, 16293; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s30, 0294; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0295; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS296; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0297; CHECK-TRUE16-NEXT: v_mov_b32_e32 v0, 0x47298; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s31, 1299; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)300; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]301; CHECK-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)302; CHECK-TRUE16-NEXT: v_readlane_b32 s31, v40, 1303; CHECK-TRUE16-NEXT: v_readlane_b32 s30, v40, 0304; CHECK-TRUE16-NEXT: s_mov_b32 s32, s33305; CHECK-TRUE16-NEXT: v_readlane_b32 s0, v40, 2306; CHECK-TRUE16-NEXT: s_or_saveexec_b32 s1, -1307; CHECK-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload308; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)309; CHECK-TRUE16-NEXT: s_mov_b32 exec_lo, s1310; CHECK-TRUE16-NEXT: s_mov_b32 s33, s0311; CHECK-TRUE16-NEXT: s_wait_loadcnt 0x0312; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)313; CHECK-TRUE16-NEXT: s_setpc_b64 s[30:31]314;315; CHECK-FAKE16-LABEL: amdgpu_gfx:316; CHECK-FAKE16: ; %bb.0:317; CHECK-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0318; CHECK-FAKE16-NEXT: s_wait_expcnt 0x0319; CHECK-FAKE16-NEXT: s_wait_samplecnt 0x0320; CHECK-FAKE16-NEXT: s_wait_bvhcnt 0x0321; CHECK-FAKE16-NEXT: s_wait_kmcnt 0x0322; CHECK-FAKE16-NEXT: s_mov_b32 s0, s33323; CHECK-FAKE16-NEXT: s_mov_b32 s33, s32324; CHECK-FAKE16-NEXT: s_or_saveexec_b32 s1, -1325; CHECK-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill326; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)327; CHECK-FAKE16-NEXT: s_mov_b32 exec_lo, s1328; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s0, 2329; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15330; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi331; CHECK-FAKE16-NEXT: s_mov_b32 s0, callee@abs32@lo332; CHECK-FAKE16-NEXT: s_add_co_i32 s32, s32, 16333; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s30, 0334; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0335; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS336; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0337; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 0x47338; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s31, 1339; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)340; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]341; CHECK-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)342; CHECK-FAKE16-NEXT: v_readlane_b32 s31, v40, 1343; CHECK-FAKE16-NEXT: v_readlane_b32 s30, v40, 0344; CHECK-FAKE16-NEXT: s_mov_b32 s32, s33345; CHECK-FAKE16-NEXT: v_readlane_b32 s0, v40, 2346; CHECK-FAKE16-NEXT: s_or_saveexec_b32 s1, -1347; CHECK-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload348; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)349; CHECK-FAKE16-NEXT: s_mov_b32 exec_lo, s1350; CHECK-FAKE16-NEXT: s_mov_b32 s33, s0351; CHECK-FAKE16-NEXT: s_wait_loadcnt 0x0352; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)353; CHECK-FAKE16-NEXT: s_setpc_b64 s[30:31]354 %local = alloca i32, addrspace(5)355 store volatile i8 15, ptr addrspace(5) %local356 call amdgpu_gfx void @callee(i32 71)357 ret void358}359 360define void @default() #0 {361; CHECK-LABEL: default:362; CHECK: ; %bb.0:363; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0364; CHECK-NEXT: s_wait_expcnt 0x0365; CHECK-NEXT: s_wait_samplecnt 0x0366; CHECK-NEXT: s_wait_bvhcnt 0x0367; CHECK-NEXT: s_wait_kmcnt 0x0368; CHECK-NEXT: s_setpc_b64 s[30:31]369 ret void370}371 372declare amdgpu_gfx void @callee(i32) #0373 374attributes #0 = { nounwind "amdgpu-dynamic-vgpr-block-size"="16" }375attributes #1 = { nounwind "frame-pointer"="none" "amdgpu-dynamic-vgpr-block-size"="16" }376attributes #2 = { nounwind "frame-pointer"="all" "amdgpu-dynamic-vgpr-block-size"="16" }377