113 lines · plain
1; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefixes=GCN,SI %s2; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GCNX3 %s3 4; FIXME: Most of these cases that don't trigger because of broken cost5; heuristics. Should not need -stress-early-ifcvt6 7; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64:8; GCN: buffer_load_dwordx2 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]9; GCN: v_cmp_neq_f64_e32 vcc, 1.0, v[[[VAL_LO]]:[[VAL_HI]]]10; GCN: v_add_f64 v[[[ADD_LO:[0-9]+]]:[[ADD_HI:[0-9]+]]], v[[[VAL_LO]]:[[VAL_HI]]], v[[[VAL_LO]]:[[VAL_HI]]]11; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc12; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc13; GCN: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]14define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {15entry:16 %v = load double, ptr addrspace(1) %in17 %cc = fcmp oeq double %v, 1.000000e+0018 br i1 %cc, label %if, label %endif19 20if:21 %u = fadd double %v, %v22 br label %endif23 24endif:25 %r = phi double [ %v, %entry ], [ %u, %if ]26 store double %r, ptr addrspace(1) %out27 ret void28}29 30; vcc branch with SGPR inputs31; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle64:32; GCN: v_cmp_neq_f6433; GCN: v_add_f6434; GCN: v_cndmask_b32_e3235; GCN: v_cndmask_b32_e3236define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {37entry:38 %v = load double, ptr addrspace(4) %in39 %cc = fcmp oeq double %v, 1.000000e+0040 br i1 %cc, label %if, label %endif41 42if:43 %u = fadd double %v, %v44 br label %endif45 46endif:47 %r = phi double [ %v, %entry ], [ %u, %if ]48 store double %r, ptr addrspace(1) %out49 ret void50}51 52; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle96:53; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.054 55; GCN: v_add_i32_e3256; GCN: v_add_i32_e3257; GCN: v_add_i32_e3258; GCN: s_mov_b64 vcc, [[CMP]]59 60; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc61; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc62; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc63 64; SI-DAG: buffer_store_dwordx265; SI-DAG: buffer_store_dword v66; GCNX3: buffer_store_dwordx367define amdgpu_kernel void @test_vccnz_ifcvt_triangle96(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cnd) #0 {68entry:69 %v = load <3 x i32>, ptr addrspace(1) %in70 %cc = fcmp oeq float %cnd, 1.000000e+0071 br i1 %cc, label %if, label %endif72 73if:74 %u = add <3 x i32> %v, %v75 br label %endif76 77endif:78 %r = phi <3 x i32> [ %v, %entry ], [ %u, %if ]79 store <3 x i32> %r, ptr addrspace(1) %out80 ret void81}82 83; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle128:84; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.085 86; GCN: v_add_i32_e3287; GCN: v_add_i32_e3288; GCN: v_add_i32_e3289; GCN: v_add_i32_e3290; GCN: s_mov_b64 vcc, [[CMP]]91 92; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc93; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc94; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc95; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc96 97; GCN: buffer_store_dwordx498define amdgpu_kernel void @test_vccnz_ifcvt_triangle128(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cnd) #0 {99entry:100 %v = load <4 x i32>, ptr addrspace(1) %in101 %cc = fcmp oeq float %cnd, 1.000000e+00102 br i1 %cc, label %if, label %endif103 104if:105 %u = add <4 x i32> %v, %v106 br label %endif107 108endif:109 %r = phi <4 x i32> [ %v, %entry ], [ %u, %if ]110 store <4 x i32> %r, ptr addrspace(1) %out111 ret void112}113