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1; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-FMF,GCN-SAFE %s2 3declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone4 5; Test that the -enable-no-signed-zeros-fp-math flag works6 7; GCN-LABEL: {{^}}fneg_fsub_f32_fmf:8; GCN: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}9; GCN-FMF-NOT: xor10define amdgpu_kernel void @fneg_fsub_f32_fmf(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {11 %tid = call i32 @llvm.amdgcn.workitem.id.x()12 %add = add i32 %tid, 113 %gep = getelementptr float, ptr addrspace(1) %in, i32 %tid14 %b_ptr = getelementptr float, ptr addrspace(1) %in, i32 %add15 %a = load float, ptr addrspace(1) %gep, align 416 %b = load float, ptr addrspace(1) %b_ptr, align 417 %result = fsub fast float %a, %b18 %neg.result = fsub fast float -0.0, %result19 store float %neg.result, ptr addrspace(1) %out, align 420 ret void21}22 23; GCN-LABEL: {{^}}fneg_fsub_f32_safe:24; GCN: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}25; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]]26define amdgpu_kernel void @fneg_fsub_f32_safe(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {27 %tid = call i32 @llvm.amdgcn.workitem.id.x()28 %add = add i32 %tid, 129 %gep = getelementptr float, ptr addrspace(1) %in, i32 %tid30 %b_ptr = getelementptr float, ptr addrspace(1) %in, i32 %add31 %a = load float, ptr addrspace(1) %gep, align 432 %b = load float, ptr addrspace(1) %b_ptr, align 433 %result = fsub float %a, %b34 %neg.result = fsub float -0.0, %result35 store float %neg.result, ptr addrspace(1) %out, align 436 ret void37}38 39attributes #0 = { nounwind }40