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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s6 7define i32 @s_add_co_select_user() {8; GFX7-LABEL: s_add_co_select_user:9; GFX7: ; %bb.0: ; %bb10; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX7-NEXT: s_mov_b64 s[4:5], 012; GFX7-NEXT: s_load_dword s6, s[4:5], 0x013; GFX7-NEXT: s_waitcnt lgkmcnt(0)14; GFX7-NEXT: s_add_u32 s7, s6, s615; GFX7-NEXT: s_addc_u32 s8, s6, 016; GFX7-NEXT: s_cselect_b64 s[4:5], -1, 017; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec18; GFX7-NEXT: s_cselect_b32 s4, s8, 019; GFX7-NEXT: s_cmp_gt_u32 s6, 3120; GFX7-NEXT: s_cselect_b32 s4, s7, s421; GFX7-NEXT: v_mov_b32_e32 v0, s422; GFX7-NEXT: s_setpc_b64 s[30:31]23;24; GFX9-LABEL: s_add_co_select_user:25; GFX9: ; %bb.0: ; %bb26; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; GFX9-NEXT: s_mov_b64 s[4:5], 028; GFX9-NEXT: s_load_dword s6, s[4:5], 0x029; GFX9-NEXT: s_waitcnt lgkmcnt(0)30; GFX9-NEXT: s_add_u32 s7, s6, s631; GFX9-NEXT: s_addc_u32 s8, s6, 032; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 033; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec34; GFX9-NEXT: s_cselect_b32 s4, s8, 035; GFX9-NEXT: s_cmp_gt_u32 s6, 3136; GFX9-NEXT: s_cselect_b32 s4, s7, s437; GFX9-NEXT: v_mov_b32_e32 v0, s438; GFX9-NEXT: s_setpc_b64 s[30:31]39;40; GFX10-LABEL: s_add_co_select_user:41; GFX10: ; %bb.0: ; %bb42; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)43; GFX10-NEXT: s_mov_b64 s[4:5], 044; GFX10-NEXT: s_load_dword s4, s[4:5], 0x045; GFX10-NEXT: s_waitcnt lgkmcnt(0)46; GFX10-NEXT: s_add_u32 s5, s4, s447; GFX10-NEXT: s_addc_u32 s6, s4, 048; GFX10-NEXT: s_cselect_b32 s7, -1, 049; GFX10-NEXT: s_and_b32 s7, s7, exec_lo50; GFX10-NEXT: s_cselect_b32 s6, s6, 051; GFX10-NEXT: s_cmp_gt_u32 s4, 3152; GFX10-NEXT: s_cselect_b32 s4, s5, s653; GFX10-NEXT: v_mov_b32_e32 v0, s454; GFX10-NEXT: s_setpc_b64 s[30:31]55;56; GFX11-LABEL: s_add_co_select_user:57; GFX11: ; %bb.0: ; %bb58; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)59; GFX11-NEXT: s_mov_b64 s[0:1], 060; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x061; GFX11-NEXT: s_waitcnt lgkmcnt(0)62; GFX11-NEXT: s_add_u32 s1, s0, s063; GFX11-NEXT: s_addc_u32 s2, s0, 064; GFX11-NEXT: s_cselect_b32 s3, -1, 065; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)66; GFX11-NEXT: s_and_b32 s3, s3, exec_lo67; GFX11-NEXT: s_cselect_b32 s2, s2, 068; GFX11-NEXT: s_cmp_gt_u32 s0, 3169; GFX11-NEXT: s_cselect_b32 s0, s1, s270; GFX11-NEXT: v_mov_b32_e32 v0, s071; GFX11-NEXT: s_setpc_b64 s[30:31]72bb:73 %i = load volatile i32, ptr addrspace(4) null, align 874 %i1 = add i32 %i, %i75 %i2 = icmp ult i32 %i1, %i76 %i3 = zext i1 %i2 to i3277 %i4 = add nuw nsw i32 %i3, 078 %i5 = add i32 %i4, %i79 %i6 = icmp ult i32 %i5, %i480 %i7 = select i1 %i6, i32 %i5, i32 081 %i8 = icmp ugt i32 %i, 3182 %i9 = select i1 %i8, i32 %i1, i32 %i783 ret i32 %i984}85 86define amdgpu_kernel void @s_add_co_br_user(i32 %i) {87; GFX7-LABEL: s_add_co_br_user:88; GFX7: ; %bb.0: ; %bb89; GFX7-NEXT: s_load_dword s0, s[8:9], 0x090; GFX7-NEXT: s_add_i32 s12, s12, s1791; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 892; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s1393; GFX7-NEXT: s_waitcnt lgkmcnt(0)94; GFX7-NEXT: s_add_u32 s1, s0, s095; GFX7-NEXT: s_addc_u32 s0, s0, 096; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 097; GFX7-NEXT: s_andn2_b64 vcc, exec, s[0:1]98; GFX7-NEXT: s_cbranch_vccnz .LBB1_299; GFX7-NEXT: ; %bb.1: ; %bb0100; GFX7-NEXT: v_mov_b32_e32 v0, 0101; GFX7-NEXT: v_mov_b32_e32 v1, 0102; GFX7-NEXT: v_mov_b32_e32 v2, 9103; GFX7-NEXT: flat_store_dword v[0:1], v2104; GFX7-NEXT: s_waitcnt vmcnt(0)105; GFX7-NEXT: .LBB1_2: ; %bb1106; GFX7-NEXT: v_mov_b32_e32 v0, 0107; GFX7-NEXT: v_mov_b32_e32 v1, 0108; GFX7-NEXT: v_mov_b32_e32 v2, 10109; GFX7-NEXT: flat_store_dword v[0:1], v2110; GFX7-NEXT: s_waitcnt vmcnt(0)111; GFX7-NEXT: s_endpgm112;113; GFX9-LABEL: s_add_co_br_user:114; GFX9: ; %bb.0: ; %bb115; GFX9-NEXT: s_load_dword s0, s[8:9], 0x0116; GFX9-NEXT: s_waitcnt lgkmcnt(0)117; GFX9-NEXT: s_add_u32 s1, s0, s0118; GFX9-NEXT: s_addc_u32 s0, s0, 0119; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0120; GFX9-NEXT: s_andn2_b64 vcc, exec, s[0:1]121; GFX9-NEXT: s_cbranch_vccnz .LBB1_2122; GFX9-NEXT: ; %bb.1: ; %bb0123; GFX9-NEXT: v_mov_b32_e32 v0, 0124; GFX9-NEXT: v_mov_b32_e32 v1, 0125; GFX9-NEXT: v_mov_b32_e32 v2, 9126; GFX9-NEXT: global_store_dword v[0:1], v2, off127; GFX9-NEXT: s_waitcnt vmcnt(0)128; GFX9-NEXT: .LBB1_2: ; %bb1129; GFX9-NEXT: v_mov_b32_e32 v0, 0130; GFX9-NEXT: v_mov_b32_e32 v1, 0131; GFX9-NEXT: v_mov_b32_e32 v2, 10132; GFX9-NEXT: global_store_dword v[0:1], v2, off133; GFX9-NEXT: s_waitcnt vmcnt(0)134; GFX9-NEXT: s_endpgm135;136; GFX10-LABEL: s_add_co_br_user:137; GFX10: ; %bb.0: ; %bb138; GFX10-NEXT: s_load_dword s0, s[8:9], 0x0139; GFX10-NEXT: s_waitcnt lgkmcnt(0)140; GFX10-NEXT: s_add_u32 s1, s0, s0141; GFX10-NEXT: s_addc_u32 s0, s0, 0142; GFX10-NEXT: s_cselect_b32 s0, -1, 0143; GFX10-NEXT: s_andn2_b32 vcc_lo, exec_lo, s0144; GFX10-NEXT: s_cbranch_vccnz .LBB1_2145; GFX10-NEXT: ; %bb.1: ; %bb0146; GFX10-NEXT: v_mov_b32_e32 v0, 0147; GFX10-NEXT: v_mov_b32_e32 v1, 0148; GFX10-NEXT: v_mov_b32_e32 v2, 9149; GFX10-NEXT: global_store_dword v[0:1], v2, off150; GFX10-NEXT: s_waitcnt_vscnt null, 0x0151; GFX10-NEXT: .LBB1_2: ; %bb1152; GFX10-NEXT: v_mov_b32_e32 v0, 0153; GFX10-NEXT: v_mov_b32_e32 v1, 0154; GFX10-NEXT: v_mov_b32_e32 v2, 10155; GFX10-NEXT: global_store_dword v[0:1], v2, off156; GFX10-NEXT: s_waitcnt_vscnt null, 0x0157; GFX10-NEXT: s_endpgm158;159; GFX11-LABEL: s_add_co_br_user:160; GFX11: ; %bb.0: ; %bb161; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0162; GFX11-NEXT: s_waitcnt lgkmcnt(0)163; GFX11-NEXT: s_add_u32 s1, s0, s0164; GFX11-NEXT: s_addc_u32 s0, s0, 0165; GFX11-NEXT: s_cselect_b32 s0, -1, 0166; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)167; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0168; GFX11-NEXT: s_cbranch_vccnz .LBB1_2169; GFX11-NEXT: ; %bb.1: ; %bb0170; GFX11-NEXT: v_mov_b32_e32 v0, 0171; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 9172; GFX11-NEXT: global_store_b32 v[0:1], v2, off dlc173; GFX11-NEXT: s_waitcnt_vscnt null, 0x0174; GFX11-NEXT: .LBB1_2: ; %bb1175; GFX11-NEXT: v_mov_b32_e32 v0, 0176; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 10177; GFX11-NEXT: global_store_b32 v[0:1], v2, off dlc178; GFX11-NEXT: s_waitcnt_vscnt null, 0x0179; GFX11-NEXT: s_endpgm180bb:181 %i1 = add i32 %i, %i182 %i2 = icmp ult i32 %i1, %i183 %i3 = zext i1 %i2 to i32184 %i4 = add nuw nsw i32 %i3, 0185 %i5 = add i32 %i4, %i186 %i6 = icmp ult i32 %i5, %i4187 %i7 = select i1 %i6, i32 %i5, i32 0188 br i1 %i6, label %bb0, label %bb1189 190bb0:191 store volatile i32 9, ptr addrspace(1) null192 br label %bb1193 194bb1:195 store volatile i32 10, ptr addrspace(1) null196 ret void197}198