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1; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=GCN2 3; GCN-LABEL: and_zext:4; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}5; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]6define amdgpu_kernel void @and_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {7 %id = call i32 @llvm.amdgcn.workitem.id.x() #18 %ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id9 %a = load i16, ptr addrspace(1) %in10 %b = load i16, ptr addrspace(1) %ptr11 %c = add i16 %a, %b12 %val16 = and i16 %c, %a13 %val32 = zext i16 %val16 to i3214 store i32 %val32, ptr addrspace(1) %out15 ret void16}17 18; GCN-LABEL: or_zext:19; GCN: v_or_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}20; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]21define amdgpu_kernel void @or_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {22 %id = call i32 @llvm.amdgcn.workitem.id.x() #123 %ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id24 %a = load i16, ptr addrspace(1) %in25 %b = load i16, ptr addrspace(1) %ptr26 %c = add i16 %a, %b27 %val16 = or i16 %c, %a28 %val32 = zext i16 %val16 to i3229 store i32 %val32, ptr addrspace(1) %out30 ret void31}32 33; GCN-LABEL: xor_zext:34; GCN: v_xor_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}35; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]36define amdgpu_kernel void @xor_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {37 %id = call i32 @llvm.amdgcn.workitem.id.x() #138 %ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id39 %a = load i16, ptr addrspace(1) %in40 %b = load i16, ptr addrspace(1) %ptr41 %c = add i16 %a, %b42 %val16 = xor i16 %c, %a43 %val32 = zext i16 %val16 to i3244 store i32 %val32, ptr addrspace(1) %out45 ret void46}47 48declare i32 @llvm.amdgcn.workitem.id.x() #149 50attributes #1 = { nounwind readnone }51