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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s3 4# Initially %2 starts out with 2 subranges (one for sub0, and one for5# the rest of the lanes). After %2 is split, after refineSubRanges the6# newly created register has a different set of lane masks since the7# copy bundle uses 2 different defs to cover the register. This was8# fixed by doing refineSubRanges after all the COPYs being inserted.9 10---11name: subrange_for_this_mask_not_found12tracksRegLiveness: true13machineFunctionInfo:14 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'15 stackPtrOffsetReg: '$sgpr32'16 occupancy: 717body: |18 ; CHECK-LABEL: name: subrange_for_this_mask_not_found19 ; CHECK: bb.0:20 ; CHECK-NEXT: successors: %bb.1(0x80000000)21 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF23 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF24 ; CHECK-NEXT: [[COPY:%[0-9]+]]:av_1024_align2 = COPY [[DEF1]]25 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: bb.1:27 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)28 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF30 ; CHECK-NEXT: S_NOP 0, implicit [[DEF1]]31 ; CHECK-NEXT: S_NOP 0, implicit [[DEF1]]32 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF33 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc34 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: bb.2:36 ; CHECK-NEXT: successors: %bb.3(0x80000000)37 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024_align2 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {39 ; CHECK-NEXT: internal [[COPY1]].sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16:av_1024_align2 = COPY [[COPY]].sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi1640 ; CHECK-NEXT: internal [[COPY1]].sub29_sub30_sub31:av_1024_align2 = COPY [[COPY]].sub29_sub30_sub3141 ; CHECK-NEXT: }42 ; CHECK-NEXT: [[COPY1:%[0-9]+]].sub0:av_1024_align2 = IMPLICIT_DEF43 ; CHECK-NEXT: S_NOP 0, implicit [[COPY1]].sub044 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: bb.3:46 ; CHECK-NEXT: successors: %bb.4(0x80000000)47 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]49 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: bb.4:51 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)52 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF54 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc55 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: bb.5:57 ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:vreg_1024_align2 = COPY [[DEF]]58 ; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]59 bb.0:60 %0:vgpr_32 = IMPLICIT_DEF61 %1:vreg_1024_align2 = IMPLICIT_DEF62 %2:vreg_1024_align2 = COPY %163 64 bb.1:65 %5:vreg_64 = IMPLICIT_DEF66 S_NOP 0, implicit %167 S_NOP 0, implicit %168 %1:vreg_1024_align2 = IMPLICIT_DEF69 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc70 71 bb.3:72 %2.sub0:vreg_1024_align2 = IMPLICIT_DEF73 S_NOP 0, implicit %2.sub074 75 bb.4:76 S_NOP 0, implicit %277 78 bb.5:79 %2:vreg_1024_align2 = IMPLICIT_DEF80 S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc81 82 bb.6:83 undef %4.sub0:vreg_1024_align2 = COPY %084 S_NOP 0, implicit %485...86