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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- -o - %s | FileCheck -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s6 7define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i32 inreg %cond.arg) {8; SI-LABEL: vec_8xi16_extract_4xi16:9; SI:       ; %bb.0:10; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; SI-NEXT:    s_cmp_lg_u32 s16, 012; SI-NEXT:    s_mov_b32 s6, 013; SI-NEXT:    s_cbranch_scc0 .LBB0_414; SI-NEXT:  ; %bb.1: ; %F15; SI-NEXT:    s_mov_b32 s7, 0xf00016; SI-NEXT:    s_mov_b32 s4, s617; SI-NEXT:    s_mov_b32 s5, s618; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[4:7], 0 addr64 glc19; SI-NEXT:    s_waitcnt vmcnt(0)20; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:2 glc21; SI-NEXT:    s_waitcnt vmcnt(0)22; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[4:7], 0 addr64 offset:4 glc23; SI-NEXT:    s_waitcnt vmcnt(0)24; SI-NEXT:    buffer_load_ushort v7, v[2:3], s[4:7], 0 addr64 offset:6 glc25; SI-NEXT:    s_waitcnt vmcnt(0)26; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:8 glc27; SI-NEXT:    s_waitcnt vmcnt(0)28; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:10 glc29; SI-NEXT:    s_waitcnt vmcnt(0)30; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:12 glc31; SI-NEXT:    s_waitcnt vmcnt(0)32; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:14 glc33; SI-NEXT:    s_waitcnt vmcnt(0)34; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v735; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v436; SI-NEXT:    v_or_b32_e32 v2, v6, v237; SI-NEXT:    v_or_b32_e32 v3, v5, v338; SI-NEXT:    s_mov_b64 vcc, exec39; SI-NEXT:    s_cbranch_execnz .LBB0_340; SI-NEXT:  .LBB0_2: ; %T41; SI-NEXT:    s_mov_b32 s7, 0xf00042; SI-NEXT:    s_mov_b32 s4, s643; SI-NEXT:    s_mov_b32 s5, s644; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 glc45; SI-NEXT:    s_waitcnt vmcnt(0)46; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:2 glc47; SI-NEXT:    s_waitcnt vmcnt(0)48; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:4 glc49; SI-NEXT:    s_waitcnt vmcnt(0)50; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:6 glc51; SI-NEXT:    s_waitcnt vmcnt(0)52; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:8 glc53; SI-NEXT:    s_waitcnt vmcnt(0)54; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:10 glc55; SI-NEXT:    s_waitcnt vmcnt(0)56; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:12 glc57; SI-NEXT:    s_waitcnt vmcnt(0)58; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:14 glc59; SI-NEXT:    s_waitcnt vmcnt(0)60; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v561; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v462; SI-NEXT:    v_or_b32_e32 v2, v2, v063; SI-NEXT:    v_or_b32_e32 v3, v3, v164; SI-NEXT:  .LBB0_3: ; %exit65; SI-NEXT:    v_bfe_i32 v0, v3, 0, 1666; SI-NEXT:    v_bfe_i32 v1, v4, 0, 1667; SI-NEXT:    v_bfe_i32 v2, v2, 0, 1668; SI-NEXT:    v_mov_b32_e32 v3, 0xffff69; SI-NEXT:    v_mov_b32_e32 v4, 0x800070; SI-NEXT:    v_mov_b32_e32 v5, 0xffff000071; SI-NEXT:    v_bfrev_b32_e32 v6, 172; SI-NEXT:    v_mov_b32_e32 v7, 0xffff800073; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v074; SI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc75; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v176; SI-NEXT:    v_cndmask_b32_e32 v1, v5, v6, vcc77; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v278; SI-NEXT:    v_cndmask_b32_e32 v2, -1, v7, vcc79; SI-NEXT:    v_or_b32_e32 v0, v0, v180; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v281; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v282; SI-NEXT:    v_or_b32_e32 v2, v3, v483; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 1684; SI-NEXT:    s_setpc_b64 s[30:31]85; SI-NEXT:  .LBB0_4:86; SI-NEXT:    ; implicit-def: $vgpr387; SI-NEXT:    ; implicit-def: $vgpr488; SI-NEXT:    ; implicit-def: $vgpr289; SI-NEXT:    s_mov_b64 vcc, 090; SI-NEXT:    s_branch .LBB0_291;92; GFX9-LABEL: vec_8xi16_extract_4xi16:93; GFX9:       ; %bb.0:94; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; GFX9-NEXT:    s_cmp_lg_u32 s16, 096; GFX9-NEXT:    s_cbranch_scc0 .LBB0_497; GFX9-NEXT:  ; %bb.1: ; %F98; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[2:3], off glc99; GFX9-NEXT:    s_waitcnt vmcnt(0)100; GFX9-NEXT:    s_cbranch_execnz .LBB0_3101; GFX9-NEXT:  .LBB0_2: ; %T102; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off glc103; GFX9-NEXT:    s_waitcnt vmcnt(0)104; GFX9-NEXT:  .LBB0_3: ; %exit105; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v3 op_sel_hi:[0,0]106; GFX9-NEXT:    s_movk_i32 s4, 0x8000107; GFX9-NEXT:    v_or_b32_e32 v1, 0xffff8000, v0108; GFX9-NEXT:    v_or_b32_sdwa v3, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD109; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]110; GFX9-NEXT:    v_or_b32_e32 v2, 0xffff8000, v0111; GFX9-NEXT:    v_or_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD112; GFX9-NEXT:    s_mov_b32 s4, 0x5040100113; GFX9-NEXT:    v_perm_b32 v0, v0, v2, s4114; GFX9-NEXT:    v_perm_b32 v1, v3, v1, s4115; GFX9-NEXT:    s_setpc_b64 s[30:31]116; GFX9-NEXT:  .LBB0_4:117; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5118; GFX9-NEXT:    s_branch .LBB0_2119;120; GFX11-TRUE16-LABEL: vec_8xi16_extract_4xi16:121; GFX11-TRUE16:       ; %bb.0:122; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)123; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0124; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0125; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB0_4126; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F127; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc128; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)129; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0130; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB0_3131; GFX11-TRUE16-NEXT:  .LBB0_2: ; %T132; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc133; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)134; GFX11-TRUE16-NEXT:  .LBB0_3: ; %exit135; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]136; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]137; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)138; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l139; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l140; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)141; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h142; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h143; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]144; GFX11-TRUE16-NEXT:  .LBB0_4:145; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5146; GFX11-TRUE16-NEXT:    s_branch .LBB0_2147;148; GFX11-FAKE16-LABEL: vec_8xi16_extract_4xi16:149; GFX11-FAKE16:       ; %bb.0:150; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0152; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0153; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB0_4154; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F155; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc156; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)157; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0158; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB0_3159; GFX11-FAKE16-NEXT:  .LBB0_2: ; %T160; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc161; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)162; GFX11-FAKE16-NEXT:  .LBB0_3: ; %exit163; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]164; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]165; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)166; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0167; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1168; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1169; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0170; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)171; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2172; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3173; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)174; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100175; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100176; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]177; GFX11-FAKE16-NEXT:  .LBB0_4:178; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5179; GFX11-FAKE16-NEXT:    s_branch .LBB0_2180  %cond = icmp eq i32 %cond.arg, 0181  br i1 %cond, label %T, label %F182 183T:184  %t = load volatile <8 x i16>, ptr addrspace(1) %p0185  br label %exit186 187F:188  %f = load volatile <8 x i16>, ptr addrspace(1) %p1189  br label %exit190 191exit:192  %m = phi <8 x i16> [ %t, %T ], [ %f, %F ]193  %v2 = shufflevector <8 x i16> %m, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>194  %b2 = icmp sgt <4 x i16> %v2, <i16 -1, i16 -1, i16 -1, i16 -1>195  %r2 = select <4 x i1> %b2, <4 x i16> <i16 -32768, i16 -32768, i16 -32768, i16 -32768>, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>196  ret <4 x i16> %r2197}198 199define <4 x i16> @vec_8xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i32 inreg %cond.arg) {200; SI-LABEL: vec_8xi16_extract_4xi16_2:201; SI:       ; %bb.0:202; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)203; SI-NEXT:    s_cmp_lg_u32 s16, 0204; SI-NEXT:    s_mov_b32 s6, 0205; SI-NEXT:    s_cbranch_scc0 .LBB1_4206; SI-NEXT:  ; %bb.1: ; %F207; SI-NEXT:    s_mov_b32 s7, 0xf000208; SI-NEXT:    s_mov_b32 s4, s6209; SI-NEXT:    s_mov_b32 s5, s6210; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc211; SI-NEXT:    s_waitcnt vmcnt(0)212; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:2 glc213; SI-NEXT:    s_waitcnt vmcnt(0)214; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:4 glc215; SI-NEXT:    s_waitcnt vmcnt(0)216; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:6 glc217; SI-NEXT:    s_waitcnt vmcnt(0)218; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[4:7], 0 addr64 offset:8 glc219; SI-NEXT:    s_waitcnt vmcnt(0)220; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:10 glc221; SI-NEXT:    s_waitcnt vmcnt(0)222; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[4:7], 0 addr64 offset:12 glc223; SI-NEXT:    s_waitcnt vmcnt(0)224; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:14 glc225; SI-NEXT:    s_waitcnt vmcnt(0)226; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v2227; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v4228; SI-NEXT:    v_or_b32_e32 v3, v6, v3229; SI-NEXT:    v_or_b32_e32 v5, v5, v7230; SI-NEXT:    s_mov_b64 vcc, exec231; SI-NEXT:    s_cbranch_execnz .LBB1_3232; SI-NEXT:  .LBB1_2: ; %T233; SI-NEXT:    s_mov_b32 s7, 0xf000234; SI-NEXT:    s_mov_b32 s4, s6235; SI-NEXT:    s_mov_b32 s5, s6236; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc237; SI-NEXT:    s_waitcnt vmcnt(0)238; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:2 glc239; SI-NEXT:    s_waitcnt vmcnt(0)240; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:4 glc241; SI-NEXT:    s_waitcnt vmcnt(0)242; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:6 glc243; SI-NEXT:    s_waitcnt vmcnt(0)244; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:8 glc245; SI-NEXT:    s_waitcnt vmcnt(0)246; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:10 glc247; SI-NEXT:    s_waitcnt vmcnt(0)248; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 offset:12 glc249; SI-NEXT:    s_waitcnt vmcnt(0)250; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:14 glc251; SI-NEXT:    s_waitcnt vmcnt(0)252; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v2253; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v4254; SI-NEXT:    v_or_b32_e32 v3, v3, v0255; SI-NEXT:    v_or_b32_e32 v5, v5, v1256; SI-NEXT:  .LBB1_3: ; %exit257; SI-NEXT:    v_bfe_i32 v0, v5, 0, 16258; SI-NEXT:    v_bfe_i32 v1, v4, 0, 16259; SI-NEXT:    v_bfe_i32 v3, v3, 0, 16260; SI-NEXT:    v_bfe_i32 v2, v2, 0, 16261; SI-NEXT:    v_mov_b32_e32 v4, 0xffff262; SI-NEXT:    v_mov_b32_e32 v5, 0x8000263; SI-NEXT:    v_mov_b32_e32 v6, 0xffff0000264; SI-NEXT:    v_bfrev_b32_e32 v7, 1265; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v0266; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc267; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v1268; SI-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc269; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v3270; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc271; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v2272; SI-NEXT:    v_cndmask_b32_e32 v4, v6, v7, vcc273; SI-NEXT:    v_or_b32_e32 v0, v0, v1274; SI-NEXT:    v_or_b32_e32 v2, v3, v4275; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 16276; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v4277; SI-NEXT:    s_setpc_b64 s[30:31]278; SI-NEXT:  .LBB1_4:279; SI-NEXT:    ; implicit-def: $vgpr5280; SI-NEXT:    ; implicit-def: $vgpr4281; SI-NEXT:    ; implicit-def: $vgpr3282; SI-NEXT:    ; implicit-def: $vgpr2283; SI-NEXT:    s_mov_b64 vcc, 0284; SI-NEXT:    s_branch .LBB1_2285;286; GFX9-LABEL: vec_8xi16_extract_4xi16_2:287; GFX9:       ; %bb.0:288; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)289; GFX9-NEXT:    s_cmp_lg_u32 s16, 0290; GFX9-NEXT:    s_cbranch_scc0 .LBB1_4291; GFX9-NEXT:  ; %bb.1: ; %F292; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[2:3], off glc293; GFX9-NEXT:    s_waitcnt vmcnt(0)294; GFX9-NEXT:    s_cbranch_execnz .LBB1_3295; GFX9-NEXT:  .LBB1_2: ; %T296; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off glc297; GFX9-NEXT:    s_waitcnt vmcnt(0)298; GFX9-NEXT:  .LBB1_3: ; %exit299; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v5 op_sel_hi:[0,1]300; GFX9-NEXT:    s_movk_i32 s4, 0x8000301; GFX9-NEXT:    v_or_b32_e32 v1, 0xffff8000, v0302; GFX9-NEXT:    v_or_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD303; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]304; GFX9-NEXT:    v_or_b32_e32 v3, 0xffff8000, v0305; GFX9-NEXT:    v_or_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD306; GFX9-NEXT:    s_mov_b32 s4, 0x5040100307; GFX9-NEXT:    v_perm_b32 v0, v0, v3, s4308; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s4309; GFX9-NEXT:    s_setpc_b64 s[30:31]310; GFX9-NEXT:  .LBB1_4:311; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5312; GFX9-NEXT:    s_branch .LBB1_2313;314; GFX11-TRUE16-LABEL: vec_8xi16_extract_4xi16_2:315; GFX11-TRUE16:       ; %bb.0:316; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)317; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0318; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0319; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB1_4320; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F321; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc322; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)323; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0324; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB1_3325; GFX11-TRUE16-NEXT:  .LBB1_2: ; %T326; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc327; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)328; GFX11-TRUE16-NEXT:  .LBB1_3: ; %exit329; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]330; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]331; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)332; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l333; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l334; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)335; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h336; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h337; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]338; GFX11-TRUE16-NEXT:  .LBB1_4:339; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5340; GFX11-TRUE16-NEXT:    s_branch .LBB1_2341;342; GFX11-FAKE16-LABEL: vec_8xi16_extract_4xi16_2:343; GFX11-FAKE16:       ; %bb.0:344; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)345; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0346; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0347; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB1_4348; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F349; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc350; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)351; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0352; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB1_3353; GFX11-FAKE16-NEXT:  .LBB1_2: ; %T354; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc355; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)356; GFX11-FAKE16-NEXT:  .LBB1_3: ; %exit357; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]358; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]359; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)360; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0361; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1362; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1363; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0364; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)365; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2366; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3367; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)368; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100369; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100370; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]371; GFX11-FAKE16-NEXT:  .LBB1_4:372; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5373; GFX11-FAKE16-NEXT:    s_branch .LBB1_2374  %cond = icmp eq i32 %cond.arg, 0375  br i1 %cond, label %T, label %F376 377T:378  %t = load volatile <8 x i16>, ptr addrspace(1) %p0379  br label %exit380 381F:382  %f = load volatile <8 x i16>, ptr addrspace(1) %p1383  br label %exit384 385exit:386  %m = phi <8 x i16> [ %t, %T ], [ %f, %F ]387  %v2 = shufflevector <8 x i16> %m, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>388  %b2 = icmp sgt <4 x i16> %v2, <i16 -1, i16 -1, i16 -1, i16 -1>389  %r2 = select <4 x i1> %b2, <4 x i16> <i16 -32768, i16 -32768, i16 -32768, i16 -32768>, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>390  ret <4 x i16> %r2391}392 393define <4 x half> @vec_8xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i32 inreg %cond.arg) {394; SI-LABEL: vec_8xf16_extract_4xf16:395; SI:       ; %bb.0:396; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)397; SI-NEXT:    s_cmp_lg_u32 s16, 0398; SI-NEXT:    s_mov_b32 s6, 0399; SI-NEXT:    s_cbranch_scc0 .LBB2_4400; SI-NEXT:  ; %bb.1: ; %F401; SI-NEXT:    s_mov_b32 s7, 0xf000402; SI-NEXT:    s_mov_b32 s4, s6403; SI-NEXT:    s_mov_b32 s5, s6404; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc405; SI-NEXT:    s_waitcnt vmcnt(0)406; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[4:7], 0 addr64 offset:2 glc407; SI-NEXT:    s_waitcnt vmcnt(0)408; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[4:7], 0 addr64 offset:4 glc409; SI-NEXT:    s_waitcnt vmcnt(0)410; SI-NEXT:    buffer_load_ushort v7, v[2:3], s[4:7], 0 addr64 offset:6 glc411; SI-NEXT:    s_waitcnt vmcnt(0)412; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:8 glc413; SI-NEXT:    s_waitcnt vmcnt(0)414; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:10 glc415; SI-NEXT:    s_waitcnt vmcnt(0)416; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:12 glc417; SI-NEXT:    s_waitcnt vmcnt(0)418; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:14 glc419; SI-NEXT:    s_waitcnt vmcnt(0)420; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v7421; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v5422; SI-NEXT:    v_cvt_f32_f16_e32 v3, v5423; SI-NEXT:    v_or_b32_e32 v2, v6, v2424; SI-NEXT:    v_or_b32_e32 v4, v4, v7425; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2426; SI-NEXT:    v_cvt_f32_f16_e32 v4, v4427; SI-NEXT:    s_mov_b64 vcc, exec428; SI-NEXT:    s_cbranch_execnz .LBB2_3429; SI-NEXT:  .LBB2_2: ; %T430; SI-NEXT:    s_mov_b32 s7, 0xf000431; SI-NEXT:    s_mov_b32 s4, s6432; SI-NEXT:    s_mov_b32 s5, s6433; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc434; SI-NEXT:    s_waitcnt vmcnt(0)435; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 offset:2 glc436; SI-NEXT:    s_waitcnt vmcnt(0)437; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:4 glc438; SI-NEXT:    s_waitcnt vmcnt(0)439; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:6 glc440; SI-NEXT:    s_waitcnt vmcnt(0)441; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:8 glc442; SI-NEXT:    s_waitcnt vmcnt(0)443; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:10 glc444; SI-NEXT:    s_waitcnt vmcnt(0)445; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:12 glc446; SI-NEXT:    s_waitcnt vmcnt(0)447; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:14 glc448; SI-NEXT:    s_waitcnt vmcnt(0)449; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v5450; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v3451; SI-NEXT:    v_or_b32_e32 v0, v4, v0452; SI-NEXT:    v_or_b32_e32 v1, v2, v1453; SI-NEXT:    v_cvt_f32_f16_e32 v2, v0454; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1455; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3456; SI-NEXT:  .LBB2_3: ; %exit457; SI-NEXT:    v_cvt_f16_f32_e32 v0, v4458; SI-NEXT:    v_cvt_f16_f32_e32 v1, v3459; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2460; SI-NEXT:    v_mov_b32_e32 v3, 0x3fa00000461; SI-NEXT:    v_mov_b32_e32 v4, 0x3f200000462; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0463; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1464; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2465; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v0466; SI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc467; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v1468; SI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc469; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v2470; SI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc471; SI-NEXT:    v_mov_b32_e32 v3, v2472; SI-NEXT:    s_setpc_b64 s[30:31]473; SI-NEXT:  .LBB2_4:474; SI-NEXT:    ; implicit-def: $vgpr4475; SI-NEXT:    ; implicit-def: $vgpr3476; SI-NEXT:    ; implicit-def: $vgpr2477; SI-NEXT:    s_mov_b64 vcc, 0478; SI-NEXT:    s_branch .LBB2_2479;480; GFX9-LABEL: vec_8xf16_extract_4xf16:481; GFX9:       ; %bb.0:482; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)483; GFX9-NEXT:    s_cmp_lg_u32 s16, 0484; GFX9-NEXT:    s_cbranch_scc0 .LBB2_4485; GFX9-NEXT:  ; %bb.1: ; %F486; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[2:3], off glc487; GFX9-NEXT:    s_waitcnt vmcnt(0)488; GFX9-NEXT:    s_cbranch_execnz .LBB2_3489; GFX9-NEXT:  .LBB2_2: ; %T490; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off glc491; GFX9-NEXT:    s_waitcnt vmcnt(0)492; GFX9-NEXT:  .LBB2_3: ; %exit493; GFX9-NEXT:    v_mov_b32_e32 v0, 0x3900494; GFX9-NEXT:    v_mov_b32_e32 v1, 0x3d00495; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v2496; GFX9-NEXT:    v_mov_b32_e32 v5, 0x3800497; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v1, vcc498; GFX9-NEXT:    v_cmp_le_f16_sdwa vcc, v2, v5 src0_sel:WORD_1 src1_sel:DWORD499; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc500; GFX9-NEXT:    v_cmp_nge_f16_e32 vcc, 0.5, v3501; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v0, vcc502; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v3503; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc504; GFX9-NEXT:    v_pack_b32_f16 v1, v0, v5505; GFX9-NEXT:    v_pack_b32_f16 v0, v4, v2506; GFX9-NEXT:    s_setpc_b64 s[30:31]507; GFX9-NEXT:  .LBB2_4:508; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5509; GFX9-NEXT:    s_branch .LBB2_2510;511; GFX11-TRUE16-LABEL: vec_8xf16_extract_4xf16:512; GFX11-TRUE16:       ; %bb.0:513; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)514; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0515; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0516; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB2_4517; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F518; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc519; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)520; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0521; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB2_3522; GFX11-TRUE16-NEXT:  .LBB2_2: ; %T523; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc524; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)525; GFX11-TRUE16-NEXT:  .LBB2_3: ; %exit526; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l527; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 0x3900528; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v2.h529; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, 0.5, v3.l530; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s2, 0.5, v3.l531; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)532; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, 0x3d00, vcc_lo533; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.l, 0x3d00, s0534; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)535; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x3d00, v0.l, s1536; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, 0x3d00, s2537; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)538; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v1.l539; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v2.l, v1.h540; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]541; GFX11-TRUE16-NEXT:  .LBB2_4:542; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5543; GFX11-TRUE16-NEXT:    s_branch .LBB2_2544;545; GFX11-FAKE16-LABEL: vec_8xf16_extract_4xf16:546; GFX11-FAKE16:       ; %bb.0:547; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)548; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0549; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0550; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB2_4551; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F552; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc553; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)554; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0555; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB2_3556; GFX11-FAKE16-NEXT:  .LBB2_2: ; %T557; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc558; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)559; GFX11-FAKE16-NEXT:  .LBB2_3: ; %exit560; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x3d00561; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v2562; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2563; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)564; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v0, vcc_lo565; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v1566; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, 0x3900 :: v_dual_cndmask_b32 v1, 0x3900, v0567; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v3568; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)569; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3d00, v4, vcc_lo570; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3571; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v0, vcc_lo572; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v1573; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v4574; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]575; GFX11-FAKE16-NEXT:  .LBB2_4:576; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5577; GFX11-FAKE16-NEXT:    s_branch .LBB2_2578  %cond = icmp eq i32 %cond.arg, 0579  br i1 %cond, label %T, label %F580 581T:582  %t = load volatile <8 x half>, ptr addrspace(1) %p0583  br label %exit584 585F:586  %f = load volatile <8 x half>, ptr addrspace(1) %p1587  br label %exit588 589exit:590  %m = phi <8 x half> [ %t, %T ], [ %f, %F ]591  %v2 = shufflevector <8 x half> %m, <8 x half> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>592  %b2 = fcmp ugt <4 x half> %v2, <half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800>593  %r2 = select <4 x i1> %b2, <4 x half> <half 0xH3900, half 0xH3900, half 0xH3900, half 0xH3900>, <4 x half> <half 0xH3D00, half 0xH3D00, half 0xH3D00, half 0xH3D00>594  ret <4 x half> %r2595}596 597define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i32 inreg %cond.arg) {598;599; SI-LABEL: vec_16xi16_extract_4xi16:600; SI:       ; %bb.0:601; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)602; SI-NEXT:    s_cmp_lg_u32 s16, 0603; SI-NEXT:    s_mov_b32 s6, 0604; SI-NEXT:    s_cbranch_scc0 .LBB3_4605; SI-NEXT:  ; %bb.1: ; %F606; SI-NEXT:    s_mov_b32 s7, 0xf000607; SI-NEXT:    s_mov_b32 s4, s6608; SI-NEXT:    s_mov_b32 s5, s6609; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[4:7], 0 addr64 glc610; SI-NEXT:    s_waitcnt vmcnt(0)611; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:2 glc612; SI-NEXT:    s_waitcnt vmcnt(0)613; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[4:7], 0 addr64 offset:4 glc614; SI-NEXT:    s_waitcnt vmcnt(0)615; SI-NEXT:    buffer_load_ushort v7, v[2:3], s[4:7], 0 addr64 offset:6 glc616; SI-NEXT:    s_waitcnt vmcnt(0)617; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:8 glc618; SI-NEXT:    s_waitcnt vmcnt(0)619; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:10 glc620; SI-NEXT:    s_waitcnt vmcnt(0)621; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:12 glc622; SI-NEXT:    s_waitcnt vmcnt(0)623; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:14 glc624; SI-NEXT:    s_waitcnt vmcnt(0)625; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:16 glc626; SI-NEXT:    s_waitcnt vmcnt(0)627; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:18 glc628; SI-NEXT:    s_waitcnt vmcnt(0)629; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:20 glc630; SI-NEXT:    s_waitcnt vmcnt(0)631; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:22 glc632; SI-NEXT:    s_waitcnt vmcnt(0)633; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:24 glc634; SI-NEXT:    s_waitcnt vmcnt(0)635; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:26 glc636; SI-NEXT:    s_waitcnt vmcnt(0)637; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:28 glc638; SI-NEXT:    s_waitcnt vmcnt(0)639; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:30 glc640; SI-NEXT:    s_waitcnt vmcnt(0)641; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v7642; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4643; SI-NEXT:    v_or_b32_e32 v2, v6, v2644; SI-NEXT:    v_or_b32_e32 v3, v5, v3645; SI-NEXT:    s_mov_b64 vcc, exec646; SI-NEXT:    s_cbranch_execnz .LBB3_3647; SI-NEXT:  .LBB3_2: ; %T648; SI-NEXT:    s_mov_b32 s7, 0xf000649; SI-NEXT:    s_mov_b32 s4, s6650; SI-NEXT:    s_mov_b32 s5, s6651; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 glc652; SI-NEXT:    s_waitcnt vmcnt(0)653; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:2 glc654; SI-NEXT:    s_waitcnt vmcnt(0)655; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:4 glc656; SI-NEXT:    s_waitcnt vmcnt(0)657; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:6 glc658; SI-NEXT:    s_waitcnt vmcnt(0)659; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:8 glc660; SI-NEXT:    s_waitcnt vmcnt(0)661; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:10 glc662; SI-NEXT:    s_waitcnt vmcnt(0)663; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:12 glc664; SI-NEXT:    s_waitcnt vmcnt(0)665; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:14 glc666; SI-NEXT:    s_waitcnt vmcnt(0)667; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:16 glc668; SI-NEXT:    s_waitcnt vmcnt(0)669; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:18 glc670; SI-NEXT:    s_waitcnt vmcnt(0)671; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:20 glc672; SI-NEXT:    s_waitcnt vmcnt(0)673; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:22 glc674; SI-NEXT:    s_waitcnt vmcnt(0)675; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:24 glc676; SI-NEXT:    s_waitcnt vmcnt(0)677; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:26 glc678; SI-NEXT:    s_waitcnt vmcnt(0)679; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:28 glc680; SI-NEXT:    s_waitcnt vmcnt(0)681; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:30 glc682; SI-NEXT:    s_waitcnt vmcnt(0)683; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v5684; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v4685; SI-NEXT:    v_or_b32_e32 v2, v2, v0686; SI-NEXT:    v_or_b32_e32 v3, v3, v1687; SI-NEXT:  .LBB3_3: ; %exit688; SI-NEXT:    v_bfe_i32 v0, v3, 0, 16689; SI-NEXT:    v_bfe_i32 v1, v4, 0, 16690; SI-NEXT:    v_bfe_i32 v2, v2, 0, 16691; SI-NEXT:    v_mov_b32_e32 v3, 0xffff692; SI-NEXT:    v_mov_b32_e32 v4, 0x8000693; SI-NEXT:    v_mov_b32_e32 v5, 0xffff0000694; SI-NEXT:    v_bfrev_b32_e32 v6, 1695; SI-NEXT:    v_mov_b32_e32 v7, 0xffff8000696; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v0697; SI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc698; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v1699; SI-NEXT:    v_cndmask_b32_e32 v1, v5, v6, vcc700; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v2701; SI-NEXT:    v_cndmask_b32_e32 v2, -1, v7, vcc702; SI-NEXT:    v_or_b32_e32 v0, v0, v1703; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v2704; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v2705; SI-NEXT:    v_or_b32_e32 v2, v3, v4706; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 16707; SI-NEXT:    s_setpc_b64 s[30:31]708; SI-NEXT:  .LBB3_4:709; SI-NEXT:    ; implicit-def: $vgpr3710; SI-NEXT:    ; implicit-def: $vgpr4711; SI-NEXT:    ; implicit-def: $vgpr2712; SI-NEXT:    s_mov_b64 vcc, 0713; SI-NEXT:    s_branch .LBB3_2714;715; GFX9-LABEL: vec_16xi16_extract_4xi16:716; GFX9:       ; %bb.0:717; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)718; GFX9-NEXT:    s_cmp_lg_u32 s16, 0719; GFX9-NEXT:    s_cbranch_scc0 .LBB3_4720; GFX9-NEXT:  ; %bb.1: ; %F721; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off offset:16 glc722; GFX9-NEXT:    s_waitcnt vmcnt(0)723; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off glc724; GFX9-NEXT:    s_waitcnt vmcnt(0)725; GFX9-NEXT:    ; kill: killed $vgpr2 killed $vgpr3726; GFX9-NEXT:    s_cbranch_execnz .LBB3_3727; GFX9-NEXT:  .LBB3_2: ; %T728; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc729; GFX9-NEXT:    s_waitcnt vmcnt(0)730; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[0:1], off glc731; GFX9-NEXT:    s_waitcnt vmcnt(0)732; GFX9-NEXT:    ; kill: killed $vgpr0 killed $vgpr1733; GFX9-NEXT:  .LBB3_3: ; %exit734; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v5 op_sel_hi:[0,0]735; GFX9-NEXT:    s_movk_i32 s4, 0x8000736; GFX9-NEXT:    v_or_b32_e32 v1, 0xffff8000, v0737; GFX9-NEXT:    v_or_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD738; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]739; GFX9-NEXT:    v_or_b32_e32 v3, 0xffff8000, v0740; GFX9-NEXT:    v_or_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD741; GFX9-NEXT:    s_mov_b32 s4, 0x5040100742; GFX9-NEXT:    v_perm_b32 v0, v0, v3, s4743; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s4744; GFX9-NEXT:    s_setpc_b64 s[30:31]745; GFX9-NEXT:  .LBB3_4:746; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11747; GFX9-NEXT:    s_branch .LBB3_2748;749; GFX11-TRUE16-LABEL: vec_16xi16_extract_4xi16:750; GFX11-TRUE16:       ; %bb.0:751; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)752; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0753; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0754; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB3_4755; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F756; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc757; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)758; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc759; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)760; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0761; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB3_3762; GFX11-TRUE16-NEXT:  .LBB3_2: ; %T763; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc764; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)765; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc766; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)767; GFX11-TRUE16-NEXT:  .LBB3_3: ; %exit768; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]769; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]770; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)771; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l772; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l773; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)774; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h775; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h776; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]777; GFX11-TRUE16-NEXT:  .LBB3_4:778; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9779; GFX11-TRUE16-NEXT:    s_branch .LBB3_2780;781; GFX11-FAKE16-LABEL: vec_16xi16_extract_4xi16:782; GFX11-FAKE16:       ; %bb.0:783; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)784; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 0785; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 0786; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB3_4787; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F788; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc789; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)790; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc791; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)792; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s0793; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB3_3794; GFX11-FAKE16-NEXT:  .LBB3_2: ; %T795; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc796; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)797; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc798; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)799; GFX11-FAKE16-NEXT:  .LBB3_3: ; %exit800; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v2 op_sel_hi:[0,1]801; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v3 op_sel_hi:[0,0]802; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)803; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0804; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1805; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v1806; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v0807; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)808; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v2809; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v3810; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)811; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100812; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x5040100813; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]814; GFX11-FAKE16-NEXT:  .LBB3_4:815; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9816; GFX11-FAKE16-NEXT:    s_branch .LBB3_2817  %cond = icmp eq i32 %cond.arg, 0818  br i1 %cond, label %T, label %F819 820T:821  %t = load volatile <16 x i16>, ptr addrspace(1) %p0822  br label %exit823 824F:825  %f = load volatile <16 x i16>, ptr addrspace(1) %p1826  br label %exit827 828exit:829  %m = phi <16 x i16> [ %t, %T ], [ %f, %F ]830  %v2 = shufflevector <16 x i16> %m, <16 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>831  %b2 = icmp sgt <4 x i16> %v2, <i16 -1, i16 -1, i16 -1, i16 -1>832  %r2 = select <4 x i1> %b2, <4 x i16> <i16 -32768, i16 -32768, i16 -32768, i16 -32768>, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>833  ret <4 x i16> %r2834}835 836define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i32 inreg %cond.arg) {837;838; SI-LABEL: vec_16xi16_extract_4xi16_2:839; SI:       ; %bb.0:840; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)841; SI-NEXT:    s_cmp_lg_u32 s16, 0842; SI-NEXT:    s_mov_b32 s6, 0843; SI-NEXT:    s_cbranch_scc0 .LBB4_4844; SI-NEXT:  ; %bb.1: ; %F845; SI-NEXT:    s_mov_b32 s7, 0xf000846; SI-NEXT:    s_mov_b32 s4, s6847; SI-NEXT:    s_mov_b32 s5, s6848; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc849; SI-NEXT:    s_waitcnt vmcnt(0)850; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:2 glc851; SI-NEXT:    s_waitcnt vmcnt(0)852; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:4 glc853; SI-NEXT:    s_waitcnt vmcnt(0)854; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:6 glc855; SI-NEXT:    s_waitcnt vmcnt(0)856; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[4:7], 0 addr64 offset:8 glc857; SI-NEXT:    s_waitcnt vmcnt(0)858; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 offset:10 glc859; SI-NEXT:    s_waitcnt vmcnt(0)860; SI-NEXT:    buffer_load_ushort v7, v[2:3], s[4:7], 0 addr64 offset:12 glc861; SI-NEXT:    s_waitcnt vmcnt(0)862; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[4:7], 0 addr64 offset:14 glc863; SI-NEXT:    s_waitcnt vmcnt(0)864; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:16 glc865; SI-NEXT:    s_waitcnt vmcnt(0)866; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:18 glc867; SI-NEXT:    s_waitcnt vmcnt(0)868; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:20 glc869; SI-NEXT:    s_waitcnt vmcnt(0)870; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:22 glc871; SI-NEXT:    s_waitcnt vmcnt(0)872; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:24 glc873; SI-NEXT:    s_waitcnt vmcnt(0)874; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:26 glc875; SI-NEXT:    s_waitcnt vmcnt(0)876; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:28 glc877; SI-NEXT:    s_waitcnt vmcnt(0)878; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:30 glc879; SI-NEXT:    s_waitcnt vmcnt(0)880; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v5881; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v4882; SI-NEXT:    v_or_b32_e32 v2, v7, v2883; SI-NEXT:    v_or_b32_e32 v3, v6, v3884; SI-NEXT:    s_mov_b64 vcc, exec885; SI-NEXT:    s_cbranch_execnz .LBB4_3886; SI-NEXT:  .LBB4_2: ; %T887; SI-NEXT:    s_mov_b32 s7, 0xf000888; SI-NEXT:    s_mov_b32 s4, s6889; SI-NEXT:    s_mov_b32 s5, s6890; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc891; SI-NEXT:    s_waitcnt vmcnt(0)892; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:2 glc893; SI-NEXT:    s_waitcnt vmcnt(0)894; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:4 glc895; SI-NEXT:    s_waitcnt vmcnt(0)896; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:6 glc897; SI-NEXT:    s_waitcnt vmcnt(0)898; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 offset:8 glc899; SI-NEXT:    s_waitcnt vmcnt(0)900; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:10 glc901; SI-NEXT:    s_waitcnt vmcnt(0)902; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 offset:12 glc903; SI-NEXT:    s_waitcnt vmcnt(0)904; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:14 glc905; SI-NEXT:    s_waitcnt vmcnt(0)906; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:16 glc907; SI-NEXT:    s_waitcnt vmcnt(0)908; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:18 glc909; SI-NEXT:    s_waitcnt vmcnt(0)910; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:20 glc911; SI-NEXT:    s_waitcnt vmcnt(0)912; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:22 glc913; SI-NEXT:    s_waitcnt vmcnt(0)914; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:24 glc915; SI-NEXT:    s_waitcnt vmcnt(0)916; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:26 glc917; SI-NEXT:    s_waitcnt vmcnt(0)918; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:28 glc919; SI-NEXT:    s_waitcnt vmcnt(0)920; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:30 glc921; SI-NEXT:    s_waitcnt vmcnt(0)922; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v5923; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v4924; SI-NEXT:    v_or_b32_e32 v2, v2, v0925; SI-NEXT:    v_or_b32_e32 v3, v3, v1926; SI-NEXT:  .LBB4_3: ; %exit927; SI-NEXT:    v_bfe_i32 v0, v3, 0, 16928; SI-NEXT:    v_bfe_i32 v1, v4, 0, 16929; SI-NEXT:    v_bfe_i32 v2, v2, 0, 16930; SI-NEXT:    v_bfe_i32 v3, v5, 0, 16931; SI-NEXT:    v_mov_b32_e32 v4, 0xffff932; SI-NEXT:    v_mov_b32_e32 v5, 0x8000933; SI-NEXT:    v_mov_b32_e32 v6, 0xffff0000934; SI-NEXT:    v_bfrev_b32_e32 v7, 1935; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v0936; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc937; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v1938; SI-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc939; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v2940; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v5, vcc941; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v3942; SI-NEXT:    v_cndmask_b32_e32 v3, v6, v7, vcc943; SI-NEXT:    v_or_b32_e32 v0, v0, v1944; SI-NEXT:    v_or_b32_e32 v2, v2, v3945; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 16946; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v3947; SI-NEXT:    s_setpc_b64 s[30:31]948; SI-NEXT:  .LBB4_4:949; SI-NEXT:    ; implicit-def: $vgpr3950; SI-NEXT:    ; implicit-def: $vgpr4951; SI-NEXT:    ; implicit-def: $vgpr2952; SI-NEXT:    ; implicit-def: $vgpr5953; SI-NEXT:    s_mov_b64 vcc, 0954; SI-NEXT:    s_branch .LBB4_2955;956; GFX9-LABEL: vec_16xi16_extract_4xi16_2:957; GFX9:       ; %bb.0:958; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)959; GFX9-NEXT:    s_cmp_lg_u32 s16, 0960; GFX9-NEXT:    s_cbranch_scc0 .LBB4_4961; GFX9-NEXT:  ; %bb.1: ; %F962; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off offset:16 glc963; GFX9-NEXT:    s_waitcnt vmcnt(0)964; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off glc965; GFX9-NEXT:    s_waitcnt vmcnt(0)966; GFX9-NEXT:    ; kill: killed $vgpr2 killed $vgpr3967; GFX9-NEXT:    s_cbranch_execnz .LBB4_3968; GFX9-NEXT:  .LBB4_2: ; %T969; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc970; GFX9-NEXT:    s_waitcnt vmcnt(0)971; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[0:1], off glc972; GFX9-NEXT:    s_waitcnt vmcnt(0)973; GFX9-NEXT:    ; kill: killed $vgpr0 killed $vgpr1974; GFX9-NEXT:  .LBB4_3: ; %exit975; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v7 op_sel_hi:[0,1]976; GFX9-NEXT:    s_movk_i32 s4, 0x8000977; GFX9-NEXT:    v_or_b32_e32 v1, 0xffff8000, v0978; GFX9-NEXT:    v_or_b32_sdwa v2, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD979; GFX9-NEXT:    v_pk_ashrrev_i16 v0, 15, v6 op_sel_hi:[0,1]980; GFX9-NEXT:    v_or_b32_e32 v3, 0xffff8000, v0981; GFX9-NEXT:    v_or_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD982; GFX9-NEXT:    s_mov_b32 s4, 0x5040100983; GFX9-NEXT:    v_perm_b32 v0, v0, v3, s4984; GFX9-NEXT:    v_perm_b32 v1, v2, v1, s4985; GFX9-NEXT:    s_setpc_b64 s[30:31]986; GFX9-NEXT:  .LBB4_4:987; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11988; GFX9-NEXT:    s_branch .LBB4_2989;990; GFX11-TRUE16-LABEL: vec_16xi16_extract_4xi16_2:991; GFX11-TRUE16:       ; %bb.0:992; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)993; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 0994; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 0995; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB4_4996; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F997; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc998; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)999; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc1000; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1001; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01002; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB4_31003; GFX11-TRUE16-NEXT:  .LBB4_2: ; %T1004; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc1005; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1006; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc1007; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1008; GFX11-TRUE16-NEXT:  .LBB4_3: ; %exit1009; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]1010; GFX11-TRUE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]1011; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1012; GFX11-TRUE16-NEXT:    v_or_b16 v1.l, 0x8000, v1.l1013; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, 0x8000, v0.l1014; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)1015; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, 0x8000, v0.h1016; GFX11-TRUE16-NEXT:    v_or_b16 v1.h, 0x8000, v1.h1017; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1018; GFX11-TRUE16-NEXT:  .LBB4_4:1019; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr91020; GFX11-TRUE16-NEXT:    s_branch .LBB4_21021;1022; GFX11-FAKE16-LABEL: vec_16xi16_extract_4xi16_2:1023; GFX11-FAKE16:       ; %bb.0:1024; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1025; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 01026; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 01027; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB4_41028; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F1029; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc1030; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1031; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc1032; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1033; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01034; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB4_31035; GFX11-FAKE16-NEXT:  .LBB4_2: ; %T1036; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc1037; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1038; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc1039; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1040; GFX11-FAKE16-NEXT:  .LBB4_3: ; %exit1041; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]1042; GFX11-FAKE16-NEXT:    v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]1043; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1044; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v01045; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v11046; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, 0xffff8000, v11047; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, 0xffff8000, v01048; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1049; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, 0xffff8000, v21050; GFX11-FAKE16-NEXT:    v_or_b32_e32 v3, 0xffff8000, v31051; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1052; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001053; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x50401001054; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1055; GFX11-FAKE16-NEXT:  .LBB4_4:1056; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr91057; GFX11-FAKE16-NEXT:    s_branch .LBB4_21058  %cond = icmp eq i32 %cond.arg, 01059  br i1 %cond, label %T, label %F1060 1061T:1062  %t = load volatile <16 x i16>, ptr addrspace(1) %p01063  br label %exit1064 1065F:1066  %f = load volatile <16 x i16>, ptr addrspace(1) %p11067  br label %exit1068 1069exit:1070  %m = phi <16 x i16> [ %t, %T ], [ %f, %F ]1071  %v2 = shufflevector <16 x i16> %m, <16 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1072  %b2 = icmp sgt <4 x i16> %v2, <i16 -1, i16 -1, i16 -1, i16 -1>1073  %r2 = select <4 x i1> %b2, <4 x i16> <i16 -32768, i16 -32768, i16 -32768, i16 -32768>, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>1074  ret <4 x i16> %r21075}1076 1077define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i32 inreg %cond.arg) {1078;1079; SI-LABEL: vec_16xf16_extract_4xf16:1080; SI:       ; %bb.0:1081; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1082; SI-NEXT:    s_cmp_lg_u32 s16, 01083; SI-NEXT:    s_mov_b32 s6, 01084; SI-NEXT:    s_cbranch_scc0 .LBB5_41085; SI-NEXT:  ; %bb.1: ; %F1086; SI-NEXT:    s_mov_b32 s7, 0xf0001087; SI-NEXT:    s_mov_b32 s4, s61088; SI-NEXT:    s_mov_b32 s5, s61089; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[4:7], 0 addr64 glc1090; SI-NEXT:    s_waitcnt vmcnt(0)1091; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[4:7], 0 addr64 offset:2 glc1092; SI-NEXT:    s_waitcnt vmcnt(0)1093; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[4:7], 0 addr64 offset:4 glc1094; SI-NEXT:    s_waitcnt vmcnt(0)1095; SI-NEXT:    buffer_load_ushort v7, v[2:3], s[4:7], 0 addr64 offset:6 glc1096; SI-NEXT:    s_waitcnt vmcnt(0)1097; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:8 glc1098; SI-NEXT:    s_waitcnt vmcnt(0)1099; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:10 glc1100; SI-NEXT:    s_waitcnt vmcnt(0)1101; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:12 glc1102; SI-NEXT:    s_waitcnt vmcnt(0)1103; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:14 glc1104; SI-NEXT:    s_waitcnt vmcnt(0)1105; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:16 glc1106; SI-NEXT:    s_waitcnt vmcnt(0)1107; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:18 glc1108; SI-NEXT:    s_waitcnt vmcnt(0)1109; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:20 glc1110; SI-NEXT:    s_waitcnt vmcnt(0)1111; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:22 glc1112; SI-NEXT:    s_waitcnt vmcnt(0)1113; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:24 glc1114; SI-NEXT:    s_waitcnt vmcnt(0)1115; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:26 glc1116; SI-NEXT:    s_waitcnt vmcnt(0)1117; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[4:7], 0 addr64 offset:28 glc1118; SI-NEXT:    s_waitcnt vmcnt(0)1119; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:30 glc1120; SI-NEXT:    s_waitcnt vmcnt(0)1121; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v71122; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v51123; SI-NEXT:    v_cvt_f32_f16_e32 v3, v51124; SI-NEXT:    v_or_b32_e32 v2, v6, v21125; SI-NEXT:    v_or_b32_e32 v4, v4, v71126; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21127; SI-NEXT:    v_cvt_f32_f16_e32 v4, v41128; SI-NEXT:    s_mov_b64 vcc, exec1129; SI-NEXT:    s_cbranch_execnz .LBB5_31130; SI-NEXT:  .LBB5_2: ; %T1131; SI-NEXT:    s_mov_b32 s7, 0xf0001132; SI-NEXT:    s_mov_b32 s4, s61133; SI-NEXT:    s_mov_b32 s5, s61134; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc1135; SI-NEXT:    s_waitcnt vmcnt(0)1136; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 offset:2 glc1137; SI-NEXT:    s_waitcnt vmcnt(0)1138; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[4:7], 0 addr64 offset:4 glc1139; SI-NEXT:    s_waitcnt vmcnt(0)1140; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[4:7], 0 addr64 offset:6 glc1141; SI-NEXT:    s_waitcnt vmcnt(0)1142; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:8 glc1143; SI-NEXT:    s_waitcnt vmcnt(0)1144; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:10 glc1145; SI-NEXT:    s_waitcnt vmcnt(0)1146; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:12 glc1147; SI-NEXT:    s_waitcnt vmcnt(0)1148; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:14 glc1149; SI-NEXT:    s_waitcnt vmcnt(0)1150; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:16 glc1151; SI-NEXT:    s_waitcnt vmcnt(0)1152; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:18 glc1153; SI-NEXT:    s_waitcnt vmcnt(0)1154; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:20 glc1155; SI-NEXT:    s_waitcnt vmcnt(0)1156; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:22 glc1157; SI-NEXT:    s_waitcnt vmcnt(0)1158; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:24 glc1159; SI-NEXT:    s_waitcnt vmcnt(0)1160; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:26 glc1161; SI-NEXT:    s_waitcnt vmcnt(0)1162; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[4:7], 0 addr64 offset:28 glc1163; SI-NEXT:    s_waitcnt vmcnt(0)1164; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:30 glc1165; SI-NEXT:    s_waitcnt vmcnt(0)1166; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v51167; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v31168; SI-NEXT:    v_or_b32_e32 v0, v4, v01169; SI-NEXT:    v_or_b32_e32 v1, v2, v11170; SI-NEXT:    v_cvt_f32_f16_e32 v2, v01171; SI-NEXT:    v_cvt_f32_f16_e32 v4, v11172; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31173; SI-NEXT:  .LBB5_3: ; %exit1174; SI-NEXT:    v_cvt_f16_f32_e32 v0, v41175; SI-NEXT:    v_cvt_f16_f32_e32 v1, v31176; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21177; SI-NEXT:    v_mov_b32_e32 v3, 0x3fa000001178; SI-NEXT:    v_mov_b32_e32 v4, 0x3f2000001179; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01180; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11181; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21182; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v01183; SI-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc1184; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v11185; SI-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc1186; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v21187; SI-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc1188; SI-NEXT:    v_mov_b32_e32 v3, v21189; SI-NEXT:    s_setpc_b64 s[30:31]1190; SI-NEXT:  .LBB5_4:1191; SI-NEXT:    ; implicit-def: $vgpr41192; SI-NEXT:    ; implicit-def: $vgpr31193; SI-NEXT:    ; implicit-def: $vgpr21194; SI-NEXT:    s_mov_b64 vcc, 01195; SI-NEXT:    s_branch .LBB5_21196;1197; GFX9-LABEL: vec_16xf16_extract_4xf16:1198; GFX9:       ; %bb.0:1199; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1200; GFX9-NEXT:    s_cmp_lg_u32 s16, 01201; GFX9-NEXT:    s_cbranch_scc0 .LBB5_41202; GFX9-NEXT:  ; %bb.1: ; %F1203; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off offset:16 glc1204; GFX9-NEXT:    s_waitcnt vmcnt(0)1205; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off glc1206; GFX9-NEXT:    s_waitcnt vmcnt(0)1207; GFX9-NEXT:    ; kill: killed $vgpr2 killed $vgpr31208; GFX9-NEXT:    s_cbranch_execnz .LBB5_31209; GFX9-NEXT:  .LBB5_2: ; %T1210; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc1211; GFX9-NEXT:    s_waitcnt vmcnt(0)1212; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[0:1], off glc1213; GFX9-NEXT:    s_waitcnt vmcnt(0)1214; GFX9-NEXT:    ; kill: killed $vgpr0 killed $vgpr11215; GFX9-NEXT:  .LBB5_3: ; %exit1216; GFX9-NEXT:    v_mov_b32_e32 v0, 0x39001217; GFX9-NEXT:    v_mov_b32_e32 v1, 0x3d001218; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v41219; GFX9-NEXT:    v_mov_b32_e32 v3, 0x38001220; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc1221; GFX9-NEXT:    v_cmp_le_f16_sdwa vcc, v4, v3 src0_sel:WORD_1 src1_sel:DWORD1222; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc1223; GFX9-NEXT:    v_cmp_nge_f16_e32 vcc, 0.5, v51224; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v0, vcc1225; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v51226; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc1227; GFX9-NEXT:    v_pack_b32_f16 v1, v0, v41228; GFX9-NEXT:    v_pack_b32_f16 v0, v2, v31229; GFX9-NEXT:    s_setpc_b64 s[30:31]1230; GFX9-NEXT:  .LBB5_4:1231; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr111232; GFX9-NEXT:    s_branch .LBB5_21233;1234; GFX11-TRUE16-LABEL: vec_16xf16_extract_4xf16:1235; GFX11-TRUE16:       ; %bb.0:1236; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1237; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s0, 01238; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 01239; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB5_41240; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F1241; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc1242; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1243; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc1244; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1245; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01246; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB5_31247; GFX11-TRUE16-NEXT:  .LBB5_2: ; %T1248; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc1249; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1250; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc1251; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1252; GFX11-TRUE16-NEXT:  .LBB5_3: ; %exit1253; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l1254; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 0x39001255; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v2.h1256; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, 0.5, v3.l1257; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s2, 0.5, v3.l1258; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1259; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, 0x3d00, vcc_lo1260; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.l, 0x3d00, s01261; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1262; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, 0x3d00, v0.l, s11263; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, 0x3d00, s21264; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1265; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v1.l1266; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v2.l, v1.h1267; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1268; GFX11-TRUE16-NEXT:  .LBB5_4:1269; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr91270; GFX11-TRUE16-NEXT:    s_branch .LBB5_21271;1272; GFX11-FAKE16-LABEL: vec_16xf16_extract_4xf16:1273; GFX11-FAKE16:       ; %bb.0:1274; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1275; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s0, 01276; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 01277; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB5_41278; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F1279; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc1280; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1281; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc1282; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1283; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01284; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB5_31285; GFX11-FAKE16-NEXT:  .LBB5_2: ; %T1286; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc1287; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1288; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc1289; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1290; GFX11-FAKE16-NEXT:  .LBB5_3: ; %exit1291; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x3d001292; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v21293; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v21294; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1295; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v0, vcc_lo1296; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v11297; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v4, 0x3900 :: v_dual_cndmask_b32 v1, 0x3900, v01298; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v31299; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)1300; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3d00, v4, vcc_lo1301; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v31302; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v0, vcc_lo1303; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v11304; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v41305; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1306; GFX11-FAKE16-NEXT:  .LBB5_4:1307; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr91308; GFX11-FAKE16-NEXT:    s_branch .LBB5_21309  %cond = icmp eq i32 %cond.arg, 01310  br i1 %cond, label %T, label %F1311 1312T:1313  %t = load volatile <16 x half>, ptr addrspace(1) %p01314  br label %exit1315 1316F:1317  %f = load volatile <16 x half>, ptr addrspace(1) %p11318  br label %exit1319 1320exit:1321  %m = phi <16 x half> [ %t, %T ], [ %f, %F ]1322  %v2 = shufflevector <16 x half> %m, <16 x half> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>1323  %b2 = fcmp ugt <4 x half> %v2, <half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800>1324  %r2 = select <4 x i1> %b2, <4 x half> <half 0xH3900, half 0xH3900, half 0xH3900, half 0xH3900>, <4 x half> <half 0xH3D00, half 0xH3D00, half 0xH3D00, half 0xH3D00>1325  ret <4 x half> %r21326}1327 1328define <8 x i16> @large_vector(ptr addrspace(3) %p, i32 %idxp) {1329; SI-LABEL: large_vector:1330; SI:       ; %bb.0:1331; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1332; SI-NEXT:    v_lshlrev_b32_e32 v1, 5, v11333; SI-NEXT:    v_add_i32_e32 v0, vcc, v0, v11334; SI-NEXT:    v_add_i32_e32 v1, vcc, 4, v01335; SI-NEXT:    v_add_i32_e32 v3, vcc, 8, v01336; SI-NEXT:    v_add_i32_e32 v5, vcc, 12, v01337; SI-NEXT:    s_mov_b32 m0, -11338; SI-NEXT:    ds_read_b32 v0, v01339; SI-NEXT:    ds_read_b32 v2, v11340; SI-NEXT:    ds_read_b32 v4, v31341; SI-NEXT:    ds_read_b32 v6, v51342; SI-NEXT:    s_waitcnt lgkmcnt(3)1343; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v01344; SI-NEXT:    s_waitcnt lgkmcnt(2)1345; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v21346; SI-NEXT:    s_waitcnt lgkmcnt(1)1347; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v41348; SI-NEXT:    s_waitcnt lgkmcnt(0)1349; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v61350; SI-NEXT:    s_setpc_b64 s[30:31]1351;1352; GFX9-LABEL: large_vector:1353; GFX9:       ; %bb.0:1354; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1355; GFX9-NEXT:    v_lshl_add_u32 v2, v1, 5, v01356; GFX9-NEXT:    ds_read2_b32 v[0:1], v2 offset1:11357; GFX9-NEXT:    ds_read2_b32 v[2:3], v2 offset0:2 offset1:31358; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1359; GFX9-NEXT:    s_setpc_b64 s[30:31]1360;1361; GFX11-LABEL: large_vector:1362; GFX11:       ; %bb.0:1363; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1364; GFX11-NEXT:    v_lshl_add_u32 v2, v1, 5, v01365; GFX11-NEXT:    ds_load_2addr_b32 v[0:1], v2 offset1:11366; GFX11-NEXT:    ds_load_2addr_b32 v[2:3], v2 offset0:2 offset1:31367; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1368; GFX11-NEXT:    s_setpc_b64 s[30:31]1369  %idx = shl i32 %idxp, 41370 1371  %i.0 = or disjoint i32 %idx, 01372  %p.0 = getelementptr half, ptr addrspace(3) %p, i32 %i.01373  %x.0 = load i16, ptr addrspace(3) %p.0, align 41374  %v0p = insertelement <8 x i16> poison, i16 %x.0, i32 01375  %i.1 = or disjoint i32 %idx, 11376  %p.1 = getelementptr half, ptr addrspace(3) %p, i32 %i.11377  %x.1 = load i16, ptr addrspace(3) %p.1, align 21378  %v0 = insertelement <8 x i16> %v0p, i16 %x.1, i32 11379 1380  %i.2 = or disjoint i32 %idx, 21381  %p.2 = getelementptr half, ptr addrspace(3) %p, i32 %i.21382  %x.2 = load i16, ptr addrspace(3) %p.2, align 41383  %v1p = insertelement <8 x i16> poison, i16 %x.2, i32 01384  %i.3 = or disjoint i32 %idx, 31385  %p.3 = getelementptr half, ptr addrspace(3) %p, i32 %i.31386  %x.3 = load i16, ptr addrspace(3) %p.3, align 21387  %v1 = insertelement <8 x i16> %v1p, i16 %x.3, i32 11388 1389  %i.4 = or disjoint i32 %idx, 41390  %p.4 = getelementptr half, ptr addrspace(3) %p, i32 %i.41391  %x.4 = load i16, ptr addrspace(3) %p.4, align 41392  %v2p = insertelement <8 x i16> poison, i16 %x.4, i32 01393  %i.5 = or disjoint i32 %idx, 51394  %p.5 = getelementptr half, ptr addrspace(3) %p, i32 %i.51395  %x.5 = load i16, ptr addrspace(3) %p.5, align 21396  %v2 = insertelement <8 x i16> %v2p, i16 %x.5, i32 11397 1398  %i.6 = or disjoint i32 %idx, 61399  %p.6 = getelementptr half, ptr addrspace(3) %p, i32 %i.61400  %x.6 = load i16, ptr addrspace(3) %p.6, align 41401  %v3p = insertelement <8 x i16> poison, i16 %x.6, i32 01402  %i.7 = or disjoint i32 %idx, 71403  %p.7 = getelementptr half, ptr addrspace(3) %p, i32 %i.71404  %x.7 = load i16, ptr addrspace(3) %p.7, align 21405  %v3 = insertelement <8 x i16> %v3p, i16 %x.7, i32 11406 1407  %z.1 = shufflevector <8 x i16> %v0, <8 x i16> %v1, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>1408  %z.2 = shufflevector <8 x i16> %z.1, <8 x i16> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison>1409  %z.3 = shufflevector <8 x i16> %z.2, <8 x i16> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>1410  ret <8 x i16> %z.31411}1412 1413define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addrspace(1) %p0, ptr addrspace(1) %p1) {1414; SI-LABEL: vec_16xi16_extract_8xi16_0:1415; SI:       ; %bb.0:1416; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1417; SI-NEXT:    buffer_load_ubyte v4, off, s[0:3], s321418; SI-NEXT:    s_waitcnt vmcnt(0)1419; SI-NEXT:    v_and_b32_e32 v4, 1, v41420; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v41421; SI-NEXT:    s_and_b64 s[34:35], vcc, exec1422; SI-NEXT:    s_mov_b32 s38, 01423; SI-NEXT:    s_cbranch_scc0 .LBB7_21424; SI-NEXT:  ; %bb.1: ; %F1425; SI-NEXT:    s_mov_b32 s39, 0xf0001426; SI-NEXT:    s_mov_b32 s36, s381427; SI-NEXT:    s_mov_b32 s37, s381428; SI-NEXT:    buffer_load_ushort v9, v[2:3], s[36:39], 0 addr64 glc1429; SI-NEXT:    s_waitcnt vmcnt(0)1430; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[36:39], 0 addr64 offset:2 glc1431; SI-NEXT:    s_waitcnt vmcnt(0)1432; SI-NEXT:    buffer_load_ushort v10, v[2:3], s[36:39], 0 addr64 offset:4 glc1433; SI-NEXT:    s_waitcnt vmcnt(0)1434; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[36:39], 0 addr64 offset:6 glc1435; SI-NEXT:    s_waitcnt vmcnt(0)1436; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[36:39], 0 addr64 offset:8 glc1437; SI-NEXT:    s_waitcnt vmcnt(0)1438; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[36:39], 0 addr64 offset:10 glc1439; SI-NEXT:    s_waitcnt vmcnt(0)1440; SI-NEXT:    buffer_load_ushort v11, v[2:3], s[36:39], 0 addr64 offset:12 glc1441; SI-NEXT:    s_waitcnt vmcnt(0)1442; SI-NEXT:    buffer_load_ushort v7, v[2:3], s[36:39], 0 addr64 offset:14 glc1443; SI-NEXT:    s_waitcnt vmcnt(0)1444; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:16 glc1445; SI-NEXT:    s_waitcnt vmcnt(0)1446; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:18 glc1447; SI-NEXT:    s_waitcnt vmcnt(0)1448; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:20 glc1449; SI-NEXT:    s_waitcnt vmcnt(0)1450; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:22 glc1451; SI-NEXT:    s_waitcnt vmcnt(0)1452; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:24 glc1453; SI-NEXT:    s_waitcnt vmcnt(0)1454; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:26 glc1455; SI-NEXT:    s_waitcnt vmcnt(0)1456; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:28 glc1457; SI-NEXT:    s_waitcnt vmcnt(0)1458; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[36:39], 0 addr64 offset:30 glc1459; SI-NEXT:    s_waitcnt vmcnt(0)1460; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v71461; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v61462; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v41463; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v51464; SI-NEXT:    v_or_b32_e32 v3, v11, v21465; SI-NEXT:    v_or_b32_e32 v8, v8, v121466; SI-NEXT:    v_or_b32_e32 v2, v10, v131467; SI-NEXT:    v_or_b32_e32 v9, v9, v141468; SI-NEXT:    s_mov_b64 vcc, exec1469; SI-NEXT:    s_cbranch_execz .LBB7_31470; SI-NEXT:    s_branch .LBB7_41471; SI-NEXT:  .LBB7_2:1472; SI-NEXT:    ; implicit-def: $vgpr91473; SI-NEXT:    ; implicit-def: $vgpr51474; SI-NEXT:    ; implicit-def: $vgpr21475; SI-NEXT:    ; implicit-def: $vgpr41476; SI-NEXT:    ; implicit-def: $vgpr81477; SI-NEXT:    ; implicit-def: $vgpr61478; SI-NEXT:    ; implicit-def: $vgpr31479; SI-NEXT:    ; implicit-def: $vgpr71480; SI-NEXT:    s_mov_b64 vcc, 01481; SI-NEXT:  .LBB7_3: ; %T1482; SI-NEXT:    s_mov_b32 s39, 0xf0001483; SI-NEXT:    s_mov_b32 s36, s381484; SI-NEXT:    s_mov_b32 s37, s381485; SI-NEXT:    buffer_load_ushort v9, v[0:1], s[36:39], 0 addr64 glc1486; SI-NEXT:    s_waitcnt vmcnt(0)1487; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[36:39], 0 addr64 offset:2 glc1488; SI-NEXT:    s_waitcnt vmcnt(0)1489; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[36:39], 0 addr64 offset:4 glc1490; SI-NEXT:    s_waitcnt vmcnt(0)1491; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[36:39], 0 addr64 offset:6 glc1492; SI-NEXT:    s_waitcnt vmcnt(0)1493; SI-NEXT:    buffer_load_ushort v8, v[0:1], s[36:39], 0 addr64 offset:8 glc1494; SI-NEXT:    s_waitcnt vmcnt(0)1495; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[36:39], 0 addr64 offset:10 glc1496; SI-NEXT:    s_waitcnt vmcnt(0)1497; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[36:39], 0 addr64 offset:12 glc1498; SI-NEXT:    s_waitcnt vmcnt(0)1499; SI-NEXT:    buffer_load_ushort v7, v[0:1], s[36:39], 0 addr64 offset:14 glc1500; SI-NEXT:    s_waitcnt vmcnt(0)1501; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:16 glc1502; SI-NEXT:    s_waitcnt vmcnt(0)1503; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:18 glc1504; SI-NEXT:    s_waitcnt vmcnt(0)1505; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:20 glc1506; SI-NEXT:    s_waitcnt vmcnt(0)1507; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:22 glc1508; SI-NEXT:    s_waitcnt vmcnt(0)1509; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:24 glc1510; SI-NEXT:    s_waitcnt vmcnt(0)1511; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:26 glc1512; SI-NEXT:    s_waitcnt vmcnt(0)1513; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:28 glc1514; SI-NEXT:    s_waitcnt vmcnt(0)1515; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[36:39], 0 addr64 offset:30 glc1516; SI-NEXT:    s_waitcnt vmcnt(0)1517; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v71518; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v61519; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v41520; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v51521; SI-NEXT:    v_or_b32_e32 v3, v3, v01522; SI-NEXT:    v_or_b32_e32 v8, v8, v11523; SI-NEXT:    v_or_b32_e32 v2, v2, v101524; SI-NEXT:    v_or_b32_e32 v9, v9, v111525; SI-NEXT:  .LBB7_4: ; %exit1526; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v91527; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v51528; SI-NEXT:    v_and_b32_e32 v5, 0xffff, v81529; SI-NEXT:    v_and_b32_e32 v6, 0xffff, v61530; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v31531; SI-NEXT:    v_and_b32_e32 v7, 0xffff, v71532; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21533; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v41534; SI-NEXT:    s_movk_i32 s34, 0x38001535; SI-NEXT:    v_mov_b32_e32 v8, 0x3d001536; SI-NEXT:    v_mov_b32_e32 v9, 0x39001537; SI-NEXT:    v_mov_b32_e32 v10, 0x3d0000001538; SI-NEXT:    v_mov_b32_e32 v11, 0x390000001539; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v01540; SI-NEXT:    v_cndmask_b32_e32 v0, v8, v9, vcc1541; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v11542; SI-NEXT:    v_cndmask_b32_e32 v1, v10, v11, vcc1543; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v51544; SI-NEXT:    v_cndmask_b32_e32 v5, v8, v9, vcc1545; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v61546; SI-NEXT:    v_cndmask_b32_e32 v12, v10, v11, vcc1547; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v31548; SI-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc1549; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v71550; SI-NEXT:    v_cndmask_b32_e32 v7, v10, v11, vcc1551; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v21552; SI-NEXT:    v_cndmask_b32_e32 v2, v8, v9, vcc1553; SI-NEXT:    v_cmp_lt_u32_e32 vcc, s34, v41554; SI-NEXT:    v_cndmask_b32_e32 v8, v10, v11, vcc1555; SI-NEXT:    v_or_b32_e32 v0, v0, v11556; SI-NEXT:    v_or_b32_e32 v4, v5, v121557; SI-NEXT:    v_or_b32_e32 v6, v3, v71558; SI-NEXT:    v_or_b32_e32 v2, v2, v81559; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v81560; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 161561; SI-NEXT:    v_alignbit_b32 v5, v6, v12, 161562; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v71563; SI-NEXT:    s_setpc_b64 s[30:31]1564;1565; GFX9-LABEL: vec_16xi16_extract_8xi16_0:1566; GFX9:       ; %bb.0:1567; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1568; GFX9-NEXT:    buffer_load_ubyte v4, off, s[0:3], s321569; GFX9-NEXT:    s_waitcnt vmcnt(0)1570; GFX9-NEXT:    v_and_b32_e32 v4, 1, v41571; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v41572; GFX9-NEXT:    s_and_b64 s[34:35], vcc, exec1573; GFX9-NEXT:    s_cbranch_scc0 .LBB7_21574; GFX9-NEXT:  ; %bb.1: ; %F1575; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off offset:16 glc1576; GFX9-NEXT:    s_waitcnt vmcnt(0)1577; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off glc1578; GFX9-NEXT:    s_waitcnt vmcnt(0)1579; GFX9-NEXT:    ; kill: killed $vgpr2 killed $vgpr31580; GFX9-NEXT:    s_cbranch_execz .LBB7_31581; GFX9-NEXT:    s_branch .LBB7_41582; GFX9-NEXT:  .LBB7_2:1583; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr111584; GFX9-NEXT:  .LBB7_3: ; %T1585; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc1586; GFX9-NEXT:    s_waitcnt vmcnt(0)1587; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[0:1], off glc1588; GFX9-NEXT:    s_waitcnt vmcnt(0)1589; GFX9-NEXT:    ; kill: killed $vgpr0 killed $vgpr11590; GFX9-NEXT:  .LBB7_4: ; %exit1591; GFX9-NEXT:    s_movk_i32 s35, 0x38011592; GFX9-NEXT:    s_movk_i32 s34, 0x38001593; GFX9-NEXT:    v_mov_b32_e32 v0, 0x39001594; GFX9-NEXT:    v_mov_b32_e32 v1, 0x3d001595; GFX9-NEXT:    v_cmp_gt_u16_e32 vcc, s35, v71596; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc1597; GFX9-NEXT:    v_cmp_gt_u16_sdwa vcc, v7, s34 src0_sel:WORD_1 src1_sel:DWORD1598; GFX9-NEXT:    v_cndmask_b32_e32 v7, v1, v0, vcc1599; GFX9-NEXT:    v_cmp_gt_u16_e32 vcc, s35, v61600; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc1601; GFX9-NEXT:    v_cmp_lt_u16_sdwa vcc, v6, s35 src0_sel:WORD_1 src1_sel:DWORD1602; GFX9-NEXT:    v_cndmask_b32_e32 v6, v0, v1, vcc1603; GFX9-NEXT:    v_cmp_gt_u16_e32 vcc, s35, v51604; GFX9-NEXT:    v_cndmask_b32_e32 v8, v0, v1, vcc1605; GFX9-NEXT:    v_cmp_lt_u16_sdwa vcc, v5, s35 src0_sel:WORD_1 src1_sel:DWORD1606; GFX9-NEXT:    v_cndmask_b32_e32 v5, v0, v1, vcc1607; GFX9-NEXT:    v_cmp_gt_u16_e32 vcc, s35, v41608; GFX9-NEXT:    v_cndmask_b32_e32 v9, v0, v1, vcc1609; GFX9-NEXT:    v_cmp_lt_u16_sdwa vcc, v4, s35 src0_sel:WORD_1 src1_sel:DWORD1610; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc1611; GFX9-NEXT:    s_mov_b32 s34, 0x50401001612; GFX9-NEXT:    v_perm_b32 v0, v0, v9, s341613; GFX9-NEXT:    v_perm_b32 v1, v5, v8, s341614; GFX9-NEXT:    v_perm_b32 v2, v6, v2, s341615; GFX9-NEXT:    v_perm_b32 v3, v7, v3, s341616; GFX9-NEXT:    s_setpc_b64 s[30:31]1617;1618; GFX11-TRUE16-LABEL: vec_16xi16_extract_8xi16_0:1619; GFX11-TRUE16:       ; %bb.0:1620; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1621; GFX11-TRUE16-NEXT:    scratch_load_u8 v4, off, s321622; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 01623; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1624; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 1, v41625; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1626; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v41627; GFX11-TRUE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo1628; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB7_21629; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F1630; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc1631; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1632; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off glc dlc1633; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1634; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01635; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB7_31636; GFX11-TRUE16-NEXT:    s_branch .LBB7_41637; GFX11-TRUE16-NEXT:  .LBB7_2:1638; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr111639; GFX11-TRUE16-NEXT:  .LBB7_3: ; %T1640; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc1641; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1642; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[0:1], off glc dlc1643; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1644; GFX11-TRUE16-NEXT:  .LBB7_4: ; %exit1645; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v7.l1646; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, 0x39001647; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s0, 0x3801, v6.l1648; GFX11-TRUE16-NEXT:    v_cmp_lt_u16_e64 s1, 0x3800, v7.h1649; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s2, 0x3801, v4.h1650; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s3, 0x3801, v5.h1651; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.h, 0x3d00, vcc_lo1652; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v3.h, 0x3d00, s01653; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v5.l1654; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s0, 0x3801, v4.l1655; GFX11-TRUE16-NEXT:    v_cmp_gt_u16_e64 s34, 0x3801, v6.h1656; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.h, 0x3d00, s21657; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v3.h, 0x3d00, s31658; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v3.h, 0x3d00, vcc_lo1659; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v3.h, 0x3d00, s01660; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v3.h, 0x3d00, s341661; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, 0x3d00, v3.h, s11662; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1663;1664; GFX11-FAKE16-LABEL: vec_16xi16_extract_8xi16_0:1665; GFX11-FAKE16:       ; %bb.0:1666; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1667; GFX11-FAKE16-NEXT:    scratch_load_u8 v4, off, s321668; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 01669; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1670; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 1, v41671; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1672; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v41673; GFX11-FAKE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo1674; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB7_21675; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F1676; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc1677; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1678; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc1679; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1680; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01681; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB7_31682; GFX11-FAKE16-NEXT:    s_branch .LBB7_41683; GFX11-FAKE16-NEXT:  .LBB7_2:1684; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr91685; GFX11-FAKE16-NEXT:  .LBB7_3: ; %T1686; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc1687; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1688; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc1689; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1690; GFX11-FAKE16-NEXT:  .LBB7_4: ; %exit1691; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v51692; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, 0x39001693; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0x3d001694; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v41695; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v51696; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v21697; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v31698; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, 0x3900, v1, vcc_lo1699; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v41700; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3900, v1, vcc_lo1701; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v71702; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, 0x3900, v1, vcc_lo1703; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v31704; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v1, vcc_lo1705; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v21706; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v1, vcc_lo1707; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v01708; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x3900, v1, vcc_lo1709; GFX11-FAKE16-NEXT:    v_cmp_gt_u16_e32 vcc_lo, 0x3801, v61710; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)1711; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v2, 0x50401001712; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3900, v1, vcc_lo1713; GFX11-FAKE16-NEXT:    v_cmp_lt_u16_e32 vcc_lo, 0x3800, v81714; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v7, v4, 0x50401001715; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v1, v3, 0x50401001716; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, 0x3d00, v9, vcc_lo1717; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1718; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v6, v5, 0x50401001719; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1720  br i1 %cond, label %T, label %F1721 1722T:1723  %t = load volatile <16 x i16>, ptr addrspace(1) %p01724  br label %exit1725 1726F:1727  %f = load volatile <16 x i16>, ptr addrspace(1) %p11728  br label %exit1729 1730exit:1731  %m = phi <16 x i16> [ %t, %T ], [ %f, %F ]1732  %v2 = shufflevector <16 x i16> %m, <16 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1733  %b2 = icmp ugt <8 x i16> %v2, <i16 u0x3800, i16 u0x3800, i16 u0x3800, i16 u0x3800, i16 u0x3800, i16 u0x3800, i16 u0x3800, i16 u0x3800>1734  %r2 = select <8 x i1> %b2, <8 x i16> <i16 u0x3900, i16 u0x3900, i16 u0x3900, i16 u0x3900, i16 u0x3900, i16 u0x3900, i16 u0x3900, i16 u0x3900>, <8 x i16> <i16 u0x3D00, i16 u0x3D00, i16 u0x3D00, i16 u0x3D00, i16 u0x3D00, i16 u0x3D00, i16 u0x3D00, i16 u0x3D00>1735  ret <8 x i16> %r21736}1737 1738define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr addrspace(1) %p0, ptr addrspace(1) %p1) {1739; SI-LABEL: vec_16xf16_extract_8xf16_0:1740; SI:       ; %bb.0:1741; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1742; SI-NEXT:    buffer_load_ubyte v4, off, s[0:3], s321743; SI-NEXT:    s_waitcnt vmcnt(0)1744; SI-NEXT:    v_and_b32_e32 v4, 1, v41745; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v41746; SI-NEXT:    s_and_b64 s[34:35], vcc, exec1747; SI-NEXT:    s_mov_b32 s38, 01748; SI-NEXT:    s_cbranch_scc0 .LBB8_21749; SI-NEXT:  ; %bb.1: ; %F1750; SI-NEXT:    s_mov_b32 s39, 0xf0001751; SI-NEXT:    s_mov_b32 s36, s381752; SI-NEXT:    s_mov_b32 s37, s381753; SI-NEXT:    buffer_load_ushort v5, v[2:3], s[36:39], 0 addr64 glc1754; SI-NEXT:    s_waitcnt vmcnt(0)1755; SI-NEXT:    buffer_load_ushort v6, v[2:3], s[36:39], 0 addr64 offset:2 glc1756; SI-NEXT:    s_waitcnt vmcnt(0)1757; SI-NEXT:    buffer_load_ushort v7, v[2:3], s[36:39], 0 addr64 offset:4 glc1758; SI-NEXT:    s_waitcnt vmcnt(0)1759; SI-NEXT:    buffer_load_ushort v4, v[2:3], s[36:39], 0 addr64 offset:6 glc1760; SI-NEXT:    s_waitcnt vmcnt(0)1761; SI-NEXT:    buffer_load_ushort v8, v[2:3], s[36:39], 0 addr64 offset:8 glc1762; SI-NEXT:    s_waitcnt vmcnt(0)1763; SI-NEXT:    buffer_load_ushort v9, v[2:3], s[36:39], 0 addr64 offset:10 glc1764; SI-NEXT:    s_waitcnt vmcnt(0)1765; SI-NEXT:    buffer_load_ushort v10, v[2:3], s[36:39], 0 addr64 offset:12 glc1766; SI-NEXT:    s_waitcnt vmcnt(0)1767; SI-NEXT:    buffer_load_ushort v11, v[2:3], s[36:39], 0 addr64 offset:14 glc1768; SI-NEXT:    s_waitcnt vmcnt(0)1769; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:16 glc1770; SI-NEXT:    s_waitcnt vmcnt(0)1771; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:18 glc1772; SI-NEXT:    s_waitcnt vmcnt(0)1773; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:20 glc1774; SI-NEXT:    s_waitcnt vmcnt(0)1775; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:22 glc1776; SI-NEXT:    s_waitcnt vmcnt(0)1777; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:24 glc1778; SI-NEXT:    s_waitcnt vmcnt(0)1779; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:26 glc1780; SI-NEXT:    s_waitcnt vmcnt(0)1781; SI-NEXT:    buffer_load_ushort v12, v[2:3], s[36:39], 0 addr64 offset:28 glc1782; SI-NEXT:    s_waitcnt vmcnt(0)1783; SI-NEXT:    buffer_load_ushort v2, v[2:3], s[36:39], 0 addr64 offset:30 glc1784; SI-NEXT:    s_waitcnt vmcnt(0)1785; SI-NEXT:    v_lshlrev_b32_e32 v12, 16, v111786; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v91787; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v41788; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v61789; SI-NEXT:    v_cvt_f32_f16_e32 v2, v111790; SI-NEXT:    v_cvt_f32_f16_e32 v3, v91791; SI-NEXT:    v_cvt_f32_f16_e32 v4, v41792; SI-NEXT:    v_cvt_f32_f16_e32 v6, v61793; SI-NEXT:    v_or_b32_e32 v9, v10, v121794; SI-NEXT:    v_or_b32_e32 v8, v8, v131795; SI-NEXT:    v_or_b32_e32 v10, v7, v141796; SI-NEXT:    v_or_b32_e32 v11, v5, v151797; SI-NEXT:    v_cvt_f32_f16_e32 v5, v91798; SI-NEXT:    v_cvt_f32_f16_e32 v7, v81799; SI-NEXT:    v_cvt_f32_f16_e32 v8, v101800; SI-NEXT:    v_cvt_f32_f16_e32 v9, v111801; SI-NEXT:    s_mov_b64 vcc, exec1802; SI-NEXT:    s_cbranch_execz .LBB8_31803; SI-NEXT:    s_branch .LBB8_41804; SI-NEXT:  .LBB8_2:1805; SI-NEXT:    ; implicit-def: $vgpr91806; SI-NEXT:    ; implicit-def: $vgpr61807; SI-NEXT:    ; implicit-def: $vgpr81808; SI-NEXT:    ; implicit-def: $vgpr41809; SI-NEXT:    ; implicit-def: $vgpr71810; SI-NEXT:    ; implicit-def: $vgpr31811; SI-NEXT:    ; implicit-def: $vgpr51812; SI-NEXT:    ; implicit-def: $vgpr21813; SI-NEXT:    s_mov_b64 vcc, 01814; SI-NEXT:  .LBB8_3: ; %T1815; SI-NEXT:    s_mov_b32 s39, 0xf0001816; SI-NEXT:    s_mov_b32 s36, s381817; SI-NEXT:    s_mov_b32 s37, s381818; SI-NEXT:    buffer_load_ushort v5, v[0:1], s[36:39], 0 addr64 glc1819; SI-NEXT:    s_waitcnt vmcnt(0)1820; SI-NEXT:    buffer_load_ushort v6, v[0:1], s[36:39], 0 addr64 offset:2 glc1821; SI-NEXT:    s_waitcnt vmcnt(0)1822; SI-NEXT:    buffer_load_ushort v7, v[0:1], s[36:39], 0 addr64 offset:4 glc1823; SI-NEXT:    s_waitcnt vmcnt(0)1824; SI-NEXT:    buffer_load_ushort v4, v[0:1], s[36:39], 0 addr64 offset:6 glc1825; SI-NEXT:    s_waitcnt vmcnt(0)1826; SI-NEXT:    buffer_load_ushort v8, v[0:1], s[36:39], 0 addr64 offset:8 glc1827; SI-NEXT:    s_waitcnt vmcnt(0)1828; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[36:39], 0 addr64 offset:10 glc1829; SI-NEXT:    s_waitcnt vmcnt(0)1830; SI-NEXT:    buffer_load_ushort v9, v[0:1], s[36:39], 0 addr64 offset:12 glc1831; SI-NEXT:    s_waitcnt vmcnt(0)1832; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[36:39], 0 addr64 offset:14 glc1833; SI-NEXT:    s_waitcnt vmcnt(0)1834; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:16 glc1835; SI-NEXT:    s_waitcnt vmcnt(0)1836; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:18 glc1837; SI-NEXT:    s_waitcnt vmcnt(0)1838; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:20 glc1839; SI-NEXT:    s_waitcnt vmcnt(0)1840; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:22 glc1841; SI-NEXT:    s_waitcnt vmcnt(0)1842; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:24 glc1843; SI-NEXT:    s_waitcnt vmcnt(0)1844; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:26 glc1845; SI-NEXT:    s_waitcnt vmcnt(0)1846; SI-NEXT:    buffer_load_ushort v10, v[0:1], s[36:39], 0 addr64 offset:28 glc1847; SI-NEXT:    s_waitcnt vmcnt(0)1848; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[36:39], 0 addr64 offset:30 glc1849; SI-NEXT:    s_waitcnt vmcnt(0)1850; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v21851; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v31852; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v41853; SI-NEXT:    v_lshlrev_b32_e32 v11, 16, v61854; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21855; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31856; SI-NEXT:    v_cvt_f32_f16_e32 v4, v41857; SI-NEXT:    v_or_b32_e32 v0, v9, v01858; SI-NEXT:    v_or_b32_e32 v1, v8, v11859; SI-NEXT:    v_or_b32_e32 v8, v7, v101860; SI-NEXT:    v_or_b32_e32 v9, v5, v111861; SI-NEXT:    v_cvt_f32_f16_e32 v5, v01862; SI-NEXT:    v_cvt_f32_f16_e32 v7, v11863; SI-NEXT:    v_cvt_f32_f16_e32 v8, v81864; SI-NEXT:    v_cvt_f32_f16_e32 v9, v91865; SI-NEXT:    v_cvt_f32_f16_e32 v6, v61866; SI-NEXT:  .LBB8_4: ; %exit1867; SI-NEXT:    v_cvt_f16_f32_e32 v0, v91868; SI-NEXT:    v_cvt_f16_f32_e32 v1, v61869; SI-NEXT:    v_cvt_f16_f32_e32 v6, v81870; SI-NEXT:    v_cvt_f16_f32_e32 v4, v41871; SI-NEXT:    v_cvt_f16_f32_e32 v7, v71872; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31873; SI-NEXT:    v_cvt_f16_f32_e32 v5, v51874; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21875; SI-NEXT:    v_mov_b32_e32 v8, 0x3fa000001876; SI-NEXT:    v_mov_b32_e32 v9, 0x3f2000001877; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01878; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11879; SI-NEXT:    v_cvt_f32_f16_e32 v6, v61880; SI-NEXT:    v_cvt_f32_f16_e32 v4, v41881; SI-NEXT:    v_cvt_f32_f16_e32 v7, v71882; SI-NEXT:    v_cvt_f32_f16_e32 v10, v31883; SI-NEXT:    v_cvt_f32_f16_e32 v11, v51884; SI-NEXT:    v_cvt_f32_f16_e32 v12, v21885; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v01886; SI-NEXT:    v_cndmask_b32_e32 v0, v8, v9, vcc1887; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v11888; SI-NEXT:    v_cndmask_b32_e32 v1, v8, v9, vcc1889; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v61890; SI-NEXT:    v_cndmask_b32_e32 v2, v8, v9, vcc1891; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v41892; SI-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc1893; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v71894; SI-NEXT:    v_cndmask_b32_e32 v4, v8, v9, vcc1895; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v101896; SI-NEXT:    v_cndmask_b32_e32 v5, v8, v9, vcc1897; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v111898; SI-NEXT:    v_cndmask_b32_e32 v6, v8, v9, vcc1899; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 0.5, v121900; SI-NEXT:    v_cndmask_b32_e32 v7, v8, v9, vcc1901; SI-NEXT:    s_setpc_b64 s[30:31]1902;1903; GFX9-LABEL: vec_16xf16_extract_8xf16_0:1904; GFX9:       ; %bb.0:1905; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1906; GFX9-NEXT:    buffer_load_ubyte v4, off, s[0:3], s321907; GFX9-NEXT:    s_waitcnt vmcnt(0)1908; GFX9-NEXT:    v_and_b32_e32 v4, 1, v41909; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v41910; GFX9-NEXT:    s_and_b64 s[34:35], vcc, exec1911; GFX9-NEXT:    s_cbranch_scc0 .LBB8_21912; GFX9-NEXT:  ; %bb.1: ; %F1913; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off offset:16 glc1914; GFX9-NEXT:    s_waitcnt vmcnt(0)1915; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[2:3], off glc1916; GFX9-NEXT:    s_waitcnt vmcnt(0)1917; GFX9-NEXT:    ; kill: killed $vgpr2 killed $vgpr31918; GFX9-NEXT:    s_cbranch_execz .LBB8_31919; GFX9-NEXT:    s_branch .LBB8_41920; GFX9-NEXT:  .LBB8_2:1921; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr111922; GFX9-NEXT:  .LBB8_3: ; %T1923; GFX9-NEXT:    global_load_dwordx4 v[2:5], v[0:1], off offset:16 glc1924; GFX9-NEXT:    s_waitcnt vmcnt(0)1925; GFX9-NEXT:    global_load_dwordx4 v[4:7], v[0:1], off glc1926; GFX9-NEXT:    s_waitcnt vmcnt(0)1927; GFX9-NEXT:    ; kill: killed $vgpr0 killed $vgpr11928; GFX9-NEXT:  .LBB8_4: ; %exit1929; GFX9-NEXT:    v_mov_b32_e32 v0, 0x38001930; GFX9-NEXT:    v_mov_b32_e32 v1, 0x39001931; GFX9-NEXT:    v_mov_b32_e32 v2, 0x3d001932; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v71933; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v2, vcc1934; GFX9-NEXT:    v_cmp_nle_f16_sdwa vcc, v7, v0 src0_sel:WORD_1 src1_sel:DWORD1935; GFX9-NEXT:    v_cndmask_b32_e32 v7, v2, v1, vcc1936; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v61937; GFX9-NEXT:    v_cndmask_b32_e32 v8, v1, v2, vcc1938; GFX9-NEXT:    v_cmp_le_f16_sdwa vcc, v6, v0 src0_sel:WORD_1 src1_sel:DWORD1939; GFX9-NEXT:    v_cndmask_b32_e32 v6, v1, v2, vcc1940; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v51941; GFX9-NEXT:    v_cndmask_b32_e32 v9, v1, v2, vcc1942; GFX9-NEXT:    v_cmp_le_f16_sdwa vcc, v5, v0 src0_sel:WORD_1 src1_sel:DWORD1943; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v2, vcc1944; GFX9-NEXT:    v_cmp_ge_f16_e32 vcc, 0.5, v41945; GFX9-NEXT:    v_cndmask_b32_e32 v10, v1, v2, vcc1946; GFX9-NEXT:    v_cmp_le_f16_sdwa vcc, v4, v0 src0_sel:WORD_1 src1_sel:DWORD1947; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc1948; GFX9-NEXT:    v_pack_b32_f16 v0, v10, v01949; GFX9-NEXT:    v_pack_b32_f16 v1, v9, v51950; GFX9-NEXT:    v_pack_b32_f16 v2, v8, v61951; GFX9-NEXT:    v_pack_b32_f16 v3, v3, v71952; GFX9-NEXT:    s_setpc_b64 s[30:31]1953;1954; GFX11-TRUE16-LABEL: vec_16xf16_extract_8xf16_0:1955; GFX11-TRUE16:       ; %bb.0:1956; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1957; GFX11-TRUE16-NEXT:    scratch_load_u8 v4, off, s321958; GFX11-TRUE16-NEXT:    s_mov_b32 s0, 01959; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1960; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 1, v41961; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1962; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v41963; GFX11-TRUE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo1964; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB8_21965; GFX11-TRUE16-NEXT:  ; %bb.1: ; %F1966; GFX11-TRUE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc1967; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1968; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc1969; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1970; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s01971; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB8_31972; GFX11-TRUE16-NEXT:    s_branch .LBB8_41973; GFX11-TRUE16-NEXT:  .LBB8_2:1974; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr91975; GFX11-TRUE16-NEXT:  .LBB8_3: ; %T1976; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc1977; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1978; GFX11-TRUE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc1979; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1980; GFX11-TRUE16-NEXT:  .LBB8_4: ; %exit1981; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v5.l1982; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, 0x39001983; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v4.l1984; GFX11-TRUE16-NEXT:    v_cmp_nge_f16_e64 s1, 0.5, v5.h1985; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s2, 0.5, v2.h1986; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s3, 0.5, v3.h1987; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v0.l, 0x3d00, vcc_lo1988; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v0.l, 0x3d00, s01989; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v3.l1990; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s0, 0.5, v2.l1991; GFX11-TRUE16-NEXT:    v_cmp_ge_f16_e64 s34, 0.5, v4.h1992; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v0.l, 0x3d00, s21993; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, 0x3d00, s31994; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.l, 0x3d00, vcc_lo1995; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, 0x3d00, s01996; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.l, 0x3d00, s341997; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, 0x3d00, v0.l, s11998; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)1999; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.h, v1.h2000; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v1.l, v2.l2001; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v5.l, v2.h2002; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)2003; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v3, v4.l, v3.l2004; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2005;2006; GFX11-FAKE16-LABEL: vec_16xf16_extract_8xf16_0:2007; GFX11-FAKE16:       ; %bb.0:2008; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2009; GFX11-FAKE16-NEXT:    scratch_load_u8 v4, off, s322010; GFX11-FAKE16-NEXT:    s_mov_b32 s0, 02011; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)2012; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 1, v42013; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2014; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v42015; GFX11-FAKE16-NEXT:    s_and_b32 s1, vcc_lo, exec_lo2016; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB8_22017; GFX11-FAKE16-NEXT:  ; %bb.1: ; %F2018; GFX11-FAKE16-NEXT:    global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc2019; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)2020; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[2:3], off glc dlc2021; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)2022; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s02023; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB8_32024; GFX11-FAKE16-NEXT:    s_branch .LBB8_42025; GFX11-FAKE16-NEXT:  .LBB8_2:2026; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr92027; GFX11-FAKE16-NEXT:  .LBB8_3: ; %T2028; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc2029; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)2030; GFX11-FAKE16-NEXT:    global_load_b128 v[2:5], v[0:1], off glc dlc2031; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)2032; GFX11-FAKE16-NEXT:  .LBB8_4: ; %exit2033; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v52034; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, 0x39002035; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0x3d002036; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v42037; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v52038; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v22039; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v32040; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, 0x3900, v1, vcc_lo2041; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v42042; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x3900, v1, vcc_lo2043; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v72044; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, 0x3900, v1, vcc_lo2045; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v32046; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x3900, v1, vcc_lo2047; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v22048; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x3900, v1, vcc_lo2049; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v02050; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x3900, v1, vcc_lo2051; GFX11-FAKE16-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0.5, v62052; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)2053; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v2, v02054; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x3900, v1, vcc_lo2055; GFX11-FAKE16-NEXT:    v_cmp_nge_f16_e32 vcc_lo, 0.5, v82056; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v2, v4, v72057; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v12058; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, 0x3d00, v9, vcc_lo2059; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2060; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v3, v5, v62061; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2062  br i1 %cond, label %T, label %F2063 2064T:2065  %t = load volatile <16 x half>, ptr addrspace(1) %p02066  br label %exit2067 2068F:2069  %f = load volatile <16 x half>, ptr addrspace(1) %p12070  br label %exit2071 2072exit:2073  %m = phi <16 x half> [ %t, %T ], [ %f, %F ]2074  %v2 = shufflevector <16 x half> %m, <16 x half> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>2075  %b2 = fcmp ugt <8 x half> %v2, <half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800>2076  %r2 = select <8 x i1> %b2, <8 x half> <half 0xH3900, half 0xH3900, half 0xH3900, half 0xH3900, half 0xH3900, half 0xH3900, half 0xH3900, half 0xH3900>, <8 x half> <half 0xH3D00, half 0xH3D00, half 0xH3D00, half 0xH3D00, half 0xH3D00, half 0xH3D00, half 0xH3D00, half 0xH3D00>2077  ret <8 x half> %r22078}2079