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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s4; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s6 7define amdgpu_kernel void @extract_vector_elt_v2f16(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr) #0 {8; SI-LABEL: extract_vector_elt_v2f16:9; SI: ; %bb.0:10; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x911; SI-NEXT: s_waitcnt lgkmcnt(0)12; SI-NEXT: s_load_dword s4, s[2:3], 0x013; SI-NEXT: s_mov_b32 s3, 0xf00014; SI-NEXT: s_waitcnt lgkmcnt(0)15; SI-NEXT: s_lshr_b32 s5, s4, 1616; SI-NEXT: s_mov_b32 s2, -117; SI-NEXT: v_mov_b32_e32 v0, s418; SI-NEXT: v_mov_b32_e32 v1, s519; SI-NEXT: buffer_store_short v1, off, s[0:3], 020; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:2021; SI-NEXT: s_endpgm22;23; VI-LABEL: extract_vector_elt_v2f16:24; VI: ; %bb.0:25; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2426; VI-NEXT: s_waitcnt lgkmcnt(0)27; VI-NEXT: s_load_dword s4, s[2:3], 0x028; VI-NEXT: s_mov_b32 s3, 0xf00029; VI-NEXT: s_mov_b32 s2, -130; VI-NEXT: s_waitcnt lgkmcnt(0)31; VI-NEXT: s_lshr_b32 s5, s4, 1632; VI-NEXT: v_mov_b32_e32 v1, s533; VI-NEXT: v_mov_b32_e32 v0, s434; VI-NEXT: buffer_store_short v1, off, s[0:3], 035; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:2036; VI-NEXT: s_endpgm37;38; GFX11-LABEL: extract_vector_elt_v2f16:39; GFX11: ; %bb.0:40; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2441; GFX11-NEXT: s_waitcnt lgkmcnt(0)42; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x043; GFX11-NEXT: v_mov_b32_e32 v0, 044; GFX11-NEXT: s_mov_b32 s3, 0x3101600045; GFX11-NEXT: s_waitcnt lgkmcnt(0)46; GFX11-NEXT: v_mov_b32_e32 v1, s247; GFX11-NEXT: s_mov_b32 s2, -148; GFX11-NEXT: s_clause 0x149; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1]50; GFX11-NEXT: buffer_store_b16 v1, off, s[0:3], 0 offset:2051; GFX11-NEXT: s_endpgm52 %vec = load <2 x half>, ptr addrspace(4) %vec.ptr53 %p0 = extractelement <2 x half> %vec, i32 054 %p1 = extractelement <2 x half> %vec, i32 155 %out1 = getelementptr half, ptr addrspace(1) %out, i32 1056 store half %p1, ptr addrspace(1) %out, align 257 store half %p0, ptr addrspace(1) %out1, align 258 ret void59}60 61define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_sgpr(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr, i32 %idx) #0 {62; SI-LABEL: extract_vector_elt_v2f16_dynamic_sgpr:63; SI: ; %bb.0:64; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x965; SI-NEXT: s_load_dword s4, s[4:5], 0xd66; SI-NEXT: s_waitcnt lgkmcnt(0)67; SI-NEXT: s_load_dword s2, s[2:3], 0x068; SI-NEXT: s_mov_b32 s3, 0xf00069; SI-NEXT: s_lshl_b32 s4, s4, 470; SI-NEXT: s_waitcnt lgkmcnt(0)71; SI-NEXT: s_lshr_b32 s4, s2, s472; SI-NEXT: s_mov_b32 s2, -173; SI-NEXT: v_mov_b32_e32 v0, s474; SI-NEXT: buffer_store_short v0, off, s[0:3], 075; SI-NEXT: s_endpgm76;77; VI-LABEL: extract_vector_elt_v2f16_dynamic_sgpr:78; VI: ; %bb.0:79; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2480; VI-NEXT: s_load_dword s8, s[4:5], 0x3481; VI-NEXT: s_mov_b32 s7, 0xf00082; VI-NEXT: s_mov_b32 s6, -183; VI-NEXT: s_waitcnt lgkmcnt(0)84; VI-NEXT: s_load_dword s2, s[2:3], 0x085; VI-NEXT: s_mov_b32 s4, s086; VI-NEXT: s_lshl_b32 s0, s8, 487; VI-NEXT: s_mov_b32 s5, s188; VI-NEXT: s_waitcnt lgkmcnt(0)89; VI-NEXT: s_lshr_b32 s0, s2, s090; VI-NEXT: v_mov_b32_e32 v0, s091; VI-NEXT: buffer_store_short v0, off, s[4:7], 092; VI-NEXT: s_endpgm93;94; GFX11-LABEL: extract_vector_elt_v2f16_dynamic_sgpr:95; GFX11: ; %bb.0:96; GFX11-NEXT: s_clause 0x197; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2498; GFX11-NEXT: s_load_b32 s4, s[4:5], 0x3499; GFX11-NEXT: s_waitcnt lgkmcnt(0)100; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0101; GFX11-NEXT: s_lshl_b32 s3, s4, 4102; GFX11-NEXT: s_waitcnt lgkmcnt(0)103; GFX11-NEXT: s_lshr_b32 s2, s2, s3104; GFX11-NEXT: s_mov_b32 s3, 0x31016000105; GFX11-NEXT: v_mov_b32_e32 v0, s2106; GFX11-NEXT: s_mov_b32 s2, -1107; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0108; GFX11-NEXT: s_endpgm109 %vec = load <2 x half>, ptr addrspace(4) %vec.ptr110 %elt = extractelement <2 x half> %vec, i32 %idx111 store half %elt, ptr addrspace(1) %out, align 2112 ret void113}114 115define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_vgpr(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr, ptr addrspace(1) %idx.ptr) #0 {116; SI-LABEL: extract_vector_elt_v2f16_dynamic_vgpr:117; SI: ; %bb.0:118; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9119; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd120; SI-NEXT: s_mov_b32 s7, 0xf000121; SI-NEXT: s_mov_b32 s6, 0122; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0123; SI-NEXT: v_mov_b32_e32 v2, 0124; SI-NEXT: s_waitcnt lgkmcnt(0)125; SI-NEXT: buffer_load_dword v3, v[1:2], s[4:7], 0 addr64126; SI-NEXT: s_load_dword s2, s[2:3], 0x0127; SI-NEXT: s_mov_b64 s[4:5], s[0:1]128; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v0129; SI-NEXT: s_waitcnt vmcnt(0)130; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v3131; SI-NEXT: s_waitcnt lgkmcnt(0)132; SI-NEXT: v_lshr_b32_e32 v0, s2, v0133; SI-NEXT: buffer_store_short v0, v[1:2], s[4:7], 0 addr64134; SI-NEXT: s_endpgm135;136; VI-LABEL: extract_vector_elt_v2f16_dynamic_vgpr:137; VI: ; %bb.0:138; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34139; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0140; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0141; VI-NEXT: s_waitcnt lgkmcnt(0)142; VI-NEXT: v_mov_b32_e32 v2, s1143; VI-NEXT: v_add_u32_e32 v1, vcc, s0, v1144; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc145; VI-NEXT: flat_load_dword v2, v[1:2]146; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24147; VI-NEXT: s_waitcnt lgkmcnt(0)148; VI-NEXT: v_mov_b32_e32 v1, s1149; VI-NEXT: s_load_dword s1, s[2:3], 0x0150; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0151; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc152; VI-NEXT: s_waitcnt vmcnt(0)153; VI-NEXT: v_lshlrev_b32_e32 v2, 4, v2154; VI-NEXT: s_waitcnt lgkmcnt(0)155; VI-NEXT: v_lshrrev_b32_e64 v2, v2, s1156; VI-NEXT: flat_store_short v[0:1], v2157; VI-NEXT: s_endpgm158;159; GFX11-LABEL: extract_vector_elt_v2f16_dynamic_vgpr:160; GFX11: ; %bb.0:161; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x34162; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0163; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)164; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v0165; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0166; GFX11-NEXT: s_waitcnt lgkmcnt(0)167; GFX11-NEXT: global_load_b32 v1, v1, s[0:1]168; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24169; GFX11-NEXT: s_waitcnt lgkmcnt(0)170; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0171; GFX11-NEXT: s_waitcnt vmcnt(0)172; GFX11-NEXT: v_lshlrev_b32_e32 v1, 4, v1173; GFX11-NEXT: s_waitcnt lgkmcnt(0)174; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)175; GFX11-NEXT: v_lshrrev_b32_e64 v1, v1, s2176; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]177; GFX11-NEXT: s_endpgm178 %tid = call i32 @llvm.amdgcn.workitem.id.x()179 %tid.ext = sext i32 %tid to i64180 %gep = getelementptr inbounds i32, ptr addrspace(1) %idx.ptr, i64 %tid.ext181 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext182 %vec = load <2 x half>, ptr addrspace(4) %vec.ptr183 %idx = load i32, ptr addrspace(1) %gep184 %elt = extractelement <2 x half> %vec, i32 %idx185 store half %elt, ptr addrspace(1) %out.gep, align 2186 ret void187}188 189define amdgpu_kernel void @extract_vector_elt_v3f16(ptr addrspace(1) %out, <3 x half> %foo) #0 {190; SI-LABEL: extract_vector_elt_v3f16:191; SI: ; %bb.0:192; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9193; SI-NEXT: s_mov_b32 s7, 0xf000194; SI-NEXT: s_mov_b32 s6, -1195; SI-NEXT: s_waitcnt lgkmcnt(0)196; SI-NEXT: s_mov_b32 s4, s0197; SI-NEXT: s_mov_b32 s5, s1198; SI-NEXT: v_mov_b32_e32 v0, s3199; SI-NEXT: buffer_store_short v0, off, s[4:7], 0200; SI-NEXT: s_waitcnt expcnt(0)201; SI-NEXT: v_mov_b32_e32 v0, s2202; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:2203; SI-NEXT: s_endpgm204;205; VI-LABEL: extract_vector_elt_v3f16:206; VI: ; %bb.0:207; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24208; VI-NEXT: s_mov_b32 s7, 0xf000209; VI-NEXT: s_mov_b32 s6, -1210; VI-NEXT: s_waitcnt lgkmcnt(0)211; VI-NEXT: s_mov_b32 s4, s0212; VI-NEXT: s_mov_b32 s5, s1213; VI-NEXT: v_mov_b32_e32 v0, s3214; VI-NEXT: buffer_store_short v0, off, s[4:7], 0215; VI-NEXT: v_mov_b32_e32 v0, s2216; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:2217; VI-NEXT: s_endpgm218;219; GFX11-LABEL: extract_vector_elt_v3f16:220; GFX11: ; %bb.0:221; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24222; GFX11-NEXT: s_mov_b32 s7, 0x31016000223; GFX11-NEXT: s_mov_b32 s6, -1224; GFX11-NEXT: s_waitcnt lgkmcnt(0)225; GFX11-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2226; GFX11-NEXT: s_mov_b32 s4, s0227; GFX11-NEXT: s_mov_b32 s5, s1228; GFX11-NEXT: s_clause 0x1229; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0230; GFX11-NEXT: buffer_store_b16 v1, off, s[4:7], 0 offset:2231; GFX11-NEXT: s_endpgm232 %p0 = extractelement <3 x half> %foo, i32 0233 %p1 = extractelement <3 x half> %foo, i32 2234 %out1 = getelementptr half, ptr addrspace(1) %out, i32 1235 store half %p1, ptr addrspace(1) %out, align 2236 store half %p0, ptr addrspace(1) %out1, align 2237 ret void238}239 240; FIXME: Why sometimes vector shift?241define amdgpu_kernel void @dynamic_extract_vector_elt_v3f16(ptr addrspace(1) %out, <3 x half> %foo, i32 %idx) #0 {242; SI-LABEL: dynamic_extract_vector_elt_v3f16:243; SI: ; %bb.0:244; SI-NEXT: s_load_dword s6, s[4:5], 0xd245; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9246; SI-NEXT: s_mov_b32 s7, 0xf000247; SI-NEXT: s_waitcnt lgkmcnt(0)248; SI-NEXT: s_lshl_b32 s4, s6, 4249; SI-NEXT: s_lshr_b64 s[2:3], s[2:3], s4250; SI-NEXT: s_mov_b32 s6, -1251; SI-NEXT: s_mov_b32 s4, s0252; SI-NEXT: s_mov_b32 s5, s1253; SI-NEXT: v_mov_b32_e32 v0, s2254; SI-NEXT: buffer_store_short v0, off, s[4:7], 0255; SI-NEXT: s_endpgm256;257; VI-LABEL: dynamic_extract_vector_elt_v3f16:258; VI: ; %bb.0:259; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24260; VI-NEXT: s_load_dword s8, s[4:5], 0x34261; VI-NEXT: s_mov_b32 s7, 0xf000262; VI-NEXT: s_mov_b32 s6, -1263; VI-NEXT: s_waitcnt lgkmcnt(0)264; VI-NEXT: s_mov_b32 s4, s0265; VI-NEXT: s_lshl_b32 s0, s8, 4266; VI-NEXT: s_mov_b32 s5, s1267; VI-NEXT: s_lshr_b64 s[0:1], s[2:3], s0268; VI-NEXT: v_mov_b32_e32 v0, s0269; VI-NEXT: buffer_store_short v0, off, s[4:7], 0270; VI-NEXT: s_endpgm271;272; GFX11-LABEL: dynamic_extract_vector_elt_v3f16:273; GFX11: ; %bb.0:274; GFX11-NEXT: s_clause 0x1275; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x34276; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24277; GFX11-NEXT: s_waitcnt lgkmcnt(0)278; GFX11-NEXT: s_lshl_b32 s4, s6, 4279; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)280; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s4281; GFX11-NEXT: s_mov_b32 s3, 0x31016000282; GFX11-NEXT: v_mov_b32_e32 v0, s2283; GFX11-NEXT: s_mov_b32 s2, -1284; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0285; GFX11-NEXT: s_endpgm286 %p0 = extractelement <3 x half> %foo, i32 %idx287 %out1 = getelementptr half, ptr addrspace(1) %out, i32 1288 store half %p0, ptr addrspace(1) %out289 ret void290}291 292define amdgpu_kernel void @v_extractelement_v4f16_2(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {293; SI-LABEL: v_extractelement_v4f16_2:294; SI: ; %bb.0:295; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9296; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v0297; SI-NEXT: s_mov_b32 s7, 0xf000298; SI-NEXT: s_mov_b32 s6, 0299; SI-NEXT: v_mov_b32_e32 v2, 0300; SI-NEXT: s_mov_b64 s[10:11], s[6:7]301; SI-NEXT: s_waitcnt lgkmcnt(0)302; SI-NEXT: s_mov_b64 s[8:9], s[2:3]303; SI-NEXT: buffer_load_dword v3, v[1:2], s[8:11], 0 addr64 offset:4304; SI-NEXT: s_mov_b64 s[4:5], s[0:1]305; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v0306; SI-NEXT: s_waitcnt vmcnt(0)307; SI-NEXT: buffer_store_short v3, v[1:2], s[4:7], 0 addr64308; SI-NEXT: s_endpgm309;310; VI-LABEL: v_extractelement_v4f16_2:311; VI: ; %bb.0:312; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24313; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0314; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0315; VI-NEXT: s_waitcnt lgkmcnt(0)316; VI-NEXT: v_mov_b32_e32 v2, s3317; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v1318; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc319; VI-NEXT: v_add_u32_e32 v1, vcc, 4, v1320; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc321; VI-NEXT: flat_load_dword v2, v[1:2]322; VI-NEXT: v_mov_b32_e32 v1, s1323; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0324; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc325; VI-NEXT: s_waitcnt vmcnt(0)326; VI-NEXT: flat_store_short v[0:1], v2327; VI-NEXT: s_endpgm328;329; GFX11-LABEL: v_extractelement_v4f16_2:330; GFX11: ; %bb.0:331; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24332; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0333; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)334; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0335; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0336; GFX11-NEXT: s_waitcnt lgkmcnt(0)337; GFX11-NEXT: global_load_b32 v1, v1, s[2:3] offset:4338; GFX11-NEXT: s_waitcnt vmcnt(0)339; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]340; GFX11-NEXT: s_endpgm341 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1342 %tid.ext = sext i32 %tid to i64343 %in.gep = getelementptr inbounds <4 x half>, ptr addrspace(1) %in, i64 %tid.ext344 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext345 %vec = load <4 x half>, ptr addrspace(1) %in.gep346 %vec.extract = extractelement <4 x half> %vec, i32 2347 store half %vec.extract, ptr addrspace(1) %out.gep348 ret void349}350 351define amdgpu_kernel void @v_insertelement_v4f16_dynamic_vgpr(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {352; SI-LABEL: v_insertelement_v4f16_dynamic_vgpr:353; SI: ; %bb.0:354; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9355; SI-NEXT: s_mov_b32 s6, 0356; SI-NEXT: s_mov_b32 s7, 0xf000357; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v0358; SI-NEXT: v_mov_b32_e32 v2, 0359; SI-NEXT: s_mov_b32 s10, -1360; SI-NEXT: s_mov_b32 s11, s7361; SI-NEXT: buffer_load_dword v5, off, s[8:11], 0 glc362; SI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)363; SI-NEXT: s_mov_b64 s[4:5], s[2:3]364; SI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64365; SI-NEXT: s_mov_b64 s[2:3], s[6:7]366; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v0367; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v5368; SI-NEXT: s_waitcnt vmcnt(0)369; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], v0370; SI-NEXT: buffer_store_short v3, v[1:2], s[0:3], 0 addr64371; SI-NEXT: s_endpgm372;373; VI-LABEL: v_insertelement_v4f16_dynamic_vgpr:374; VI: ; %bb.0:375; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24376; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0377; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v0378; VI-NEXT: s_waitcnt lgkmcnt(0)379; VI-NEXT: v_mov_b32_e32 v2, s3380; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v1381; VI-NEXT: s_mov_b32 s3, 0xf000382; VI-NEXT: s_mov_b32 s2, -1383; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc384; VI-NEXT: buffer_load_dword v3, off, s[0:3], 0 glc385; VI-NEXT: s_waitcnt vmcnt(0)386; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2]387; VI-NEXT: v_mov_b32_e32 v5, s1388; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v3389; VI-NEXT: s_waitcnt vmcnt(0)390; VI-NEXT: v_lshrrev_b64 v[0:1], v0, v[1:2]391; VI-NEXT: v_add_u32_e32 v1, vcc, s0, v4392; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc393; VI-NEXT: flat_store_short v[1:2], v0394; VI-NEXT: s_endpgm395;396; GFX11-LABEL: v_insertelement_v4f16_dynamic_vgpr:397; GFX11: ; %bb.0:398; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24399; GFX11-NEXT: v_and_b32_e32 v2, 0x3ff, v0400; GFX11-NEXT: s_mov_b32 s7, 0x31016000401; GFX11-NEXT: s_mov_b32 s6, -1402; GFX11-NEXT: buffer_load_b32 v3, off, s[4:7], 0 glc dlc403; GFX11-NEXT: s_waitcnt vmcnt(0)404; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v2405; GFX11-NEXT: s_waitcnt lgkmcnt(0)406; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3]407; GFX11-NEXT: v_lshlrev_b32_e32 v3, 4, v3408; GFX11-NEXT: s_waitcnt vmcnt(0)409; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)410; GFX11-NEXT: v_lshrrev_b64 v[0:1], v3, v[0:1]411; GFX11-NEXT: v_lshlrev_b32_e32 v1, 1, v2412; GFX11-NEXT: global_store_b16 v1, v0, s[0:1]413; GFX11-NEXT: s_endpgm414 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1415 %tid.ext = sext i32 %tid to i64416 %in.gep = getelementptr inbounds <4 x half>, ptr addrspace(1) %in, i64 %tid.ext417 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext418 %idx.val = load volatile i32, ptr addrspace(1) poison419 %vec = load <4 x half>, ptr addrspace(1) %in.gep420 %vec.extract = extractelement <4 x half> %vec, i32 %idx.val421 store half %vec.extract, ptr addrspace(1) %out.gep422 ret void423}424 425define amdgpu_kernel void @reduce_load_vector_v8f16_extract_01(ptr addrspace(4) %ptr) #0 {426; SI-LABEL: reduce_load_vector_v8f16_extract_01:427; SI: ; %bb.0:428; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9429; SI-NEXT: s_waitcnt lgkmcnt(0)430; SI-NEXT: s_load_dword s0, s[0:1], 0x0431; SI-NEXT: s_mov_b32 s3, 0xf000432; SI-NEXT: s_mov_b32 s2, -1433; SI-NEXT: s_waitcnt lgkmcnt(0)434; SI-NEXT: s_lshr_b32 s1, s0, 16435; SI-NEXT: v_mov_b32_e32 v0, s0436; SI-NEXT: buffer_store_short v0, off, s[0:3], 0437; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)438; SI-NEXT: v_mov_b32_e32 v0, s1439; SI-NEXT: buffer_store_short v0, off, s[0:3], 0440; SI-NEXT: s_waitcnt vmcnt(0)441; SI-NEXT: s_endpgm442;443; VI-LABEL: reduce_load_vector_v8f16_extract_01:444; VI: ; %bb.0:445; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24446; VI-NEXT: s_mov_b32 s3, 0xf000447; VI-NEXT: s_mov_b32 s2, -1448; VI-NEXT: s_waitcnt lgkmcnt(0)449; VI-NEXT: s_load_dword s0, s[0:1], 0x0450; VI-NEXT: s_waitcnt lgkmcnt(0)451; VI-NEXT: s_lshr_b32 s1, s0, 16452; VI-NEXT: v_mov_b32_e32 v0, s0453; VI-NEXT: buffer_store_short v0, off, s[0:3], 0454; VI-NEXT: s_waitcnt vmcnt(0)455; VI-NEXT: v_mov_b32_e32 v0, s1456; VI-NEXT: buffer_store_short v0, off, s[0:3], 0457; VI-NEXT: s_waitcnt vmcnt(0)458; VI-NEXT: s_endpgm459;460; GFX11-LABEL: reduce_load_vector_v8f16_extract_01:461; GFX11: ; %bb.0:462; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24463; GFX11-NEXT: s_mov_b32 s3, 0x31016000464; GFX11-NEXT: s_mov_b32 s2, -1465; GFX11-NEXT: s_waitcnt lgkmcnt(0)466; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0467; GFX11-NEXT: s_waitcnt lgkmcnt(0)468; GFX11-NEXT: s_lshr_b32 s1, s0, 16469; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)470; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1471; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 dlc472; GFX11-NEXT: s_waitcnt_vscnt null, 0x0473; GFX11-NEXT: buffer_store_b16 v1, off, s[0:3], 0 dlc474; GFX11-NEXT: s_waitcnt_vscnt null, 0x0475; GFX11-NEXT: s_endpgm476 %load = load <16 x half>, ptr addrspace(4) %ptr477 %elt0 = extractelement <16 x half> %load, i32 0478 %elt1 = extractelement <16 x half> %load, i32 1479 store volatile half %elt0, ptr addrspace(1) poison, align 2480 store volatile half %elt1, ptr addrspace(1) poison, align 2481 ret void482}483 484define amdgpu_kernel void @reduce_load_vector_v8f16_extract_23(ptr addrspace(4) %ptr) #0 {485; SI-LABEL: reduce_load_vector_v8f16_extract_23:486; SI: ; %bb.0:487; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9488; SI-NEXT: s_waitcnt lgkmcnt(0)489; SI-NEXT: s_load_dword s0, s[0:1], 0x1490; SI-NEXT: s_mov_b32 s3, 0xf000491; SI-NEXT: s_mov_b32 s2, -1492; SI-NEXT: s_waitcnt lgkmcnt(0)493; SI-NEXT: s_lshr_b32 s1, s0, 16494; SI-NEXT: v_mov_b32_e32 v0, s0495; SI-NEXT: buffer_store_short v0, off, s[0:3], 0496; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)497; SI-NEXT: v_mov_b32_e32 v0, s1498; SI-NEXT: buffer_store_short v0, off, s[0:3], 0499; SI-NEXT: s_waitcnt vmcnt(0)500; SI-NEXT: s_endpgm501;502; VI-LABEL: reduce_load_vector_v8f16_extract_23:503; VI: ; %bb.0:504; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24505; VI-NEXT: s_mov_b32 s3, 0xf000506; VI-NEXT: s_mov_b32 s2, -1507; VI-NEXT: s_waitcnt lgkmcnt(0)508; VI-NEXT: s_load_dword s0, s[0:1], 0x4509; VI-NEXT: s_waitcnt lgkmcnt(0)510; VI-NEXT: s_lshr_b32 s1, s0, 16511; VI-NEXT: v_mov_b32_e32 v0, s0512; VI-NEXT: buffer_store_short v0, off, s[0:3], 0513; VI-NEXT: s_waitcnt vmcnt(0)514; VI-NEXT: v_mov_b32_e32 v0, s1515; VI-NEXT: buffer_store_short v0, off, s[0:3], 0516; VI-NEXT: s_waitcnt vmcnt(0)517; VI-NEXT: s_endpgm518;519; GFX11-LABEL: reduce_load_vector_v8f16_extract_23:520; GFX11: ; %bb.0:521; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24522; GFX11-NEXT: s_mov_b32 s3, 0x31016000523; GFX11-NEXT: s_mov_b32 s2, -1524; GFX11-NEXT: s_waitcnt lgkmcnt(0)525; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x4526; GFX11-NEXT: s_waitcnt lgkmcnt(0)527; GFX11-NEXT: s_lshr_b32 s1, s0, 16528; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)529; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1530; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 dlc531; GFX11-NEXT: s_waitcnt_vscnt null, 0x0532; GFX11-NEXT: buffer_store_b16 v1, off, s[0:3], 0 dlc533; GFX11-NEXT: s_waitcnt_vscnt null, 0x0534; GFX11-NEXT: s_endpgm535 %load = load <16 x half>, ptr addrspace(4) %ptr536 %elt2 = extractelement <16 x half> %load, i32 2537 %elt3 = extractelement <16 x half> %load, i32 3538 store volatile half %elt2, ptr addrspace(1) poison, align 2539 store volatile half %elt3, ptr addrspace(1) poison, align 2540 ret void541}542 543define amdgpu_kernel void @v_extractelement_v8f16_dynamic_sgpr(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %n) #0 {544; SI-LABEL: v_extractelement_v8f16_dynamic_sgpr:545; SI: ; %bb.0:546; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9547; SI-NEXT: s_load_dword s8, s[4:5], 0xd548; SI-NEXT: s_mov_b32 s7, 0xf000549; SI-NEXT: s_mov_b32 s6, 0550; SI-NEXT: v_lshlrev_b32_e32 v4, 4, v0551; SI-NEXT: v_mov_b32_e32 v5, 0552; SI-NEXT: s_waitcnt lgkmcnt(0)553; SI-NEXT: s_mov_b64 s[4:5], s[2:3]554; SI-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[4:7], 0 addr64555; SI-NEXT: v_lshlrev_b32_e32 v6, 1, v0556; SI-NEXT: v_mov_b32_e32 v7, v5557; SI-NEXT: s_mov_b64 s[2:3], s[6:7]558; SI-NEXT: s_cmp_eq_u32 s8, 1559; SI-NEXT: s_waitcnt vmcnt(0)560; SI-NEXT: v_cvt_f32_f16_e32 v0, v1561; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1562; SI-NEXT: v_cvt_f32_f16_e32 v5, v2563; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2564; SI-NEXT: v_cvt_f32_f16_e32 v8, v3565; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3566; SI-NEXT: v_cvt_f32_f16_e32 v9, v4567; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4568; SI-NEXT: v_cvt_f32_f16_e32 v1, v1569; SI-NEXT: s_cselect_b64 vcc, -1, 0570; SI-NEXT: s_cmp_eq_u32 s8, 2571; SI-NEXT: v_cvt_f32_f16_e32 v2, v2572; SI-NEXT: v_cvt_f32_f16_e32 v3, v3573; SI-NEXT: v_cvt_f32_f16_e32 v4, v4574; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc575; SI-NEXT: s_cselect_b64 vcc, -1, 0576; SI-NEXT: s_cmp_eq_u32 s8, 3577; SI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc578; SI-NEXT: s_cselect_b64 vcc, -1, 0579; SI-NEXT: s_cmp_eq_u32 s8, 4580; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc581; SI-NEXT: s_cselect_b64 vcc, -1, 0582; SI-NEXT: s_cmp_eq_u32 s8, 5583; SI-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc584; SI-NEXT: s_cselect_b64 vcc, -1, 0585; SI-NEXT: s_cmp_eq_u32 s8, 6586; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc587; SI-NEXT: s_cselect_b64 vcc, -1, 0588; SI-NEXT: s_cmp_eq_u32 s8, 7589; SI-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc590; SI-NEXT: s_cselect_b64 vcc, -1, 0591; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc592; SI-NEXT: v_cvt_f16_f32_e32 v0, v0593; SI-NEXT: buffer_store_short v0, v[6:7], s[0:3], 0 addr64594; SI-NEXT: s_endpgm595;596; VI-LABEL: v_extractelement_v8f16_dynamic_sgpr:597; VI: ; %bb.0:598; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24599; VI-NEXT: s_load_dword s4, s[4:5], 0x34600; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v0601; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0602; VI-NEXT: s_waitcnt lgkmcnt(0)603; VI-NEXT: v_mov_b32_e32 v2, s3604; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v1605; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc606; VI-NEXT: flat_load_dwordx4 v[1:4], v[1:2]607; VI-NEXT: v_mov_b32_e32 v6, s1608; VI-NEXT: v_add_u32_e32 v5, vcc, s0, v0609; VI-NEXT: s_cmp_eq_u32 s4, 1610; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc611; VI-NEXT: s_cselect_b64 vcc, -1, 0612; VI-NEXT: s_cmp_eq_u32 s4, 2613; VI-NEXT: s_waitcnt vmcnt(0)614; VI-NEXT: v_cndmask_b32_sdwa v0, v1, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1615; VI-NEXT: s_cselect_b64 vcc, -1, 0616; VI-NEXT: s_cmp_eq_u32 s4, 3617; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc618; VI-NEXT: s_cselect_b64 vcc, -1, 0619; VI-NEXT: s_cmp_eq_u32 s4, 4620; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1621; VI-NEXT: s_cselect_b64 vcc, -1, 0622; VI-NEXT: s_cmp_eq_u32 s4, 5623; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc624; VI-NEXT: s_cselect_b64 vcc, -1, 0625; VI-NEXT: s_cmp_eq_u32 s4, 6626; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1627; VI-NEXT: s_cselect_b64 vcc, -1, 0628; VI-NEXT: s_cmp_eq_u32 s4, 7629; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc630; VI-NEXT: s_cselect_b64 vcc, -1, 0631; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1632; VI-NEXT: flat_store_short v[5:6], v0633; VI-NEXT: s_endpgm634;635; GFX11-TRUE16-LABEL: v_extractelement_v8f16_dynamic_sgpr:636; GFX11-TRUE16: ; %bb.0:637; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24638; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x3ff, v0639; GFX11-TRUE16-NEXT: s_load_b32 s4, s[4:5], 0x34640; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)641; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 4, v4642; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)643; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v0, s[2:3]644; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 1645; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0646; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 2647; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)648; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, s2649; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0650; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 3651; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)652; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2653; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0654; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 4655; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.h, s2656; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0657; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 5658; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 1, v4659; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)660; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2661; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0662; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 6663; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.h, s2664; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0665; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 7666; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)667; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2668; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0669; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)670; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.h, s2671; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]672; GFX11-TRUE16-NEXT: s_endpgm673;674; GFX11-FAKE16-LABEL: v_extractelement_v8f16_dynamic_sgpr:675; GFX11-FAKE16: ; %bb.0:676; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24677; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x3ff, v0678; GFX11-FAKE16-NEXT: s_load_b32 s4, s[4:5], 0x34679; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)680; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 4, v4681; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)682; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v0, s[2:3]683; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 1684; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0685; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 2686; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)687; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0688; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)689; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo690; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0691; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1692; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 3693; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo694; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0695; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 4696; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2697; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)698; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo699; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0700; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 5701; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo702; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0703; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 6704; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 1, v4705; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)706; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo707; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0708; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3709; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 7710; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo711; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0712; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)713; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo714; GFX11-FAKE16-NEXT: global_store_b16 v2, v0, s[0:1]715; GFX11-FAKE16-NEXT: s_endpgm716 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1717 %tid.ext = sext i32 %tid to i64718 %in.gep = getelementptr inbounds <8 x half>, ptr addrspace(1) %in, i64 %tid.ext719 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext720 %vec = load <8 x half>, ptr addrspace(1) %in.gep721 %vec.extract = extractelement <8 x half> %vec, i32 %n722 store half %vec.extract, ptr addrspace(1) %out.gep723 ret void724}725 726define amdgpu_kernel void @v_extractelement_v16f16_dynamic_sgpr(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %n) #0 {727; SI-LABEL: v_extractelement_v16f16_dynamic_sgpr:728; SI: ; %bb.0:729; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9730; SI-NEXT: s_load_dword s8, s[4:5], 0xd731; SI-NEXT: s_mov_b32 s7, 0xf000732; SI-NEXT: s_mov_b32 s6, 0733; SI-NEXT: v_lshlrev_b32_e32 v8, 5, v0734; SI-NEXT: v_mov_b32_e32 v9, 0735; SI-NEXT: s_waitcnt lgkmcnt(0)736; SI-NEXT: s_mov_b64 s[4:5], s[2:3]737; SI-NEXT: buffer_load_dwordx4 v[1:4], v[8:9], s[4:7], 0 addr64738; SI-NEXT: buffer_load_dwordx4 v[5:8], v[8:9], s[4:7], 0 addr64 offset:16739; SI-NEXT: s_waitcnt vmcnt(1)740; SI-NEXT: v_cvt_f32_f16_e32 v10, v1741; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1742; SI-NEXT: v_cvt_f32_f16_e32 v11, v2743; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2744; SI-NEXT: v_cvt_f32_f16_e32 v12, v3745; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3746; SI-NEXT: v_cvt_f32_f16_e32 v13, v4747; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4748; SI-NEXT: s_waitcnt vmcnt(0)749; SI-NEXT: v_cvt_f32_f16_e32 v14, v5750; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5751; SI-NEXT: v_cvt_f32_f16_e32 v15, v6752; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6753; SI-NEXT: v_cvt_f32_f16_e32 v16, v7754; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7755; SI-NEXT: v_cvt_f32_f16_e32 v17, v8756; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v8757; SI-NEXT: v_lshlrev_b32_e32 v8, 1, v0758; SI-NEXT: s_mov_b64 s[2:3], s[6:7]759; SI-NEXT: s_cmp_eq_u32 s8, 1760; SI-NEXT: v_cvt_f32_f16_e32 v0, v1761; SI-NEXT: s_cselect_b64 vcc, -1, 0762; SI-NEXT: s_cmp_eq_u32 s8, 2763; SI-NEXT: v_cvt_f32_f16_e32 v1, v2764; SI-NEXT: v_cvt_f32_f16_e32 v2, v3765; SI-NEXT: v_cvt_f32_f16_e32 v3, v4766; SI-NEXT: v_cvt_f32_f16_e32 v4, v5767; SI-NEXT: v_cvt_f32_f16_e32 v5, v6768; SI-NEXT: v_cvt_f32_f16_e32 v6, v7769; SI-NEXT: v_cvt_f32_f16_e32 v7, v18770; SI-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc771; SI-NEXT: s_cselect_b64 vcc, -1, 0772; SI-NEXT: s_cmp_eq_u32 s8, 3773; SI-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc774; SI-NEXT: s_cselect_b64 vcc, -1, 0775; SI-NEXT: s_cmp_eq_u32 s8, 4776; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc777; SI-NEXT: s_cselect_b64 vcc, -1, 0778; SI-NEXT: s_cmp_eq_u32 s8, 5779; SI-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc780; SI-NEXT: s_cselect_b64 vcc, -1, 0781; SI-NEXT: s_cmp_eq_u32 s8, 6782; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc783; SI-NEXT: s_cselect_b64 vcc, -1, 0784; SI-NEXT: s_cmp_eq_u32 s8, 7785; SI-NEXT: v_cndmask_b32_e32 v0, v0, v13, vcc786; SI-NEXT: s_cselect_b64 vcc, -1, 0787; SI-NEXT: s_cmp_eq_u32 s8, 8788; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc789; SI-NEXT: s_cselect_b64 vcc, -1, 0790; SI-NEXT: s_cmp_eq_u32 s8, 9791; SI-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc792; SI-NEXT: s_cselect_b64 vcc, -1, 0793; SI-NEXT: s_cmp_eq_u32 s8, 10794; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc795; SI-NEXT: s_cselect_b64 vcc, -1, 0796; SI-NEXT: s_cmp_eq_u32 s8, 11797; SI-NEXT: v_cndmask_b32_e32 v0, v0, v15, vcc798; SI-NEXT: s_cselect_b64 vcc, -1, 0799; SI-NEXT: s_cmp_eq_u32 s8, 12800; SI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc801; SI-NEXT: s_cselect_b64 vcc, -1, 0802; SI-NEXT: s_cmp_eq_u32 s8, 13803; SI-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc804; SI-NEXT: s_cselect_b64 vcc, -1, 0805; SI-NEXT: s_cmp_eq_u32 s8, 14806; SI-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc807; SI-NEXT: s_cselect_b64 vcc, -1, 0808; SI-NEXT: s_cmp_eq_u32 s8, 15809; SI-NEXT: v_cndmask_b32_e32 v0, v0, v17, vcc810; SI-NEXT: s_cselect_b64 vcc, -1, 0811; SI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc812; SI-NEXT: v_cvt_f16_f32_e32 v0, v0813; SI-NEXT: buffer_store_short v0, v[8:9], s[0:3], 0 addr64814; SI-NEXT: s_endpgm815;816; VI-LABEL: v_extractelement_v16f16_dynamic_sgpr:817; VI: ; %bb.0:818; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24819; VI-NEXT: s_load_dword s4, s[4:5], 0x34820; VI-NEXT: v_lshlrev_b32_e32 v1, 5, v0821; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0822; VI-NEXT: s_waitcnt lgkmcnt(0)823; VI-NEXT: v_mov_b32_e32 v2, s3824; VI-NEXT: v_add_u32_e32 v5, vcc, s2, v1825; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v2, vcc826; VI-NEXT: flat_load_dwordx4 v[1:4], v[5:6]827; VI-NEXT: v_add_u32_e32 v5, vcc, 16, v5828; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc829; VI-NEXT: flat_load_dwordx4 v[5:8], v[5:6]830; VI-NEXT: v_mov_b32_e32 v10, s1831; VI-NEXT: v_add_u32_e32 v9, vcc, s0, v0832; VI-NEXT: s_cmp_eq_u32 s4, 1833; VI-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc834; VI-NEXT: s_cselect_b64 vcc, -1, 0835; VI-NEXT: s_cmp_eq_u32 s4, 2836; VI-NEXT: s_waitcnt vmcnt(1)837; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v1838; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc839; VI-NEXT: s_cselect_b64 vcc, -1, 0840; VI-NEXT: s_cmp_eq_u32 s4, 3841; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v2842; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc843; VI-NEXT: s_cselect_b64 vcc, -1, 0844; VI-NEXT: s_cmp_eq_u32 s4, 4845; VI-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc846; VI-NEXT: s_cselect_b64 vcc, -1, 0847; VI-NEXT: s_cmp_eq_u32 s4, 5848; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v3849; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc850; VI-NEXT: s_cselect_b64 vcc, -1, 0851; VI-NEXT: s_cmp_eq_u32 s4, 6852; VI-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc853; VI-NEXT: s_cselect_b64 vcc, -1, 0854; VI-NEXT: s_cmp_eq_u32 s4, 7855; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v4856; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc857; VI-NEXT: s_cselect_b64 vcc, -1, 0858; VI-NEXT: s_cmp_eq_u32 s4, 8859; VI-NEXT: v_cndmask_b32_e32 v0, v0, v13, vcc860; VI-NEXT: s_cselect_b64 vcc, -1, 0861; VI-NEXT: s_cmp_eq_u32 s4, 9862; VI-NEXT: s_waitcnt vmcnt(0)863; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc864; VI-NEXT: s_cselect_b64 vcc, -1, 0865; VI-NEXT: s_cmp_eq_u32 s4, 10866; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v5, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1867; VI-NEXT: s_cselect_b64 vcc, -1, 0868; VI-NEXT: s_cmp_eq_u32 s4, 11869; VI-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc870; VI-NEXT: s_cselect_b64 vcc, -1, 0871; VI-NEXT: s_cmp_eq_u32 s4, 12872; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v6, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1873; VI-NEXT: s_cselect_b64 vcc, -1, 0874; VI-NEXT: s_cmp_eq_u32 s4, 13875; VI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc876; VI-NEXT: s_cselect_b64 vcc, -1, 0877; VI-NEXT: s_cmp_eq_u32 s4, 14878; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v7, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1879; VI-NEXT: s_cselect_b64 vcc, -1, 0880; VI-NEXT: s_cmp_eq_u32 s4, 15881; VI-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc882; VI-NEXT: s_cselect_b64 vcc, -1, 0883; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v8, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1884; VI-NEXT: flat_store_short v[9:10], v0885; VI-NEXT: s_endpgm886;887; GFX11-TRUE16-LABEL: v_extractelement_v16f16_dynamic_sgpr:888; GFX11-TRUE16: ; %bb.0:889; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24890; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x3ff, v0891; GFX11-TRUE16-NEXT: s_load_b32 s4, s[4:5], 0x34892; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)893; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 5, v8894; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)895; GFX11-TRUE16-NEXT: s_clause 0x1896; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v4, s[2:3]897; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v4, s[2:3] offset:16898; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 1899; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0900; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 2901; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)902; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, s2903; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0904; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 3905; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)906; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2907; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0908; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 4909; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.h, s2910; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0911; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 5912; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 1, v8913; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)914; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2915; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0916; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 6917; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.h, s2918; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0919; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 7920; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)921; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2922; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0923; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 8924; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.h, s2925; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0926; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 9927; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)928; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)929; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s2930; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0931; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 10932; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.h, s2933; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0934; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 11935; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)936; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v5.l, s2937; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0938; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 12939; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v5.h, s2940; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0941; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 13942; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)943; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v6.l, s2944; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0945; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 14946; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v6.h, s2947; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0948; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 15949; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)950; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v7.l, s2951; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0952; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)953; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v7.h, s2954; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]955; GFX11-TRUE16-NEXT: s_endpgm956;957; GFX11-FAKE16-LABEL: v_extractelement_v16f16_dynamic_sgpr:958; GFX11-FAKE16: ; %bb.0:959; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24960; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x3ff, v0961; GFX11-FAKE16-NEXT: s_load_b32 s4, s[4:5], 0x34962; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)963; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 5, v8964; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)965; GFX11-FAKE16-NEXT: s_clause 0x1966; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v4, s[2:3]967; GFX11-FAKE16-NEXT: global_load_b128 v[4:7], v4, s[2:3] offset:16968; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 1969; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0970; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 2971; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)972; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0973; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)974; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo975; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0976; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1977; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 3978; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo979; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0980; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 4981; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2982; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)983; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo984; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0985; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 5986; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo987; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0988; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 6989; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 1, v8990; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)991; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo992; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0993; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3994; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 7995; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo996; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0997; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 8998; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)999; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo1000; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01001; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)1002; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v41003; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 91004; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo1005; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01006; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 101007; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)1008; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo1009; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01010; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v51011; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 111012; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo1013; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01014; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 121015; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)1016; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo1017; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01018; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v61019; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 131020; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo1021; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01022; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 141023; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)1024; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo1025; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01026; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v71027; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 151028; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo1029; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 01030; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1031; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo1032; GFX11-FAKE16-NEXT: global_store_b16 v2, v0, s[0:1]1033; GFX11-FAKE16-NEXT: s_endpgm1034 %tid = call i32 @llvm.amdgcn.workitem.id.x() #11035 %tid.ext = sext i32 %tid to i641036 %in.gep = getelementptr inbounds <16 x half>, ptr addrspace(1) %in, i64 %tid.ext1037 %out.gep = getelementptr inbounds half, ptr addrspace(1) %out, i64 %tid.ext1038 %vec = load <16 x half>, ptr addrspace(1) %in.gep1039 %vec.extract = extractelement <16 x half> %vec, i32 %n1040 store half %vec.extract, ptr addrspace(1) %out.gep1041 ret void1042}1043 1044declare i32 @llvm.amdgcn.workitem.id.x() #11045 1046attributes #0 = { nounwind }1047attributes #1 = { nounwind readnone }1048