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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s4 5define amdgpu_kernel void @extract_vector_elt_v1i8(ptr addrspace(1) %out, <1 x i8> %foo) #0 {6; SI-LABEL: extract_vector_elt_v1i8:7; SI: ; %bb.0:8; SI-NEXT: s_mov_b32 flat_scratch_lo, s139; SI-NEXT: s_add_i32 s12, s12, s1710; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 811; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x012; SI-NEXT: s_load_dword s2, s[8:9], 0x213; SI-NEXT: s_waitcnt lgkmcnt(0)14; SI-NEXT: v_mov_b32_e32 v0, s015; SI-NEXT: v_mov_b32_e32 v1, s116; SI-NEXT: v_mov_b32_e32 v2, s217; SI-NEXT: flat_store_byte v[0:1], v218; SI-NEXT: s_endpgm19;20; VI-LABEL: extract_vector_elt_v1i8:21; VI: ; %bb.0:22; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x023; VI-NEXT: s_load_dword s2, s[8:9], 0x824; VI-NEXT: s_add_i32 s12, s12, s1725; VI-NEXT: s_mov_b32 flat_scratch_lo, s1326; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 827; VI-NEXT: s_waitcnt lgkmcnt(0)28; VI-NEXT: v_mov_b32_e32 v0, s029; VI-NEXT: v_mov_b32_e32 v1, s130; VI-NEXT: v_mov_b32_e32 v2, s231; VI-NEXT: flat_store_byte v[0:1], v232; VI-NEXT: s_endpgm33 %p0 = extractelement <1 x i8> %foo, i32 034 store i8 %p0, ptr addrspace(1) %out35 ret void36}37 38define amdgpu_kernel void @extract_vector_elt_v2i8(ptr addrspace(1) %out, <2 x i8> %foo) #0 {39; SI-LABEL: extract_vector_elt_v2i8:40; SI: ; %bb.0:41; SI-NEXT: s_mov_b32 flat_scratch_lo, s1342; SI-NEXT: s_add_i32 s12, s12, s1743; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 844; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x045; SI-NEXT: s_load_dword s2, s[8:9], 0x246; SI-NEXT: s_waitcnt lgkmcnt(0)47; SI-NEXT: s_lshr_b32 s3, s2, 848; SI-NEXT: v_mov_b32_e32 v0, s049; SI-NEXT: v_mov_b32_e32 v1, s150; SI-NEXT: v_mov_b32_e32 v2, s251; SI-NEXT: s_add_u32 s0, s0, 152; SI-NEXT: v_mov_b32_e32 v3, s353; SI-NEXT: s_addc_u32 s1, s1, 054; SI-NEXT: flat_store_byte v[0:1], v355; SI-NEXT: s_waitcnt vmcnt(0)56; SI-NEXT: v_mov_b32_e32 v0, s057; SI-NEXT: v_mov_b32_e32 v1, s158; SI-NEXT: flat_store_byte v[0:1], v259; SI-NEXT: s_waitcnt vmcnt(0)60; SI-NEXT: s_endpgm61;62; VI-LABEL: extract_vector_elt_v2i8:63; VI: ; %bb.0:64; VI-NEXT: s_load_dword s2, s[8:9], 0x865; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x066; VI-NEXT: s_add_i32 s12, s12, s1767; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 868; VI-NEXT: s_mov_b32 flat_scratch_lo, s1369; VI-NEXT: s_waitcnt lgkmcnt(0)70; VI-NEXT: s_lshr_b32 s3, s2, 871; VI-NEXT: v_mov_b32_e32 v0, s072; VI-NEXT: v_mov_b32_e32 v1, s173; VI-NEXT: s_add_u32 s0, s0, 174; VI-NEXT: v_mov_b32_e32 v2, s375; VI-NEXT: s_addc_u32 s1, s1, 076; VI-NEXT: flat_store_byte v[0:1], v277; VI-NEXT: s_waitcnt vmcnt(0)78; VI-NEXT: v_mov_b32_e32 v0, s079; VI-NEXT: v_mov_b32_e32 v1, s180; VI-NEXT: v_mov_b32_e32 v2, s281; VI-NEXT: flat_store_byte v[0:1], v282; VI-NEXT: s_waitcnt vmcnt(0)83; VI-NEXT: s_endpgm84 %p0 = extractelement <2 x i8> %foo, i32 085 %p1 = extractelement <2 x i8> %foo, i32 186 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 187 store volatile i8 %p1, ptr addrspace(1) %out88 store volatile i8 %p0, ptr addrspace(1) %out189 ret void90}91 92define amdgpu_kernel void @extract_vector_elt_v3i8(ptr addrspace(1) %out, <3 x i8> %foo) #0 {93; SI-LABEL: extract_vector_elt_v3i8:94; SI: ; %bb.0:95; SI-NEXT: s_mov_b32 flat_scratch_lo, s1396; SI-NEXT: s_add_i32 s12, s12, s1797; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 898; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x099; SI-NEXT: s_load_dword s2, s[8:9], 0x2100; SI-NEXT: s_waitcnt lgkmcnt(0)101; SI-NEXT: s_lshr_b32 s3, s2, 16102; SI-NEXT: v_mov_b32_e32 v0, s0103; SI-NEXT: v_mov_b32_e32 v1, s1104; SI-NEXT: v_mov_b32_e32 v2, s2105; SI-NEXT: s_add_u32 s0, s0, 1106; SI-NEXT: v_mov_b32_e32 v3, s3107; SI-NEXT: s_addc_u32 s1, s1, 0108; SI-NEXT: flat_store_byte v[0:1], v3109; SI-NEXT: s_waitcnt vmcnt(0)110; SI-NEXT: v_mov_b32_e32 v0, s0111; SI-NEXT: v_mov_b32_e32 v1, s1112; SI-NEXT: flat_store_byte v[0:1], v2113; SI-NEXT: s_waitcnt vmcnt(0)114; SI-NEXT: s_endpgm115;116; VI-LABEL: extract_vector_elt_v3i8:117; VI: ; %bb.0:118; VI-NEXT: s_load_dword s2, s[8:9], 0x8119; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0120; VI-NEXT: s_add_i32 s12, s12, s17121; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8122; VI-NEXT: s_mov_b32 flat_scratch_lo, s13123; VI-NEXT: s_waitcnt lgkmcnt(0)124; VI-NEXT: s_lshr_b32 s3, s2, 16125; VI-NEXT: v_mov_b32_e32 v0, s0126; VI-NEXT: v_mov_b32_e32 v1, s1127; VI-NEXT: s_add_u32 s0, s0, 1128; VI-NEXT: v_mov_b32_e32 v2, s3129; VI-NEXT: s_addc_u32 s1, s1, 0130; VI-NEXT: flat_store_byte v[0:1], v2131; VI-NEXT: s_waitcnt vmcnt(0)132; VI-NEXT: v_mov_b32_e32 v0, s0133; VI-NEXT: v_mov_b32_e32 v1, s1134; VI-NEXT: v_mov_b32_e32 v2, s2135; VI-NEXT: flat_store_byte v[0:1], v2136; VI-NEXT: s_waitcnt vmcnt(0)137; VI-NEXT: s_endpgm138 %p0 = extractelement <3 x i8> %foo, i32 0139 %p1 = extractelement <3 x i8> %foo, i32 2140 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 1141 store volatile i8 %p1, ptr addrspace(1) %out142 store volatile i8 %p0, ptr addrspace(1) %out1143 ret void144}145 146define amdgpu_kernel void @extract_vector_elt_v4i8(ptr addrspace(1) %out, <4 x i8> %foo) #0 {147; SI-LABEL: extract_vector_elt_v4i8:148; SI: ; %bb.0:149; SI-NEXT: s_mov_b32 flat_scratch_lo, s13150; SI-NEXT: s_add_i32 s12, s12, s17151; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8152; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0153; SI-NEXT: s_load_dword s2, s[8:9], 0x2154; SI-NEXT: s_waitcnt lgkmcnt(0)155; SI-NEXT: s_lshr_b32 s3, s2, 16156; SI-NEXT: v_mov_b32_e32 v0, s0157; SI-NEXT: v_mov_b32_e32 v1, s1158; SI-NEXT: v_mov_b32_e32 v2, s2159; SI-NEXT: s_add_u32 s0, s0, 1160; SI-NEXT: v_mov_b32_e32 v3, s3161; SI-NEXT: s_addc_u32 s1, s1, 0162; SI-NEXT: flat_store_byte v[0:1], v3163; SI-NEXT: s_waitcnt vmcnt(0)164; SI-NEXT: v_mov_b32_e32 v0, s0165; SI-NEXT: v_mov_b32_e32 v1, s1166; SI-NEXT: flat_store_byte v[0:1], v2167; SI-NEXT: s_waitcnt vmcnt(0)168; SI-NEXT: s_endpgm169;170; VI-LABEL: extract_vector_elt_v4i8:171; VI: ; %bb.0:172; VI-NEXT: s_load_dword s2, s[8:9], 0x8173; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0174; VI-NEXT: s_add_i32 s12, s12, s17175; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8176; VI-NEXT: s_mov_b32 flat_scratch_lo, s13177; VI-NEXT: s_waitcnt lgkmcnt(0)178; VI-NEXT: s_lshr_b32 s3, s2, 16179; VI-NEXT: v_mov_b32_e32 v0, s0180; VI-NEXT: v_mov_b32_e32 v1, s1181; VI-NEXT: s_add_u32 s0, s0, 1182; VI-NEXT: v_mov_b32_e32 v2, s3183; VI-NEXT: s_addc_u32 s1, s1, 0184; VI-NEXT: flat_store_byte v[0:1], v2185; VI-NEXT: s_waitcnt vmcnt(0)186; VI-NEXT: v_mov_b32_e32 v0, s0187; VI-NEXT: v_mov_b32_e32 v1, s1188; VI-NEXT: v_mov_b32_e32 v2, s2189; VI-NEXT: flat_store_byte v[0:1], v2190; VI-NEXT: s_waitcnt vmcnt(0)191; VI-NEXT: s_endpgm192 %p0 = extractelement <4 x i8> %foo, i32 0193 %p1 = extractelement <4 x i8> %foo, i32 2194 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 1195 store volatile i8 %p1, ptr addrspace(1) %out196 store volatile i8 %p0, ptr addrspace(1) %out1197 ret void198}199 200define amdgpu_kernel void @extract_vector_elt_v8i8(<8 x i8> %foo) #0 {201; SI-LABEL: extract_vector_elt_v8i8:202; SI: ; %bb.0:203; SI-NEXT: s_mov_b32 flat_scratch_lo, s13204; SI-NEXT: s_add_i32 s12, s12, s17205; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8206; SI-NEXT: s_load_dword s0, s[8:9], 0x0207; SI-NEXT: s_waitcnt lgkmcnt(0)208; SI-NEXT: s_lshr_b32 s1, s0, 16209; SI-NEXT: v_mov_b32_e32 v0, 0210; SI-NEXT: v_mov_b32_e32 v1, 0211; SI-NEXT: v_mov_b32_e32 v2, s0212; SI-NEXT: v_mov_b32_e32 v3, s1213; SI-NEXT: flat_store_byte v[0:1], v3214; SI-NEXT: s_waitcnt vmcnt(0)215; SI-NEXT: flat_store_byte v[0:1], v2216; SI-NEXT: s_waitcnt vmcnt(0)217; SI-NEXT: s_endpgm218;219; VI-LABEL: extract_vector_elt_v8i8:220; VI: ; %bb.0:221; VI-NEXT: s_load_dword s0, s[8:9], 0x0222; VI-NEXT: s_add_i32 s12, s12, s17223; VI-NEXT: v_mov_b32_e32 v0, 0224; VI-NEXT: s_mov_b32 flat_scratch_lo, s13225; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8226; VI-NEXT: s_waitcnt lgkmcnt(0)227; VI-NEXT: s_lshr_b32 s1, s0, 16228; VI-NEXT: v_mov_b32_e32 v1, 0229; VI-NEXT: v_mov_b32_e32 v3, s1230; VI-NEXT: v_mov_b32_e32 v2, s0231; VI-NEXT: flat_store_byte v[0:1], v3232; VI-NEXT: s_waitcnt vmcnt(0)233; VI-NEXT: flat_store_byte v[0:1], v2234; VI-NEXT: s_waitcnt vmcnt(0)235; VI-NEXT: s_endpgm236 %p0 = extractelement <8 x i8> %foo, i32 0237 %p1 = extractelement <8 x i8> %foo, i32 2238 store volatile i8 %p1, ptr addrspace(1) null239 store volatile i8 %p0, ptr addrspace(1) null240 ret void241}242 243define amdgpu_kernel void @extract_vector_elt_v16i8(ptr addrspace(1) %out, <16 x i8> %foo) #0 {244; SI-LABEL: extract_vector_elt_v16i8:245; SI: ; %bb.0:246; SI-NEXT: s_mov_b32 flat_scratch_lo, s13247; SI-NEXT: s_add_i32 s12, s12, s17248; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8249; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0250; SI-NEXT: s_load_dword s2, s[8:9], 0x4251; SI-NEXT: s_waitcnt lgkmcnt(0)252; SI-NEXT: s_lshr_b32 s3, s2, 16253; SI-NEXT: v_mov_b32_e32 v0, s0254; SI-NEXT: v_mov_b32_e32 v1, s1255; SI-NEXT: v_mov_b32_e32 v2, s2256; SI-NEXT: s_add_u32 s0, s0, 1257; SI-NEXT: v_mov_b32_e32 v3, s3258; SI-NEXT: s_addc_u32 s1, s1, 0259; SI-NEXT: flat_store_byte v[0:1], v3260; SI-NEXT: s_waitcnt vmcnt(0)261; SI-NEXT: v_mov_b32_e32 v0, s0262; SI-NEXT: v_mov_b32_e32 v1, s1263; SI-NEXT: flat_store_byte v[0:1], v2264; SI-NEXT: s_waitcnt vmcnt(0)265; SI-NEXT: s_endpgm266;267; VI-LABEL: extract_vector_elt_v16i8:268; VI: ; %bb.0:269; VI-NEXT: s_load_dword s2, s[8:9], 0x10270; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0271; VI-NEXT: s_add_i32 s12, s12, s17272; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8273; VI-NEXT: s_mov_b32 flat_scratch_lo, s13274; VI-NEXT: s_waitcnt lgkmcnt(0)275; VI-NEXT: s_lshr_b32 s3, s2, 16276; VI-NEXT: v_mov_b32_e32 v0, s0277; VI-NEXT: v_mov_b32_e32 v1, s1278; VI-NEXT: s_add_u32 s0, s0, 1279; VI-NEXT: v_mov_b32_e32 v2, s3280; VI-NEXT: s_addc_u32 s1, s1, 0281; VI-NEXT: flat_store_byte v[0:1], v2282; VI-NEXT: s_waitcnt vmcnt(0)283; VI-NEXT: v_mov_b32_e32 v0, s0284; VI-NEXT: v_mov_b32_e32 v1, s1285; VI-NEXT: v_mov_b32_e32 v2, s2286; VI-NEXT: flat_store_byte v[0:1], v2287; VI-NEXT: s_waitcnt vmcnt(0)288; VI-NEXT: s_endpgm289 %p0 = extractelement <16 x i8> %foo, i32 0290 %p1 = extractelement <16 x i8> %foo, i32 2291 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 1292 store volatile i8 %p1, ptr addrspace(1) %out293 store volatile i8 %p0, ptr addrspace(1) %out1294 ret void295}296 297define amdgpu_kernel void @extract_vector_elt_v32i8(<32 x i8> %foo) #0 {298; SI-LABEL: extract_vector_elt_v32i8:299; SI: ; %bb.0:300; SI-NEXT: s_mov_b32 flat_scratch_lo, s13301; SI-NEXT: s_add_i32 s12, s12, s17302; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8303; SI-NEXT: s_load_dword s0, s[8:9], 0x0304; SI-NEXT: s_waitcnt lgkmcnt(0)305; SI-NEXT: s_lshr_b32 s1, s0, 16306; SI-NEXT: v_mov_b32_e32 v0, 0307; SI-NEXT: v_mov_b32_e32 v1, 0308; SI-NEXT: v_mov_b32_e32 v2, s0309; SI-NEXT: v_mov_b32_e32 v3, s1310; SI-NEXT: flat_store_byte v[0:1], v3311; SI-NEXT: s_waitcnt vmcnt(0)312; SI-NEXT: flat_store_byte v[0:1], v2313; SI-NEXT: s_waitcnt vmcnt(0)314; SI-NEXT: s_endpgm315;316; VI-LABEL: extract_vector_elt_v32i8:317; VI: ; %bb.0:318; VI-NEXT: s_load_dword s0, s[8:9], 0x0319; VI-NEXT: s_add_i32 s12, s12, s17320; VI-NEXT: v_mov_b32_e32 v0, 0321; VI-NEXT: s_mov_b32 flat_scratch_lo, s13322; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8323; VI-NEXT: s_waitcnt lgkmcnt(0)324; VI-NEXT: s_lshr_b32 s1, s0, 16325; VI-NEXT: v_mov_b32_e32 v1, 0326; VI-NEXT: v_mov_b32_e32 v3, s1327; VI-NEXT: v_mov_b32_e32 v2, s0328; VI-NEXT: flat_store_byte v[0:1], v3329; VI-NEXT: s_waitcnt vmcnt(0)330; VI-NEXT: flat_store_byte v[0:1], v2331; VI-NEXT: s_waitcnt vmcnt(0)332; VI-NEXT: s_endpgm333 %p0 = extractelement <32 x i8> %foo, i32 0334 %p1 = extractelement <32 x i8> %foo, i32 2335 store volatile i8 %p1, ptr addrspace(1) null336 store volatile i8 %p0, ptr addrspace(1) null337 ret void338}339 340define amdgpu_kernel void @extract_vector_elt_v64i8(ptr addrspace(1) %out, <64 x i8> %foo) #0 {341; SI-LABEL: extract_vector_elt_v64i8:342; SI: ; %bb.0:343; SI-NEXT: s_mov_b32 flat_scratch_lo, s13344; SI-NEXT: s_add_i32 s12, s12, s17345; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8346; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0347; SI-NEXT: s_load_dword s2, s[8:9], 0x10348; SI-NEXT: s_waitcnt lgkmcnt(0)349; SI-NEXT: s_lshr_b32 s3, s2, 16350; SI-NEXT: v_mov_b32_e32 v0, s0351; SI-NEXT: v_mov_b32_e32 v1, s1352; SI-NEXT: v_mov_b32_e32 v2, s2353; SI-NEXT: s_add_u32 s0, s0, 1354; SI-NEXT: v_mov_b32_e32 v3, s3355; SI-NEXT: s_addc_u32 s1, s1, 0356; SI-NEXT: flat_store_byte v[0:1], v3357; SI-NEXT: s_waitcnt vmcnt(0)358; SI-NEXT: v_mov_b32_e32 v0, s0359; SI-NEXT: v_mov_b32_e32 v1, s1360; SI-NEXT: flat_store_byte v[0:1], v2361; SI-NEXT: s_waitcnt vmcnt(0)362; SI-NEXT: s_endpgm363;364; VI-LABEL: extract_vector_elt_v64i8:365; VI: ; %bb.0:366; VI-NEXT: s_load_dword s2, s[8:9], 0x40367; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0368; VI-NEXT: s_add_i32 s12, s12, s17369; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8370; VI-NEXT: s_mov_b32 flat_scratch_lo, s13371; VI-NEXT: s_waitcnt lgkmcnt(0)372; VI-NEXT: s_lshr_b32 s3, s2, 16373; VI-NEXT: v_mov_b32_e32 v0, s0374; VI-NEXT: v_mov_b32_e32 v1, s1375; VI-NEXT: s_add_u32 s0, s0, 1376; VI-NEXT: v_mov_b32_e32 v2, s3377; VI-NEXT: s_addc_u32 s1, s1, 0378; VI-NEXT: flat_store_byte v[0:1], v2379; VI-NEXT: s_waitcnt vmcnt(0)380; VI-NEXT: v_mov_b32_e32 v0, s0381; VI-NEXT: v_mov_b32_e32 v1, s1382; VI-NEXT: v_mov_b32_e32 v2, s2383; VI-NEXT: flat_store_byte v[0:1], v2384; VI-NEXT: s_waitcnt vmcnt(0)385; VI-NEXT: s_endpgm386 %p0 = extractelement <64 x i8> %foo, i32 0387 %p1 = extractelement <64 x i8> %foo, i32 2388 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 1389 store volatile i8 %p1, ptr addrspace(1) %out390 store volatile i8 %p0, ptr addrspace(1) %out1391 ret void392}393 394; FIXME: SI generates much worse code from that's a pain to match395 396; FIXME: 16-bit and 32-bit shift not combined after legalize to to397; isTypeDesirableForOp in SimplifyDemandedBits398 399define amdgpu_kernel void @dynamic_extract_vector_elt_v2i8(ptr addrspace(1) %out, [8 x i32], <2 x i8> %foo, [8 x i32], i32 %idx) #0 {400; SI-LABEL: dynamic_extract_vector_elt_v2i8:401; SI: ; %bb.0:402; SI-NEXT: s_mov_b32 flat_scratch_lo, s13403; SI-NEXT: s_add_i32 s12, s12, s17404; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8405; SI-NEXT: s_load_dword s2, s[8:9], 0xa406; SI-NEXT: s_load_dword s3, s[8:9], 0x13407; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0408; SI-NEXT: s_waitcnt lgkmcnt(0)409; SI-NEXT: s_and_b32 s2, s2, 0xffff410; SI-NEXT: s_lshl_b32 s3, s3, 3411; SI-NEXT: s_lshr_b32 s2, s2, s3412; SI-NEXT: v_mov_b32_e32 v0, s0413; SI-NEXT: v_mov_b32_e32 v1, s1414; SI-NEXT: v_mov_b32_e32 v2, s2415; SI-NEXT: flat_store_byte v[0:1], v2416; SI-NEXT: s_waitcnt vmcnt(0)417; SI-NEXT: s_endpgm418;419; VI-LABEL: dynamic_extract_vector_elt_v2i8:420; VI: ; %bb.0:421; VI-NEXT: s_load_dword s2, s[8:9], 0x4c422; VI-NEXT: s_load_dword s3, s[8:9], 0x28423; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0424; VI-NEXT: s_add_i32 s12, s12, s17425; VI-NEXT: s_mov_b32 flat_scratch_lo, s13426; VI-NEXT: s_waitcnt lgkmcnt(0)427; VI-NEXT: s_lshl_b32 s2, s2, 3428; VI-NEXT: s_and_b32 s3, s3, 0xffff429; VI-NEXT: s_lshr_b32 s2, s3, s2430; VI-NEXT: v_mov_b32_e32 v0, s0431; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8432; VI-NEXT: v_mov_b32_e32 v1, s1433; VI-NEXT: v_mov_b32_e32 v2, s2434; VI-NEXT: flat_store_byte v[0:1], v2435; VI-NEXT: s_waitcnt vmcnt(0)436; VI-NEXT: s_endpgm437 %elt = extractelement <2 x i8> %foo, i32 %idx438 store volatile i8 %elt, ptr addrspace(1) %out439 ret void440}441 442define amdgpu_kernel void @dynamic_extract_vector_elt_v3i8(ptr addrspace(1) %out, [8 x i32], <3 x i8> %foo, [8 x i32], i32 %idx) #0 {443; SI-LABEL: dynamic_extract_vector_elt_v3i8:444; SI: ; %bb.0:445; SI-NEXT: s_mov_b32 flat_scratch_lo, s13446; SI-NEXT: s_add_i32 s12, s12, s17447; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8448; SI-NEXT: s_load_dword s2, s[8:9], 0x13449; SI-NEXT: s_load_dword s3, s[8:9], 0xa450; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0451; SI-NEXT: s_waitcnt lgkmcnt(0)452; SI-NEXT: s_lshl_b32 s2, s2, 3453; SI-NEXT: s_lshr_b32 s2, s3, s2454; SI-NEXT: v_mov_b32_e32 v0, s0455; SI-NEXT: v_mov_b32_e32 v1, s1456; SI-NEXT: v_mov_b32_e32 v2, s2457; SI-NEXT: flat_store_byte v[0:1], v2458; SI-NEXT: s_waitcnt vmcnt(0)459; SI-NEXT: s_endpgm460;461; VI-LABEL: dynamic_extract_vector_elt_v3i8:462; VI: ; %bb.0:463; VI-NEXT: s_load_dword s2, s[8:9], 0x4c464; VI-NEXT: s_load_dword s3, s[8:9], 0x28465; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0466; VI-NEXT: s_add_i32 s12, s12, s17467; VI-NEXT: s_mov_b32 flat_scratch_lo, s13468; VI-NEXT: s_waitcnt lgkmcnt(0)469; VI-NEXT: s_lshl_b32 s2, s2, 3470; VI-NEXT: s_lshr_b32 s2, s3, s2471; VI-NEXT: v_mov_b32_e32 v0, s0472; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8473; VI-NEXT: v_mov_b32_e32 v1, s1474; VI-NEXT: v_mov_b32_e32 v2, s2475; VI-NEXT: flat_store_byte v[0:1], v2476; VI-NEXT: s_waitcnt vmcnt(0)477; VI-NEXT: s_endpgm478 %p0 = extractelement <3 x i8> %foo, i32 %idx479 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 1480 store volatile i8 %p0, ptr addrspace(1) %out481 ret void482}483 484define amdgpu_kernel void @dynamic_extract_vector_elt_v4i8(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr, [8 x i32], i32 %idx) #0 {485; SI-LABEL: dynamic_extract_vector_elt_v4i8:486; SI: ; %bb.0:487; SI-NEXT: s_mov_b32 flat_scratch_lo, s13488; SI-NEXT: s_add_i32 s12, s12, s17489; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8490; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0491; SI-NEXT: s_load_dword s4, s[8:9], 0xc492; SI-NEXT: s_waitcnt lgkmcnt(0)493; SI-NEXT: s_load_dword s2, s[2:3], 0x0494; SI-NEXT: s_lshl_b32 s3, s4, 3495; SI-NEXT: s_waitcnt lgkmcnt(0)496; SI-NEXT: s_lshr_b32 s2, s2, s3497; SI-NEXT: v_mov_b32_e32 v0, s0498; SI-NEXT: v_mov_b32_e32 v1, s1499; SI-NEXT: v_mov_b32_e32 v2, s2500; SI-NEXT: flat_store_byte v[0:1], v2501; SI-NEXT: s_waitcnt vmcnt(0)502; SI-NEXT: s_endpgm503;504; VI-LABEL: dynamic_extract_vector_elt_v4i8:505; VI: ; %bb.0:506; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0507; VI-NEXT: s_load_dword s4, s[8:9], 0x30508; VI-NEXT: s_add_i32 s12, s12, s17509; VI-NEXT: s_mov_b32 flat_scratch_lo, s13510; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8511; VI-NEXT: s_waitcnt lgkmcnt(0)512; VI-NEXT: s_load_dword s2, s[2:3], 0x0513; VI-NEXT: v_mov_b32_e32 v0, s0514; VI-NEXT: s_lshl_b32 s0, s4, 3515; VI-NEXT: v_mov_b32_e32 v1, s1516; VI-NEXT: s_waitcnt lgkmcnt(0)517; VI-NEXT: s_lshr_b32 s0, s2, s0518; VI-NEXT: v_mov_b32_e32 v2, s0519; VI-NEXT: flat_store_byte v[0:1], v2520; VI-NEXT: s_waitcnt vmcnt(0)521; VI-NEXT: s_endpgm522 %vec = load <4 x i8>, ptr addrspace(4) %vec.ptr523 %p0 = extractelement <4 x i8> %vec, i32 %idx524 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 1525 store volatile i8 %p0, ptr addrspace(1) %out526 ret void527}528 529define amdgpu_kernel void @dynamic_extract_vector_elt_v8i8(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr, i32 %idx) #0 {530; SI-LABEL: dynamic_extract_vector_elt_v8i8:531; SI: ; %bb.0:532; SI-NEXT: s_mov_b32 flat_scratch_lo, s13533; SI-NEXT: s_add_i32 s12, s12, s17534; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8535; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0536; SI-NEXT: s_load_dword s4, s[8:9], 0x4537; SI-NEXT: s_waitcnt lgkmcnt(0)538; SI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0539; SI-NEXT: s_lshl_b32 s4, s4, 3540; SI-NEXT: s_waitcnt lgkmcnt(0)541; SI-NEXT: s_lshr_b64 s[2:3], s[2:3], s4542; SI-NEXT: v_mov_b32_e32 v0, s0543; SI-NEXT: v_mov_b32_e32 v1, s1544; SI-NEXT: v_mov_b32_e32 v2, s2545; SI-NEXT: flat_store_byte v[0:1], v2546; SI-NEXT: s_waitcnt vmcnt(0)547; SI-NEXT: s_endpgm548;549; VI-LABEL: dynamic_extract_vector_elt_v8i8:550; VI: ; %bb.0:551; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0552; VI-NEXT: s_load_dword s4, s[8:9], 0x10553; VI-NEXT: s_add_i32 s12, s12, s17554; VI-NEXT: s_mov_b32 flat_scratch_lo, s13555; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8556; VI-NEXT: s_waitcnt lgkmcnt(0)557; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0558; VI-NEXT: v_mov_b32_e32 v0, s0559; VI-NEXT: s_lshl_b32 s0, s4, 3560; VI-NEXT: v_mov_b32_e32 v1, s1561; VI-NEXT: s_waitcnt lgkmcnt(0)562; VI-NEXT: s_lshr_b64 s[0:1], s[2:3], s0563; VI-NEXT: v_mov_b32_e32 v2, s0564; VI-NEXT: flat_store_byte v[0:1], v2565; VI-NEXT: s_waitcnt vmcnt(0)566; VI-NEXT: s_endpgm567 %vec = load <8 x i8>, ptr addrspace(4) %vec.ptr568 %p0 = extractelement <8 x i8> %vec, i32 %idx569 %out1 = getelementptr i8, ptr addrspace(1) %out, i32 1570 store volatile i8 %p0, ptr addrspace(1) %out571 ret void572}573 574define amdgpu_kernel void @reduce_load_vector_v8i8_extract_0123() #0 {575; SI-LABEL: reduce_load_vector_v8i8_extract_0123:576; SI: ; %bb.0:577; SI-NEXT: s_mov_b32 flat_scratch_lo, s13578; SI-NEXT: s_add_i32 s12, s12, s17579; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8580; SI-NEXT: s_mov_b64 s[0:1], 0581; SI-NEXT: s_load_dword s0, s[0:1], 0x0582; SI-NEXT: s_waitcnt lgkmcnt(0)583; SI-NEXT: s_lshr_b32 s1, s0, 8584; SI-NEXT: s_lshr_b32 s2, s0, 16585; SI-NEXT: s_lshr_b32 s3, s0, 24586; SI-NEXT: v_mov_b32_e32 v0, s0587; SI-NEXT: flat_store_byte v[0:1], v0588; SI-NEXT: s_waitcnt vmcnt(0)589; SI-NEXT: v_mov_b32_e32 v0, s1590; SI-NEXT: flat_store_byte v[0:1], v0591; SI-NEXT: s_waitcnt vmcnt(0)592; SI-NEXT: v_mov_b32_e32 v0, s2593; SI-NEXT: flat_store_byte v[0:1], v0594; SI-NEXT: s_waitcnt vmcnt(0)595; SI-NEXT: v_mov_b32_e32 v0, s3596; SI-NEXT: flat_store_byte v[0:1], v0597; SI-NEXT: s_waitcnt vmcnt(0)598; SI-NEXT: s_endpgm599;600; VI-LABEL: reduce_load_vector_v8i8_extract_0123:601; VI: ; %bb.0:602; VI-NEXT: s_mov_b64 s[0:1], 0603; VI-NEXT: s_load_dword s0, s[0:1], 0x0604; VI-NEXT: s_add_i32 s12, s12, s17605; VI-NEXT: s_mov_b32 flat_scratch_lo, s13606; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8607; VI-NEXT: s_waitcnt lgkmcnt(0)608; VI-NEXT: s_lshr_b32 s1, s0, 8609; VI-NEXT: v_mov_b32_e32 v0, s0610; VI-NEXT: s_lshr_b32 s2, s0, 16611; VI-NEXT: flat_store_byte v[0:1], v0612; VI-NEXT: s_waitcnt vmcnt(0)613; VI-NEXT: v_mov_b32_e32 v0, s1614; VI-NEXT: s_lshr_b32 s3, s0, 24615; VI-NEXT: flat_store_byte v[0:1], v0616; VI-NEXT: s_waitcnt vmcnt(0)617; VI-NEXT: v_mov_b32_e32 v0, s2618; VI-NEXT: flat_store_byte v[0:1], v0619; VI-NEXT: s_waitcnt vmcnt(0)620; VI-NEXT: v_mov_b32_e32 v0, s3621; VI-NEXT: flat_store_byte v[0:1], v0622; VI-NEXT: s_waitcnt vmcnt(0)623; VI-NEXT: s_endpgm624 %load = load <8 x i8>, ptr addrspace(4) null625 %elt0 = extractelement <8 x i8> %load, i32 0626 %elt1 = extractelement <8 x i8> %load, i32 1627 %elt2 = extractelement <8 x i8> %load, i32 2628 %elt3 = extractelement <8 x i8> %load, i32 3629 store volatile i8 %elt0, ptr addrspace(1) poison, align 1630 store volatile i8 %elt1, ptr addrspace(1) poison, align 1631 store volatile i8 %elt2, ptr addrspace(1) poison, align 1632 store volatile i8 %elt3, ptr addrspace(1) poison, align 1633 ret void634}635 636define amdgpu_kernel void @reduce_load_vector_v8i8_extract_0145() #0 {637; SI-LABEL: reduce_load_vector_v8i8_extract_0145:638; SI: ; %bb.0:639; SI-NEXT: s_mov_b32 flat_scratch_lo, s13640; SI-NEXT: s_add_i32 s12, s12, s17641; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8642; SI-NEXT: s_mov_b64 s[0:1], 0643; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0644; SI-NEXT: s_waitcnt lgkmcnt(0)645; SI-NEXT: s_lshr_b32 s2, s0, 8646; SI-NEXT: s_lshr_b32 s3, s1, 8647; SI-NEXT: v_mov_b32_e32 v0, s0648; SI-NEXT: flat_store_byte v[0:1], v0649; SI-NEXT: s_waitcnt vmcnt(0)650; SI-NEXT: v_mov_b32_e32 v0, s1651; SI-NEXT: v_mov_b32_e32 v1, s2652; SI-NEXT: flat_store_byte v[0:1], v1653; SI-NEXT: s_waitcnt vmcnt(0)654; SI-NEXT: flat_store_byte v[0:1], v0655; SI-NEXT: s_waitcnt vmcnt(0)656; SI-NEXT: v_mov_b32_e32 v0, s3657; SI-NEXT: flat_store_byte v[0:1], v0658; SI-NEXT: s_waitcnt vmcnt(0)659; SI-NEXT: s_endpgm660;661; VI-LABEL: reduce_load_vector_v8i8_extract_0145:662; VI: ; %bb.0:663; VI-NEXT: s_mov_b64 s[0:1], 0664; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0665; VI-NEXT: s_add_i32 s12, s12, s17666; VI-NEXT: s_mov_b32 flat_scratch_lo, s13667; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8668; VI-NEXT: s_waitcnt lgkmcnt(0)669; VI-NEXT: s_lshr_b32 s2, s0, 8670; VI-NEXT: v_mov_b32_e32 v0, s0671; VI-NEXT: v_mov_b32_e32 v1, s1672; VI-NEXT: s_lshr_b32 s3, s1, 8673; VI-NEXT: flat_store_byte v[0:1], v0674; VI-NEXT: s_waitcnt vmcnt(0)675; VI-NEXT: v_mov_b32_e32 v0, s2676; VI-NEXT: flat_store_byte v[0:1], v0677; VI-NEXT: s_waitcnt vmcnt(0)678; VI-NEXT: flat_store_byte v[0:1], v1679; VI-NEXT: s_waitcnt vmcnt(0)680; VI-NEXT: v_mov_b32_e32 v0, s3681; VI-NEXT: flat_store_byte v[0:1], v0682; VI-NEXT: s_waitcnt vmcnt(0)683; VI-NEXT: s_endpgm684 %load = load <8 x i8>, ptr addrspace(4) null685 %elt0 = extractelement <8 x i8> %load, i32 0686 %elt1 = extractelement <8 x i8> %load, i32 1687 %elt4 = extractelement <8 x i8> %load, i32 4688 %elt5 = extractelement <8 x i8> %load, i32 5689 store volatile i8 %elt0, ptr addrspace(1) poison, align 1690 store volatile i8 %elt1, ptr addrspace(1) poison, align 1691 store volatile i8 %elt4, ptr addrspace(1) poison, align 1692 store volatile i8 %elt5, ptr addrspace(1) poison, align 1693 ret void694}695 696define amdgpu_kernel void @reduce_load_vector_v8i8_extract_45() #0 {697; SI-LABEL: reduce_load_vector_v8i8_extract_45:698; SI: ; %bb.0:699; SI-NEXT: s_mov_b32 flat_scratch_lo, s13700; SI-NEXT: s_add_i32 s12, s12, s17701; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8702; SI-NEXT: s_mov_b64 s[0:1], 4703; SI-NEXT: s_load_dword s0, s[0:1], 0x0704; SI-NEXT: s_waitcnt lgkmcnt(0)705; SI-NEXT: s_lshr_b32 s1, s0, 8706; SI-NEXT: v_mov_b32_e32 v0, s0707; SI-NEXT: flat_store_byte v[0:1], v0708; SI-NEXT: s_waitcnt vmcnt(0)709; SI-NEXT: v_mov_b32_e32 v0, s1710; SI-NEXT: flat_store_byte v[0:1], v0711; SI-NEXT: s_waitcnt vmcnt(0)712; SI-NEXT: s_endpgm713;714; VI-LABEL: reduce_load_vector_v8i8_extract_45:715; VI: ; %bb.0:716; VI-NEXT: s_mov_b64 s[0:1], 4717; VI-NEXT: s_load_dword s0, s[0:1], 0x0718; VI-NEXT: s_add_i32 s12, s12, s17719; VI-NEXT: s_mov_b32 flat_scratch_lo, s13720; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8721; VI-NEXT: s_waitcnt lgkmcnt(0)722; VI-NEXT: s_lshr_b32 s1, s0, 8723; VI-NEXT: v_mov_b32_e32 v0, s0724; VI-NEXT: flat_store_byte v[0:1], v0725; VI-NEXT: s_waitcnt vmcnt(0)726; VI-NEXT: v_mov_b32_e32 v0, s1727; VI-NEXT: flat_store_byte v[0:1], v0728; VI-NEXT: s_waitcnt vmcnt(0)729; VI-NEXT: s_endpgm730 %load = load <8 x i8>, ptr addrspace(4) null731 %elt4 = extractelement <8 x i8> %load, i32 4732 %elt5 = extractelement <8 x i8> %load, i32 5733 store volatile i8 %elt4, ptr addrspace(1) poison, align 1734 store volatile i8 %elt5, ptr addrspace(1) poison, align 1735 ret void736}737 738; FIXME: ought to be able to eliminate high half of load739define amdgpu_kernel void @reduce_load_vector_v16i8_extract_0145() #0 {740; SI-LABEL: reduce_load_vector_v16i8_extract_0145:741; SI: ; %bb.0:742; SI-NEXT: s_mov_b32 flat_scratch_lo, s13743; SI-NEXT: s_add_i32 s12, s12, s17744; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8745; SI-NEXT: s_mov_b64 s[0:1], 0746; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0747; SI-NEXT: s_waitcnt lgkmcnt(0)748; SI-NEXT: s_lshr_b32 s2, s0, 8749; SI-NEXT: s_lshr_b32 s3, s1, 8750; SI-NEXT: v_mov_b32_e32 v0, s0751; SI-NEXT: flat_store_byte v[0:1], v0752; SI-NEXT: s_waitcnt vmcnt(0)753; SI-NEXT: v_mov_b32_e32 v0, s1754; SI-NEXT: v_mov_b32_e32 v1, s2755; SI-NEXT: flat_store_byte v[0:1], v1756; SI-NEXT: s_waitcnt vmcnt(0)757; SI-NEXT: flat_store_byte v[0:1], v0758; SI-NEXT: s_waitcnt vmcnt(0)759; SI-NEXT: v_mov_b32_e32 v0, s3760; SI-NEXT: flat_store_byte v[0:1], v0761; SI-NEXT: s_waitcnt vmcnt(0)762; SI-NEXT: s_endpgm763;764; VI-LABEL: reduce_load_vector_v16i8_extract_0145:765; VI: ; %bb.0:766; VI-NEXT: s_mov_b64 s[0:1], 0767; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0768; VI-NEXT: s_add_i32 s12, s12, s17769; VI-NEXT: s_mov_b32 flat_scratch_lo, s13770; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8771; VI-NEXT: s_waitcnt lgkmcnt(0)772; VI-NEXT: s_lshr_b32 s2, s0, 8773; VI-NEXT: v_mov_b32_e32 v0, s0774; VI-NEXT: v_mov_b32_e32 v1, s1775; VI-NEXT: s_lshr_b32 s3, s1, 8776; VI-NEXT: flat_store_byte v[0:1], v0777; VI-NEXT: s_waitcnt vmcnt(0)778; VI-NEXT: v_mov_b32_e32 v0, s2779; VI-NEXT: flat_store_byte v[0:1], v0780; VI-NEXT: s_waitcnt vmcnt(0)781; VI-NEXT: flat_store_byte v[0:1], v1782; VI-NEXT: s_waitcnt vmcnt(0)783; VI-NEXT: v_mov_b32_e32 v0, s3784; VI-NEXT: flat_store_byte v[0:1], v0785; VI-NEXT: s_waitcnt vmcnt(0)786; VI-NEXT: s_endpgm787 %load = load <16 x i8>, ptr addrspace(4) null788 %elt0 = extractelement <16 x i8> %load, i32 0789 %elt1 = extractelement <16 x i8> %load, i32 1790 %elt4 = extractelement <16 x i8> %load, i32 4791 %elt5 = extractelement <16 x i8> %load, i32 5792 store volatile i8 %elt0, ptr addrspace(1) poison, align 1793 store volatile i8 %elt1, ptr addrspace(1) poison, align 1794 store volatile i8 %elt4, ptr addrspace(1) poison, align 1795 store volatile i8 %elt5, ptr addrspace(1) poison, align 1796 ret void797}798 799attributes #0 = { nounwind }800