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1; RUN: llc -mtriple=amdgcn < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC3; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC4 5; FUNC-LABEL: {{^}}fadd_f32:6; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W7; SI: v_add_f328define amdgpu_kernel void @fadd_f32(ptr addrspace(1) %out, float %a, float %b) #0 {9 %add = fadd float %a, %b10 store float %add, ptr addrspace(1) %out, align 411 ret void12}13 14; FUNC-LABEL: {{^}}fadd_v2f32:15; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z16; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y17; SI: v_add_f3218; SI: v_add_f3219define amdgpu_kernel void @fadd_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {20 %add = fadd <2 x float> %a, %b21 store <2 x float> %add, ptr addrspace(1) %out, align 822 ret void23}24 25; FUNC-LABEL: {{^}}fadd_v4f32:26; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}27; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}28; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}29; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}30; SI: v_add_f3231; SI: v_add_f3232; SI: v_add_f3233; SI: v_add_f3234define amdgpu_kernel void @fadd_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {35 %b_ptr = getelementptr <4 x float>, ptr addrspace(1) %in, i32 136 %a = load <4 x float>, ptr addrspace(1) %in, align 1637 %b = load <4 x float>, ptr addrspace(1) %b_ptr, align 1638 %result = fadd <4 x float> %a, %b39 store <4 x float> %result, ptr addrspace(1) %out, align 1640 ret void41}42 43; FUNC-LABEL: {{^}}fadd_v8f32:44; R600: ADD45; R600: ADD46; R600: ADD47; R600: ADD48; R600: ADD49; R600: ADD50; R600: ADD51; R600: ADD52; SI: v_add_f3253; SI: v_add_f3254; SI: v_add_f3255; SI: v_add_f3256; SI: v_add_f3257; SI: v_add_f3258; SI: v_add_f3259; SI: v_add_f3260define amdgpu_kernel void @fadd_v8f32(ptr addrspace(1) %out, <8 x float> %a, <8 x float> %b) #0 {61 %add = fadd <8 x float> %a, %b62 store <8 x float> %add, ptr addrspace(1) %out, align 3263 ret void64}65 66; FUNC-LABEL: {{^}}fadd_0_nsz_attr_f32:67; SI-NOT: v_add_f3268define amdgpu_kernel void @fadd_0_nsz_attr_f32(ptr addrspace(1) %out, float %a) #1 {69 %add = fadd nsz float %a, 0.070 store float %add, ptr addrspace(1) %out, align 471 ret void72}73 74attributes #0 = { nounwind }75attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }76