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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck %s3 4; CHECK-LABEL: {{^}}v_fadd_f64:5; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}6define amdgpu_kernel void @v_fadd_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,7 ptr addrspace(1) %in2) {8 %tid = call i32 @llvm.amdgcn.workitem.id.x()9 %gep1 = getelementptr inbounds double, ptr addrspace(1) %in1, i32 %tid10 %gep2 = getelementptr inbounds double, ptr addrspace(1) %in2, i32 %tid11 %r0 = load double, ptr addrspace(1) %gep112 %r1 = load double, ptr addrspace(1) %gep213 %r2 = fadd double %r0, %r114 store double %r2, ptr addrspace(1) %out15 ret void16}17 18; CHECK-LABEL: {{^}}s_fadd_f64:19; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}20define amdgpu_kernel void @s_fadd_f64(ptr addrspace(1) %out, double %r0, double %r1) {21 %r2 = fadd double %r0, %r122 store double %r2, ptr addrspace(1) %out23 ret void24}25 26; CHECK-LABEL: {{^}}v_fadd_v2f64:27; CHECK: v_add_f6428; CHECK: v_add_f6429; CHECK: _store_dwordx430define amdgpu_kernel void @v_fadd_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,31 ptr addrspace(1) %in2) {32 %r0 = load <2 x double>, ptr addrspace(1) %in133 %r1 = load <2 x double>, ptr addrspace(1) %in234 %r2 = fadd <2 x double> %r0, %r135 store <2 x double> %r2, ptr addrspace(1) %out36 ret void37}38 39; CHECK-LABEL: {{^}}s_fadd_v2f64:40; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}41; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}42; CHECK: _store_dwordx443define amdgpu_kernel void @s_fadd_v2f64(ptr addrspace(1) %out, <2 x double> %r0, <2 x double> %r1) {44 %r2 = fadd <2 x double> %r0, %r145 store <2 x double> %r2, ptr addrspace(1) %out46 ret void47}48 49declare i32 @llvm.amdgcn.workitem.id.x() #150 51attributes #0 = { nounwind }52attributes #1 = { nounwind readnone }53