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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s3; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s4 5declare float @llvm.ceil.f32(float) nounwind readnone6declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone7declare <3 x float> @llvm.ceil.v3f32(<3 x float>) nounwind readnone8declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone9declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone10declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone11 12; FUNC-LABEL: {{^}}fceil_f32:13; SI: v_ceil_f32_e3214; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]15; EG: CEIL {{\*? *}}[[RESULT]]16define amdgpu_kernel void @fceil_f32(ptr addrspace(1) %out, float %x) {17 %y = call float @llvm.ceil.f32(float %x) nounwind readnone18 store float %y, ptr addrspace(1) %out19 ret void20}21 22; FUNC-LABEL: {{^}}fceil_v2f32:23; SI: v_ceil_f32_e3224; SI: v_ceil_f32_e3225; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}26; EG: CEIL {{\*? *}}[[RESULT]]27; EG: CEIL {{\*? *}}[[RESULT]]28define amdgpu_kernel void @fceil_v2f32(ptr addrspace(1) %out, <2 x float> %x) {29 %y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x) nounwind readnone30 store <2 x float> %y, ptr addrspace(1) %out31 ret void32}33 34; FUNC-LABEL: {{^}}fceil_v3f32:35; FIXME-SI: v_ceil_f32_e3236; FIXME-SI: v_ceil_f32_e3237; FIXME-SI: v_ceil_f32_e3238; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores39; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}40; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}41; EG-DAG: CEIL {{\*? *}}[[RESULT1]]42; EG-DAG: CEIL {{\*? *}}[[RESULT2]]43; EG-DAG: CEIL {{\*? *}}[[RESULT2]]44define amdgpu_kernel void @fceil_v3f32(ptr addrspace(1) %out, <3 x float> %x) {45 %y = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) nounwind readnone46 store <3 x float> %y, ptr addrspace(1) %out47 ret void48}49 50; FUNC-LABEL: {{^}}fceil_v4f32:51; SI: v_ceil_f32_e3252; SI: v_ceil_f32_e3253; SI: v_ceil_f32_e3254; SI: v_ceil_f32_e3255; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}56; EG: CEIL {{\*? *}}[[RESULT]]57; EG: CEIL {{\*? *}}[[RESULT]]58; EG: CEIL {{\*? *}}[[RESULT]]59; EG: CEIL {{\*? *}}[[RESULT]]60define amdgpu_kernel void @fceil_v4f32(ptr addrspace(1) %out, <4 x float> %x) {61 %y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone62 store <4 x float> %y, ptr addrspace(1) %out63 ret void64}65 66; FUNC-LABEL: {{^}}fceil_v8f32:67; SI: v_ceil_f32_e3268; SI: v_ceil_f32_e3269; SI: v_ceil_f32_e3270; SI: v_ceil_f32_e3271; SI: v_ceil_f32_e3272; SI: v_ceil_f32_e3273; SI: v_ceil_f32_e3274; SI: v_ceil_f32_e3275; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}76; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}77; EG-DAG: CEIL {{\*? *}}[[RESULT1]]78; EG-DAG: CEIL {{\*? *}}[[RESULT1]]79; EG-DAG: CEIL {{\*? *}}[[RESULT1]]80; EG-DAG: CEIL {{\*? *}}[[RESULT1]]81; EG-DAG: CEIL {{\*? *}}[[RESULT2]]82; EG-DAG: CEIL {{\*? *}}[[RESULT2]]83; EG-DAG: CEIL {{\*? *}}[[RESULT2]]84; EG-DAG: CEIL {{\*? *}}[[RESULT2]]85define amdgpu_kernel void @fceil_v8f32(ptr addrspace(1) %out, <8 x float> %x) {86 %y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone87 store <8 x float> %y, ptr addrspace(1) %out88 ret void89}90 91; FUNC-LABEL: {{^}}fceil_v16f32:92; SI: v_ceil_f32_e3293; SI: v_ceil_f32_e3294; SI: v_ceil_f32_e3295; SI: v_ceil_f32_e3296; SI: v_ceil_f32_e3297; SI: v_ceil_f32_e3298; SI: v_ceil_f32_e3299; SI: v_ceil_f32_e32100; SI: v_ceil_f32_e32101; SI: v_ceil_f32_e32102; SI: v_ceil_f32_e32103; SI: v_ceil_f32_e32104; SI: v_ceil_f32_e32105; SI: v_ceil_f32_e32106; SI: v_ceil_f32_e32107; SI: v_ceil_f32_e32108; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}109; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}110; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}}111; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT4:T[0-9]+]]{{\.[XYZW]}}112; EG-DAG: CEIL {{\*? *}}[[RESULT1]]113; EG-DAG: CEIL {{\*? *}}[[RESULT1]]114; EG-DAG: CEIL {{\*? *}}[[RESULT1]]115; EG-DAG: CEIL {{\*? *}}[[RESULT1]]116; EG-DAG: CEIL {{\*? *}}[[RESULT2]]117; EG-DAG: CEIL {{\*? *}}[[RESULT2]]118; EG-DAG: CEIL {{\*? *}}[[RESULT2]]119; EG-DAG: CEIL {{\*? *}}[[RESULT2]]120; EG-DAG: CEIL {{\*? *}}[[RESULT3]]121; EG-DAG: CEIL {{\*? *}}[[RESULT3]]122; EG-DAG: CEIL {{\*? *}}[[RESULT3]]123; EG-DAG: CEIL {{\*? *}}[[RESULT3]]124; EG-DAG: CEIL {{\*? *}}[[RESULT4]]125; EG-DAG: CEIL {{\*? *}}[[RESULT4]]126; EG-DAG: CEIL {{\*? *}}[[RESULT4]]127; EG-DAG: CEIL {{\*? *}}[[RESULT4]]128define amdgpu_kernel void @fceil_v16f32(ptr addrspace(1) %out, <16 x float> %x) {129 %y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone130 store <16 x float> %y, ptr addrspace(1) %out131 ret void132}133