757 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s3; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s5 6declare double @llvm.ceil.f64(double) nounwind readnone7declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone8declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone9declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone10declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone11declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone12 13define amdgpu_kernel void @fceil_f64(ptr addrspace(1) %out, double %x) {14; SI-LABEL: fceil_f64:15; SI: ; %bb.0:16; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x917; SI-NEXT: s_mov_b32 s7, 0xf00018; SI-NEXT: s_mov_b32 s6, -119; SI-NEXT: s_mov_b32 s5, 0xfffff20; SI-NEXT: s_mov_b32 s4, s621; SI-NEXT: s_waitcnt lgkmcnt(0)22; SI-NEXT: s_bfe_u32 s8, s3, 0xb001423; SI-NEXT: s_and_b32 s9, s3, 0x8000000024; SI-NEXT: s_addk_i32 s8, 0xfc0125; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s826; SI-NEXT: s_andn2_b64 s[4:5], s[2:3], s[4:5]27; SI-NEXT: s_cmp_lt_i32 s8, 028; SI-NEXT: s_cselect_b32 s4, 0, s429; SI-NEXT: s_cselect_b32 s5, s9, s530; SI-NEXT: s_cmp_gt_i32 s8, 5131; SI-NEXT: s_cselect_b32 s9, s3, s532; SI-NEXT: s_cselect_b32 s8, s2, s433; SI-NEXT: v_cmp_gt_f64_e64 s[4:5], s[2:3], 034; SI-NEXT: v_mov_b32_e32 v0, s835; SI-NEXT: v_mov_b32_e32 v1, s936; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[0:1]37; SI-NEXT: s_and_b64 s[2:3], s[4:5], vcc38; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec39; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 040; SI-NEXT: v_mov_b32_e32 v0, 041; SI-NEXT: s_mov_b32 s4, s042; SI-NEXT: s_mov_b32 s5, s143; SI-NEXT: v_mov_b32_e32 v1, s244; SI-NEXT: v_add_f64 v[0:1], s[8:9], v[0:1]45; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 046; SI-NEXT: s_endpgm47 %y = call double @llvm.ceil.f64(double %x) nounwind readnone48 store double %y, ptr addrspace(1) %out49 ret void50}51 52define amdgpu_kernel void @fceil_v2f64(ptr addrspace(1) %out, <2 x double> %x) {53; SI-LABEL: fceil_v2f64:54; SI: ; %bb.0:55; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x956; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd57; SI-NEXT: s_mov_b32 s3, 0xf00058; SI-NEXT: s_mov_b32 s2, -159; SI-NEXT: s_mov_b32 s9, 0xfffff60; SI-NEXT: v_mov_b32_e32 v0, 061; SI-NEXT: s_mov_b32 s8, s262; SI-NEXT: s_waitcnt lgkmcnt(0)63; SI-NEXT: s_bfe_u32 s10, s7, 0xb001464; SI-NEXT: s_and_b32 s12, s7, 0x8000000065; SI-NEXT: s_add_i32 s13, s10, 0xfffffc0166; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], s1367; SI-NEXT: s_andn2_b64 s[10:11], s[6:7], s[10:11]68; SI-NEXT: s_cmp_lt_i32 s13, 069; SI-NEXT: s_cselect_b32 s10, 0, s1070; SI-NEXT: s_cselect_b32 s11, s12, s1171; SI-NEXT: s_cmp_gt_i32 s13, 5172; SI-NEXT: s_cselect_b32 s11, s7, s1173; SI-NEXT: s_cselect_b32 s10, s6, s1074; SI-NEXT: v_cmp_gt_f64_e64 s[12:13], s[6:7], 075; SI-NEXT: v_mov_b32_e32 v1, s1076; SI-NEXT: v_mov_b32_e32 v2, s1177; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[1:2]78; SI-NEXT: s_and_b64 s[6:7], s[12:13], vcc79; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec80; SI-NEXT: s_cselect_b32 s12, 0x3ff00000, 081; SI-NEXT: s_bfe_u32 s6, s5, 0xb001482; SI-NEXT: s_and_b32 s13, s5, 0x8000000083; SI-NEXT: s_add_i32 s14, s6, 0xfffffc0184; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], s1485; SI-NEXT: s_andn2_b64 s[6:7], s[4:5], s[6:7]86; SI-NEXT: s_cmp_lt_i32 s14, 087; SI-NEXT: s_cselect_b32 s6, 0, s688; SI-NEXT: s_cselect_b32 s7, s13, s789; SI-NEXT: s_cmp_gt_i32 s14, 5190; SI-NEXT: s_cselect_b32 s7, s5, s791; SI-NEXT: s_cselect_b32 s6, s4, s692; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[4:5], 093; SI-NEXT: v_mov_b32_e32 v1, s1294; SI-NEXT: v_mov_b32_e32 v2, s695; SI-NEXT: v_mov_b32_e32 v3, s796; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[2:3]97; SI-NEXT: s_and_b64 s[4:5], s[8:9], vcc98; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec99; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0100; SI-NEXT: v_add_f64 v[2:3], s[10:11], v[0:1]101; SI-NEXT: v_mov_b32_e32 v1, s4102; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[0:1]103; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0104; SI-NEXT: s_endpgm105 %y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone106 store <2 x double> %y, ptr addrspace(1) %out107 ret void108}109 110; FIXME-FUNC-LABEL: {{^}}fceil_v3f64:111; FIXME-CI: v_ceil_f64_e32112; FIXME-CI: v_ceil_f64_e32113; FIXME-CI: v_ceil_f64_e32114; define amdgpu_kernel void @fceil_v3f64(ptr addrspace(1) %out, <3 x double> %x) {115; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone116; store <3 x double> %y, ptr addrspace(1) %out117; ret void118; }119 120define amdgpu_kernel void @fceil_v4f64(ptr addrspace(1) %out, <4 x double> %x) {121; SI-LABEL: fceil_v4f64:122; SI: ; %bb.0:123; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9124; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x11125; SI-NEXT: s_mov_b32 s11, 0xf000126; SI-NEXT: s_mov_b32 s10, -1127; SI-NEXT: s_mov_b32 s13, 0xfffff128; SI-NEXT: v_mov_b32_e32 v0, 0129; SI-NEXT: s_mov_b32 s12, s10130; SI-NEXT: s_waitcnt lgkmcnt(0)131; SI-NEXT: s_bfe_u32 s18, s3, 0xb0014132; SI-NEXT: s_and_b32 s20, s3, 0x80000000133; SI-NEXT: v_cmp_gt_f64_e64 s[14:15], s[2:3], 0134; SI-NEXT: v_cmp_gt_f64_e64 s[16:17], s[0:1], 0135; SI-NEXT: s_add_i32 s21, s18, 0xfffffc01136; SI-NEXT: s_lshr_b64 s[18:19], s[12:13], s21137; SI-NEXT: s_andn2_b64 s[18:19], s[2:3], s[18:19]138; SI-NEXT: s_cmp_lt_i32 s21, 0139; SI-NEXT: s_cselect_b32 s18, 0, s18140; SI-NEXT: s_cselect_b32 s19, s20, s19141; SI-NEXT: s_cmp_gt_i32 s21, 51142; SI-NEXT: s_cselect_b32 s19, s3, s19143; SI-NEXT: s_cselect_b32 s18, s2, s18144; SI-NEXT: v_cmp_gt_f64_e64 s[20:21], s[6:7], 0145; SI-NEXT: v_mov_b32_e32 v1, s18146; SI-NEXT: v_mov_b32_e32 v2, s19147; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[1:2]148; SI-NEXT: s_and_b64 s[2:3], s[14:15], vcc149; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec150; SI-NEXT: s_cselect_b32 s22, 0x3ff00000, 0151; SI-NEXT: s_bfe_u32 s2, s1, 0xb0014152; SI-NEXT: s_and_b32 s14, s1, 0x80000000153; SI-NEXT: s_add_i32 s15, s2, 0xfffffc01154; SI-NEXT: s_lshr_b64 s[2:3], s[12:13], s15155; SI-NEXT: s_andn2_b64 s[2:3], s[0:1], s[2:3]156; SI-NEXT: s_cmp_lt_i32 s15, 0157; SI-NEXT: s_cselect_b32 s2, 0, s2158; SI-NEXT: s_cselect_b32 s3, s14, s3159; SI-NEXT: s_cmp_gt_i32 s15, 51160; SI-NEXT: s_cselect_b32 s3, s1, s3161; SI-NEXT: s_cselect_b32 s2, s0, s2162; SI-NEXT: v_cmp_gt_f64_e64 s[14:15], s[4:5], 0163; SI-NEXT: v_mov_b32_e32 v1, s22164; SI-NEXT: v_mov_b32_e32 v2, s2165; SI-NEXT: v_mov_b32_e32 v3, s3166; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[0:1], v[2:3]167; SI-NEXT: s_and_b64 s[0:1], s[16:17], vcc168; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec169; SI-NEXT: s_cselect_b32 s16, 0x3ff00000, 0170; SI-NEXT: s_bfe_u32 s0, s7, 0xb0014171; SI-NEXT: s_and_b32 s17, s7, 0x80000000172; SI-NEXT: s_add_i32 s22, s0, 0xfffffc01173; SI-NEXT: s_lshr_b64 s[0:1], s[12:13], s22174; SI-NEXT: s_andn2_b64 s[0:1], s[6:7], s[0:1]175; SI-NEXT: s_cmp_lt_i32 s22, 0176; SI-NEXT: s_cselect_b32 s0, 0, s0177; SI-NEXT: s_cselect_b32 s1, s17, s1178; SI-NEXT: s_cmp_gt_i32 s22, 51179; SI-NEXT: s_cselect_b32 s1, s7, s1180; SI-NEXT: s_cselect_b32 s0, s6, s0181; SI-NEXT: v_add_f64 v[4:5], s[18:19], v[0:1]182; SI-NEXT: v_mov_b32_e32 v1, s16183; SI-NEXT: v_mov_b32_e32 v3, s1184; SI-NEXT: v_mov_b32_e32 v2, s0185; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[2:3]186; SI-NEXT: s_and_b64 s[6:7], s[20:21], vcc187; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec188; SI-NEXT: s_cselect_b32 s16, 0x3ff00000, 0189; SI-NEXT: s_bfe_u32 s6, s5, 0xb0014190; SI-NEXT: s_and_b32 s17, s5, 0x80000000191; SI-NEXT: s_add_i32 s18, s6, 0xfffffc01192; SI-NEXT: s_lshr_b64 s[6:7], s[12:13], s18193; SI-NEXT: s_andn2_b64 s[6:7], s[4:5], s[6:7]194; SI-NEXT: s_cmp_lt_i32 s18, 0195; SI-NEXT: s_cselect_b32 s6, 0, s6196; SI-NEXT: s_cselect_b32 s7, s17, s7197; SI-NEXT: s_cmp_gt_i32 s18, 51198; SI-NEXT: s_cselect_b32 s7, s5, s7199; SI-NEXT: s_cselect_b32 s6, s4, s6200; SI-NEXT: v_add_f64 v[2:3], s[2:3], v[0:1]201; SI-NEXT: v_mov_b32_e32 v1, s16202; SI-NEXT: v_mov_b32_e32 v6, s6203; SI-NEXT: v_mov_b32_e32 v7, s7204; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[6:7]205; SI-NEXT: s_and_b64 s[2:3], s[14:15], vcc206; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec207; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0208; SI-NEXT: v_add_f64 v[8:9], s[0:1], v[0:1]209; SI-NEXT: v_mov_b32_e32 v1, s2210; SI-NEXT: v_add_f64 v[6:7], s[6:7], v[0:1]211; SI-NEXT: buffer_store_dwordx4 v[6:9], off, s[8:11], 0 offset:16212; SI-NEXT: buffer_store_dwordx4 v[2:5], off, s[8:11], 0213; SI-NEXT: s_endpgm214 %y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone215 store <4 x double> %y, ptr addrspace(1) %out216 ret void217}218 219define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {220; SI-LABEL: fceil_v8f64:221; SI: ; %bb.0:222; SI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x9223; SI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0x19224; SI-NEXT: s_mov_b32 s19, 0xf000225; SI-NEXT: s_mov_b32 s18, -1226; SI-NEXT: s_mov_b32 s21, 0xfffff227; SI-NEXT: v_mov_b32_e32 v4, 0228; SI-NEXT: s_mov_b32 s20, s18229; SI-NEXT: s_waitcnt lgkmcnt(0)230; SI-NEXT: s_bfe_u32 s33, s3, 0xb0014231; SI-NEXT: s_and_b32 s40, s3, 0x80000000232; SI-NEXT: v_cmp_gt_f64_e64 s[22:23], s[2:3], 0233; SI-NEXT: v_cmp_gt_f64_e64 s[26:27], s[0:1], 0234; SI-NEXT: v_cmp_gt_f64_e64 s[30:31], s[6:7], 0235; SI-NEXT: v_cmp_gt_f64_e64 s[36:37], s[4:5], 0236; SI-NEXT: v_cmp_gt_f64_e64 s[24:25], s[10:11], 0237; SI-NEXT: v_cmp_gt_f64_e64 s[28:29], s[8:9], 0238; SI-NEXT: v_cmp_gt_f64_e64 s[34:35], s[14:15], 0239; SI-NEXT: s_addk_i32 s33, 0xfc01240; SI-NEXT: s_lshr_b64 s[38:39], s[20:21], s33241; SI-NEXT: s_andn2_b64 s[38:39], s[2:3], s[38:39]242; SI-NEXT: s_cmp_lt_i32 s33, 0243; SI-NEXT: s_cselect_b32 s38, 0, s38244; SI-NEXT: s_cselect_b32 s39, s40, s39245; SI-NEXT: s_cmp_gt_i32 s33, 51246; SI-NEXT: s_cselect_b32 s41, s3, s39247; SI-NEXT: s_cselect_b32 s40, s2, s38248; SI-NEXT: v_cmp_gt_f64_e64 s[38:39], s[12:13], 0249; SI-NEXT: v_mov_b32_e32 v0, s40250; SI-NEXT: v_mov_b32_e32 v1, s41251; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[0:1]252; SI-NEXT: s_and_b64 s[2:3], s[22:23], vcc253; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec254; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0255; SI-NEXT: s_bfe_u32 s3, s1, 0xb0014256; SI-NEXT: s_and_b32 s22, s1, 0x80000000257; SI-NEXT: v_mov_b32_e32 v5, s2258; SI-NEXT: s_add_i32 s23, s3, 0xfffffc01259; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s23260; SI-NEXT: s_andn2_b64 s[2:3], s[0:1], s[2:3]261; SI-NEXT: s_cmp_lt_i32 s23, 0262; SI-NEXT: s_cselect_b32 s2, 0, s2263; SI-NEXT: s_cselect_b32 s3, s22, s3264; SI-NEXT: s_cmp_gt_i32 s23, 51265; SI-NEXT: s_cselect_b32 s3, s1, s3266; SI-NEXT: s_cselect_b32 s2, s0, s2267; SI-NEXT: v_add_f64 v[2:3], s[40:41], v[4:5]268; SI-NEXT: v_mov_b32_e32 v0, s2269; SI-NEXT: v_mov_b32_e32 v1, s3270; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[0:1], v[0:1]271; SI-NEXT: s_and_b64 s[0:1], s[26:27], vcc272; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec273; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0274; SI-NEXT: s_bfe_u32 s1, s7, 0xb0014275; SI-NEXT: s_and_b32 s22, s7, 0x80000000276; SI-NEXT: v_mov_b32_e32 v5, s0277; SI-NEXT: s_add_i32 s23, s1, 0xfffffc01278; SI-NEXT: s_lshr_b64 s[0:1], s[20:21], s23279; SI-NEXT: s_andn2_b64 s[0:1], s[6:7], s[0:1]280; SI-NEXT: s_cmp_lt_i32 s23, 0281; SI-NEXT: s_cselect_b32 s0, 0, s0282; SI-NEXT: s_cselect_b32 s1, s22, s1283; SI-NEXT: s_cmp_gt_i32 s23, 51284; SI-NEXT: s_cselect_b32 s1, s7, s1285; SI-NEXT: s_cselect_b32 s0, s6, s0286; SI-NEXT: v_add_f64 v[0:1], s[2:3], v[4:5]287; SI-NEXT: v_mov_b32_e32 v6, s1288; SI-NEXT: v_mov_b32_e32 v5, s0289; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[5:6]290; SI-NEXT: s_and_b64 s[2:3], s[30:31], vcc291; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec292; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0293; SI-NEXT: s_bfe_u32 s3, s5, 0xb0014294; SI-NEXT: s_and_b32 s6, s5, 0x80000000295; SI-NEXT: v_mov_b32_e32 v5, s2296; SI-NEXT: s_add_i32 s7, s3, 0xfffffc01297; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s7298; SI-NEXT: s_andn2_b64 s[2:3], s[4:5], s[2:3]299; SI-NEXT: s_cmp_lt_i32 s7, 0300; SI-NEXT: s_cselect_b32 s2, 0, s2301; SI-NEXT: s_cselect_b32 s3, s6, s3302; SI-NEXT: s_cmp_gt_i32 s7, 51303; SI-NEXT: s_cselect_b32 s3, s5, s3304; SI-NEXT: s_cselect_b32 s2, s4, s2305; SI-NEXT: v_add_f64 v[7:8], s[0:1], v[4:5]306; SI-NEXT: v_mov_b32_e32 v6, s3307; SI-NEXT: v_mov_b32_e32 v5, s2308; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[5:6]309; SI-NEXT: s_and_b64 s[0:1], s[36:37], vcc310; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec311; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0312; SI-NEXT: s_bfe_u32 s1, s11, 0xb0014313; SI-NEXT: s_and_b32 s4, s11, 0x80000000314; SI-NEXT: v_mov_b32_e32 v5, s0315; SI-NEXT: v_add_f64 v[5:6], s[2:3], v[4:5]316; SI-NEXT: s_add_i32 s2, s1, 0xfffffc01317; SI-NEXT: s_lshr_b64 s[0:1], s[20:21], s2318; SI-NEXT: s_andn2_b64 s[0:1], s[10:11], s[0:1]319; SI-NEXT: s_cmp_lt_i32 s2, 0320; SI-NEXT: s_cselect_b32 s0, 0, s0321; SI-NEXT: s_cselect_b32 s1, s4, s1322; SI-NEXT: s_cmp_gt_i32 s2, 51323; SI-NEXT: s_cselect_b32 s1, s11, s1324; SI-NEXT: s_cselect_b32 s0, s10, s0325; SI-NEXT: buffer_store_dwordx4 v[5:8], off, s[16:19], 0 offset:16326; SI-NEXT: s_waitcnt expcnt(0)327; SI-NEXT: v_mov_b32_e32 v6, s1328; SI-NEXT: v_mov_b32_e32 v5, s0329; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[5:6]330; SI-NEXT: s_and_b64 s[2:3], s[24:25], vcc331; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec332; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0333; SI-NEXT: s_bfe_u32 s3, s9, 0xb0014334; SI-NEXT: s_and_b32 s4, s9, 0x80000000335; SI-NEXT: v_mov_b32_e32 v5, s2336; SI-NEXT: s_add_i32 s5, s3, 0xfffffc01337; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s5338; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], s[2:3]339; SI-NEXT: s_cmp_lt_i32 s5, 0340; SI-NEXT: s_cselect_b32 s2, 0, s2341; SI-NEXT: s_cselect_b32 s3, s4, s3342; SI-NEXT: s_cmp_gt_i32 s5, 51343; SI-NEXT: s_cselect_b32 s3, s9, s3344; SI-NEXT: s_cselect_b32 s2, s8, s2345; SI-NEXT: v_add_f64 v[7:8], s[0:1], v[4:5]346; SI-NEXT: v_mov_b32_e32 v6, s3347; SI-NEXT: v_mov_b32_e32 v5, s2348; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[5:6]349; SI-NEXT: s_and_b64 s[0:1], s[28:29], vcc350; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec351; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0352; SI-NEXT: s_bfe_u32 s1, s15, 0xb0014353; SI-NEXT: s_and_b32 s4, s15, 0x80000000354; SI-NEXT: v_mov_b32_e32 v5, s0355; SI-NEXT: s_add_i32 s5, s1, 0xfffffc01356; SI-NEXT: s_lshr_b64 s[0:1], s[20:21], s5357; SI-NEXT: s_andn2_b64 s[0:1], s[14:15], s[0:1]358; SI-NEXT: s_cmp_lt_i32 s5, 0359; SI-NEXT: s_cselect_b32 s0, 0, s0360; SI-NEXT: s_cselect_b32 s1, s4, s1361; SI-NEXT: s_cmp_gt_i32 s5, 51362; SI-NEXT: s_cselect_b32 s1, s15, s1363; SI-NEXT: s_cselect_b32 s0, s14, s0364; SI-NEXT: v_add_f64 v[5:6], s[2:3], v[4:5]365; SI-NEXT: v_mov_b32_e32 v10, s1366; SI-NEXT: v_mov_b32_e32 v9, s0367; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[9:10]368; SI-NEXT: s_and_b64 s[2:3], s[34:35], vcc369; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec370; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0371; SI-NEXT: s_bfe_u32 s2, s13, 0xb0014372; SI-NEXT: s_and_b32 s5, s13, 0x80000000373; SI-NEXT: s_add_i32 s6, s2, 0xfffffc01374; SI-NEXT: s_lshr_b64 s[2:3], s[20:21], s6375; SI-NEXT: s_andn2_b64 s[2:3], s[12:13], s[2:3]376; SI-NEXT: s_cmp_lt_i32 s6, 0377; SI-NEXT: s_cselect_b32 s2, 0, s2378; SI-NEXT: s_cselect_b32 s3, s5, s3379; SI-NEXT: s_cmp_gt_i32 s6, 51380; SI-NEXT: s_cselect_b32 s3, s13, s3381; SI-NEXT: s_cselect_b32 s2, s12, s2382; SI-NEXT: buffer_store_dwordx4 v[5:8], off, s[16:19], 0 offset:32383; SI-NEXT: s_waitcnt expcnt(0)384; SI-NEXT: v_mov_b32_e32 v5, s4385; SI-NEXT: v_mov_b32_e32 v7, s3386; SI-NEXT: v_mov_b32_e32 v6, s2387; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[6:7]388; SI-NEXT: s_and_b64 s[4:5], s[38:39], vcc389; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec390; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0391; SI-NEXT: v_add_f64 v[6:7], s[0:1], v[4:5]392; SI-NEXT: v_mov_b32_e32 v5, s4393; SI-NEXT: v_add_f64 v[4:5], s[2:3], v[4:5]394; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 offset:48395; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0396; SI-NEXT: s_endpgm397 %y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone398 store <8 x double> %y, ptr addrspace(1) %out399 ret void400}401 402define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x) {403; SI-LABEL: fceil_v16f64:404; SI: ; %bb.0:405; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x29406; SI-NEXT: s_mov_b32 s26, -1407; SI-NEXT: s_mov_b32 s29, 0xfffff408; SI-NEXT: s_load_dwordx2 s[24:25], s[4:5], 0x9409; SI-NEXT: v_mov_b32_e32 v8, 0410; SI-NEXT: s_mov_b32 s28, s26411; SI-NEXT: s_waitcnt lgkmcnt(0)412; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014413; SI-NEXT: s_and_b32 s2, s11, 0x80000000414; SI-NEXT: s_add_i32 s3, s0, 0xfffffc01415; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s3416; SI-NEXT: s_andn2_b64 s[0:1], s[10:11], s[0:1]417; SI-NEXT: s_cmp_lt_i32 s3, 0418; SI-NEXT: s_cselect_b32 s0, 0, s0419; SI-NEXT: s_cselect_b32 s1, s2, s1420; SI-NEXT: s_cmp_gt_i32 s3, 51421; SI-NEXT: s_cselect_b32 s3, s11, s1422; SI-NEXT: s_cselect_b32 s2, s10, s0423; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[10:11], 0424; SI-NEXT: v_mov_b32_e32 v0, s2425; SI-NEXT: v_mov_b32_e32 v1, s3426; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]427; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc428; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec429; SI-NEXT: s_cselect_b32 s10, 0x3ff00000, 0430; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014431; SI-NEXT: s_and_b32 s6, s9, 0x80000000432; SI-NEXT: s_add_i32 s7, s0, 0xfffffc01433; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s7434; SI-NEXT: s_andn2_b64 s[0:1], s[8:9], s[0:1]435; SI-NEXT: s_cmp_lt_i32 s7, 0436; SI-NEXT: s_cselect_b32 s0, 0, s0437; SI-NEXT: s_cselect_b32 s1, s6, s1438; SI-NEXT: s_cmp_gt_i32 s7, 51439; SI-NEXT: s_cselect_b32 s7, s9, s1440; SI-NEXT: s_cselect_b32 s6, s8, s0441; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[8:9], 0442; SI-NEXT: v_mov_b32_e32 v0, s6443; SI-NEXT: v_mov_b32_e32 v1, s7444; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]445; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc446; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec447; SI-NEXT: s_cselect_b32 s27, 0x3ff00000, 0448; SI-NEXT: s_bfe_u32 s0, s15, 0xb0014449; SI-NEXT: s_and_b32 s8, s15, 0x80000000450; SI-NEXT: s_add_i32 s9, s0, 0xfffffc01451; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s9452; SI-NEXT: s_andn2_b64 s[0:1], s[14:15], s[0:1]453; SI-NEXT: s_cmp_lt_i32 s9, 0454; SI-NEXT: s_cselect_b32 s0, 0, s0455; SI-NEXT: s_cselect_b32 s1, s8, s1456; SI-NEXT: s_cmp_gt_i32 s9, 51457; SI-NEXT: s_cselect_b32 s9, s15, s1458; SI-NEXT: s_cselect_b32 s8, s14, s0459; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[14:15], 0460; SI-NEXT: v_mov_b32_e32 v9, s10461; SI-NEXT: v_mov_b32_e32 v0, s8462; SI-NEXT: v_mov_b32_e32 v1, s9463; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]464; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc465; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec466; SI-NEXT: s_cselect_b32 s14, 0x3ff00000, 0467; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014468; SI-NEXT: s_and_b32 s10, s13, 0x80000000469; SI-NEXT: s_add_i32 s15, s0, 0xfffffc01470; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s15471; SI-NEXT: s_andn2_b64 s[0:1], s[12:13], s[0:1]472; SI-NEXT: s_cmp_lt_i32 s15, 0473; SI-NEXT: s_cselect_b32 s0, 0, s0474; SI-NEXT: s_cselect_b32 s1, s10, s1475; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[12:13], 0476; SI-NEXT: s_cmp_gt_i32 s15, 51477; SI-NEXT: s_cselect_b32 s1, s13, s1478; SI-NEXT: s_cselect_b32 s0, s12, s0479; SI-NEXT: v_add_f64 v[2:3], s[2:3], v[8:9]480; SI-NEXT: v_mov_b32_e32 v9, s27481; SI-NEXT: v_mov_b32_e32 v0, s0482; SI-NEXT: v_mov_b32_e32 v1, s1483; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[0:1]484; SI-NEXT: s_and_b64 s[2:3], s[10:11], vcc485; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec486; SI-NEXT: s_cselect_b32 s10, 0x3ff00000, 0487; SI-NEXT: s_bfe_u32 s2, s19, 0xb0014488; SI-NEXT: s_and_b32 s11, s19, 0x80000000489; SI-NEXT: s_add_i32 s12, s2, 0xfffffc01490; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s12491; SI-NEXT: s_andn2_b64 s[2:3], s[18:19], s[2:3]492; SI-NEXT: s_cmp_lt_i32 s12, 0493; SI-NEXT: s_cselect_b32 s13, 0, s2494; SI-NEXT: s_cselect_b32 s11, s11, s3495; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[18:19], 0496; SI-NEXT: s_cmp_gt_i32 s12, 51497; SI-NEXT: s_cselect_b32 s31, s19, s11498; SI-NEXT: s_cselect_b32 s30, s18, s13499; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[8:9]500; SI-NEXT: v_mov_b32_e32 v9, s14501; SI-NEXT: v_mov_b32_e32 v4, s30502; SI-NEXT: v_mov_b32_e32 v5, s31503; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[4:5]504; SI-NEXT: s_and_b64 s[2:3], s[2:3], vcc505; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec506; SI-NEXT: s_cselect_b32 s33, 0x3ff00000, 0507; SI-NEXT: s_bfe_u32 s2, s17, 0xb0014508; SI-NEXT: s_and_b32 s6, s17, 0x80000000509; SI-NEXT: s_add_i32 s7, s2, 0xfffffc01510; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s7511; SI-NEXT: s_andn2_b64 s[2:3], s[16:17], s[2:3]512; SI-NEXT: s_cmp_lt_i32 s7, 0513; SI-NEXT: s_cselect_b32 s11, 0, s2514; SI-NEXT: s_cselect_b32 s6, s6, s3515; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[16:17], 0516; SI-NEXT: s_cmp_gt_i32 s7, 51517; SI-NEXT: s_cselect_b32 s19, s17, s6518; SI-NEXT: s_cselect_b32 s18, s16, s11519; SI-NEXT: v_add_f64 v[6:7], s[8:9], v[8:9]520; SI-NEXT: v_mov_b32_e32 v9, s10521; SI-NEXT: v_mov_b32_e32 v4, s18522; SI-NEXT: v_mov_b32_e32 v5, s19523; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[16:17], v[4:5]524; SI-NEXT: s_and_b64 s[2:3], s[2:3], vcc525; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec526; SI-NEXT: s_cselect_b32 s36, 0x3ff00000, 0527; SI-NEXT: s_bfe_u32 s2, s23, 0xb0014528; SI-NEXT: s_and_b32 s6, s23, 0x80000000529; SI-NEXT: s_add_i32 s7, s2, 0xfffffc01530; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s7531; SI-NEXT: s_andn2_b64 s[2:3], s[22:23], s[2:3]532; SI-NEXT: s_cmp_lt_i32 s7, 0533; SI-NEXT: s_cselect_b32 s6, s6, s3534; SI-NEXT: s_cselect_b32 s8, 0, s2535; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[22:23], 0536; SI-NEXT: s_cmp_gt_i32 s7, 51537; SI-NEXT: s_cselect_b32 s35, s23, s6538; SI-NEXT: s_cselect_b32 s34, s22, s8539; SI-NEXT: v_add_f64 v[4:5], s[0:1], v[8:9]540; SI-NEXT: v_mov_b32_e32 v9, s34541; SI-NEXT: v_mov_b32_e32 v10, s35542; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[22:23], v[9:10]543; SI-NEXT: s_and_b64 s[0:1], s[2:3], vcc544; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec545; SI-NEXT: s_cselect_b32 s37, 0x3ff00000, 0546; SI-NEXT: s_bfe_u32 s0, s21, 0xb0014547; SI-NEXT: s_and_b32 s2, s21, 0x80000000548; SI-NEXT: s_add_i32 s3, s0, 0xfffffc01549; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s3550; SI-NEXT: s_andn2_b64 s[0:1], s[20:21], s[0:1]551; SI-NEXT: s_cmp_lt_i32 s3, 0552; SI-NEXT: s_cselect_b32 s1, s2, s1553; SI-NEXT: s_cselect_b32 s0, 0, s0554; SI-NEXT: s_cmp_gt_i32 s3, 51555; SI-NEXT: s_cselect_b32 s17, s21, s1556; SI-NEXT: s_cselect_b32 s16, s20, s0557; SI-NEXT: v_cmp_gt_f64_e64 s[22:23], s[20:21], 0558; SI-NEXT: v_mov_b32_e32 v9, s16559; SI-NEXT: v_mov_b32_e32 v10, s17560; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[20:21], v[9:10]561; SI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0x39562; SI-NEXT: s_mov_b32 s27, 0xf000563; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:16564; SI-NEXT: v_mov_b32_e32 v9, s33565; SI-NEXT: s_waitcnt expcnt(0)566; SI-NEXT: v_add_f64 v[6:7], s[30:31], v[8:9]567; SI-NEXT: s_waitcnt lgkmcnt(0)568; SI-NEXT: v_cmp_gt_f64_e64 s[20:21], s[2:3], 0569; SI-NEXT: v_mov_b32_e32 v9, s36570; SI-NEXT: v_cmp_gt_f64_e64 s[30:31], s[0:1], 0571; SI-NEXT: v_add_f64 v[4:5], s[18:19], v[8:9]572; SI-NEXT: v_cmp_gt_f64_e64 s[18:19], s[6:7], 0573; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:32574; SI-NEXT: v_mov_b32_e32 v9, s37575; SI-NEXT: s_waitcnt expcnt(0)576; SI-NEXT: v_add_f64 v[6:7], s[34:35], v[8:9]577; SI-NEXT: v_cmp_gt_f64_e64 s[34:35], s[4:5], 0578; SI-NEXT: s_and_b64 s[22:23], s[22:23], vcc579; SI-NEXT: s_and_b64 s[22:23], s[22:23], exec580; SI-NEXT: s_cselect_b32 s22, 0x3ff00000, 0581; SI-NEXT: s_bfe_u32 s23, s3, 0xb0014582; SI-NEXT: s_and_b32 s33, s3, 0x80000000583; SI-NEXT: v_mov_b32_e32 v9, s22584; SI-NEXT: s_add_i32 s36, s23, 0xfffffc01585; SI-NEXT: s_lshr_b64 s[22:23], s[28:29], s36586; SI-NEXT: s_andn2_b64 s[22:23], s[2:3], s[22:23]587; SI-NEXT: s_cmp_lt_i32 s36, 0588; SI-NEXT: s_cselect_b32 s38, 0, s22589; SI-NEXT: s_cselect_b32 s33, s33, s23590; SI-NEXT: v_cmp_gt_f64_e64 s[22:23], s[10:11], 0591; SI-NEXT: s_cmp_gt_i32 s36, 51592; SI-NEXT: s_cselect_b32 s37, s3, s33593; SI-NEXT: s_cselect_b32 s36, s2, s38594; SI-NEXT: v_add_f64 v[4:5], s[16:17], v[8:9]595; SI-NEXT: v_mov_b32_e32 v9, s36596; SI-NEXT: v_mov_b32_e32 v10, s37597; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[9:10]598; SI-NEXT: s_and_b64 s[2:3], s[20:21], vcc599; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec600; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0601; SI-NEXT: s_bfe_u32 s3, s1, 0xb0014602; SI-NEXT: s_and_b32 s16, s1, 0x80000000603; SI-NEXT: v_mov_b32_e32 v9, s2604; SI-NEXT: s_add_i32 s17, s3, 0xfffffc01605; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s17606; SI-NEXT: s_andn2_b64 s[2:3], s[0:1], s[2:3]607; SI-NEXT: s_cmp_lt_i32 s17, 0608; SI-NEXT: s_cselect_b32 s20, 0, s2609; SI-NEXT: s_cselect_b32 s16, s16, s3610; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[8:9], 0611; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:48612; SI-NEXT: s_cmp_gt_i32 s17, 51613; SI-NEXT: s_cselect_b32 s17, s1, s16614; SI-NEXT: s_cselect_b32 s16, s0, s20615; SI-NEXT: s_waitcnt expcnt(0)616; SI-NEXT: v_add_f64 v[6:7], s[36:37], v[8:9]617; SI-NEXT: v_mov_b32_e32 v4, s16618; SI-NEXT: v_mov_b32_e32 v5, s17619; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[0:1], v[4:5]620; SI-NEXT: s_and_b64 s[0:1], s[30:31], vcc621; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec622; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0623; SI-NEXT: s_bfe_u32 s1, s7, 0xb0014624; SI-NEXT: s_and_b32 s20, s7, 0x80000000625; SI-NEXT: v_mov_b32_e32 v9, s0626; SI-NEXT: s_add_i32 s21, s1, 0xfffffc01627; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s21628; SI-NEXT: s_andn2_b64 s[0:1], s[6:7], s[0:1]629; SI-NEXT: s_cmp_lt_i32 s21, 0630; SI-NEXT: s_cselect_b32 s30, 0, s0631; SI-NEXT: s_cselect_b32 s20, s20, s1632; SI-NEXT: v_cmp_gt_f64_e64 s[0:1], s[14:15], 0633; SI-NEXT: s_cmp_gt_i32 s21, 51634; SI-NEXT: s_cselect_b32 s21, s7, s20635; SI-NEXT: s_cselect_b32 s20, s6, s30636; SI-NEXT: v_add_f64 v[4:5], s[16:17], v[8:9]637; SI-NEXT: v_mov_b32_e32 v9, s20638; SI-NEXT: v_mov_b32_e32 v10, s21639; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[6:7], v[9:10]640; SI-NEXT: s_and_b64 s[6:7], s[18:19], vcc641; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec642; SI-NEXT: s_cselect_b32 s6, 0x3ff00000, 0643; SI-NEXT: s_bfe_u32 s7, s5, 0xb0014644; SI-NEXT: s_and_b32 s16, s5, 0x80000000645; SI-NEXT: v_mov_b32_e32 v9, s6646; SI-NEXT: s_add_i32 s17, s7, 0xfffffc01647; SI-NEXT: s_lshr_b64 s[6:7], s[28:29], s17648; SI-NEXT: s_andn2_b64 s[6:7], s[4:5], s[6:7]649; SI-NEXT: s_cmp_lt_i32 s17, 0650; SI-NEXT: s_cselect_b32 s18, 0, s6651; SI-NEXT: s_cselect_b32 s16, s16, s7652; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[12:13], 0653; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:64654; SI-NEXT: s_cmp_gt_i32 s17, 51655; SI-NEXT: s_cselect_b32 s17, s5, s16656; SI-NEXT: s_cselect_b32 s16, s4, s18657; SI-NEXT: s_waitcnt expcnt(0)658; SI-NEXT: v_add_f64 v[6:7], s[20:21], v[8:9]659; SI-NEXT: v_mov_b32_e32 v4, s16660; SI-NEXT: v_mov_b32_e32 v5, s17661; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[4:5], v[4:5]662; SI-NEXT: s_and_b64 s[4:5], s[34:35], vcc663; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec664; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0665; SI-NEXT: s_bfe_u32 s5, s11, 0xb0014666; SI-NEXT: s_and_b32 s18, s11, 0x80000000667; SI-NEXT: v_mov_b32_e32 v9, s4668; SI-NEXT: v_add_f64 v[4:5], s[16:17], v[8:9]669; SI-NEXT: s_add_i32 s16, s5, 0xfffffc01670; SI-NEXT: s_lshr_b64 s[4:5], s[28:29], s16671; SI-NEXT: s_andn2_b64 s[4:5], s[10:11], s[4:5]672; SI-NEXT: s_cmp_lt_i32 s16, 0673; SI-NEXT: s_cselect_b32 s4, 0, s4674; SI-NEXT: s_cselect_b32 s5, s18, s5675; SI-NEXT: s_cmp_gt_i32 s16, 51676; SI-NEXT: s_cselect_b32 s5, s11, s5677; SI-NEXT: s_cselect_b32 s4, s10, s4678; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:80679; SI-NEXT: s_waitcnt expcnt(0)680; SI-NEXT: v_mov_b32_e32 v4, s4681; SI-NEXT: v_mov_b32_e32 v5, s5682; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[4:5]683; SI-NEXT: s_and_b64 s[10:11], s[22:23], vcc684; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec685; SI-NEXT: s_cselect_b32 s10, 0x3ff00000, 0686; SI-NEXT: s_bfe_u32 s11, s9, 0xb0014687; SI-NEXT: s_and_b32 s16, s9, 0x80000000688; SI-NEXT: v_mov_b32_e32 v9, s10689; SI-NEXT: s_add_i32 s17, s11, 0xfffffc01690; SI-NEXT: s_lshr_b64 s[10:11], s[28:29], s17691; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[10:11]692; SI-NEXT: s_cmp_lt_i32 s17, 0693; SI-NEXT: s_cselect_b32 s10, 0, s10694; SI-NEXT: s_cselect_b32 s11, s16, s11695; SI-NEXT: s_cmp_gt_i32 s17, 51696; SI-NEXT: s_cselect_b32 s11, s9, s11697; SI-NEXT: s_cselect_b32 s10, s8, s10698; SI-NEXT: v_add_f64 v[6:7], s[4:5], v[8:9]699; SI-NEXT: v_mov_b32_e32 v4, s10700; SI-NEXT: v_mov_b32_e32 v5, s11701; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[4:5]702; SI-NEXT: s_and_b64 s[2:3], s[2:3], vcc703; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec704; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0705; SI-NEXT: s_bfe_u32 s3, s15, 0xb0014706; SI-NEXT: s_and_b32 s4, s15, 0x80000000707; SI-NEXT: v_mov_b32_e32 v9, s2708; SI-NEXT: s_add_i32 s5, s3, 0xfffffc01709; SI-NEXT: s_lshr_b64 s[2:3], s[28:29], s5710; SI-NEXT: s_andn2_b64 s[2:3], s[14:15], s[2:3]711; SI-NEXT: s_cmp_lt_i32 s5, 0712; SI-NEXT: s_cselect_b32 s2, 0, s2713; SI-NEXT: s_cselect_b32 s3, s4, s3714; SI-NEXT: s_cmp_gt_i32 s5, 51715; SI-NEXT: s_cselect_b32 s3, s15, s3716; SI-NEXT: s_cselect_b32 s2, s14, s2717; SI-NEXT: v_add_f64 v[4:5], s[10:11], v[8:9]718; SI-NEXT: v_mov_b32_e32 v10, s3719; SI-NEXT: v_mov_b32_e32 v9, s2720; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[9:10]721; SI-NEXT: s_and_b64 s[0:1], s[0:1], vcc722; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec723; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0724; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014725; SI-NEXT: s_and_b32 s5, s13, 0x80000000726; SI-NEXT: s_add_i32 s8, s0, 0xfffffc01727; SI-NEXT: s_lshr_b64 s[0:1], s[28:29], s8728; SI-NEXT: s_andn2_b64 s[0:1], s[12:13], s[0:1]729; SI-NEXT: s_cmp_lt_i32 s8, 0730; SI-NEXT: s_cselect_b32 s0, 0, s0731; SI-NEXT: s_cselect_b32 s1, s5, s1732; SI-NEXT: s_cmp_gt_i32 s8, 51733; SI-NEXT: s_cselect_b32 s1, s13, s1734; SI-NEXT: s_cselect_b32 s0, s12, s0735; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:96736; SI-NEXT: v_mov_b32_e32 v9, s4737; SI-NEXT: s_waitcnt expcnt(0)738; SI-NEXT: v_mov_b32_e32 v5, s1739; SI-NEXT: v_mov_b32_e32 v4, s0740; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[4:5]741; SI-NEXT: s_and_b64 s[4:5], s[6:7], vcc742; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec743; SI-NEXT: s_cselect_b32 s4, 0x3ff00000, 0744; SI-NEXT: v_add_f64 v[6:7], s[2:3], v[8:9]745; SI-NEXT: v_mov_b32_e32 v9, s4746; SI-NEXT: v_add_f64 v[4:5], s[0:1], v[8:9]747; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:112748; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[24:27], 0749; SI-NEXT: s_endpgm750 %y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone751 store <16 x double> %y, ptr addrspace(1) %out752 ret void753}754;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:755; CI: {{.*}}756; FUNC: {{.*}}757