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1; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s2 3; CHECK: {{^}}fcmp_sext:4; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}5 6define amdgpu_kernel void @fcmp_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {7entry:8 %0 = load float, ptr addrspace(1) %in9 %arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %in, i32 110 %1 = load float, ptr addrspace(1) %arrayidx111 %cmp = fcmp oeq float %0, %112 %sext = sext i1 %cmp to i3213 store i32 %sext, ptr addrspace(1) %out14 ret void15}16 17; This test checks that a setcc node with f32 operands is lowered to a18; SET*_DX10 instruction. Previously we were lowering this to:19; SET* + FP_TO_SINT20 21; CHECK: {{^}}fcmp_br:22; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}23; CHECK-NEXT: {{[0-9]+\(5.0}}24 25define amdgpu_kernel void @fcmp_br(ptr addrspace(1) %out, float %in) {26entry:27 %0 = fcmp oeq float %in, 5.028 br i1 %0, label %IF, label %ENDIF29 30IF:31 %1 = getelementptr i32, ptr addrspace(1) %out, i32 132 store i32 0, ptr addrspace(1) %133 br label %ENDIF34 35ENDIF:36 store i32 0, ptr addrspace(1) %out37 ret void38}39