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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope --check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope --check-prefixes=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope --check-prefixes=GFX9 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s7 8declare half @llvm.copysign.f16(half, half) #09declare float @llvm.copysign.f32(float, float) #010declare double @llvm.copysign.f64(double, double) #011declare <2 x half> @llvm.copysign.v2f16(<2 x half>, <2 x half>) #012declare <3 x half> @llvm.copysign.v3f16(<3 x half>, <3 x half>) #013declare <4 x half> @llvm.copysign.v4f16(<4 x half>, <4 x half>) #014declare i32 @llvm.amdgcn.workitem.id.x() #015 16define amdgpu_ps i16 @s_copysign_f16(half inreg %mag, half inreg %sign) {17; SI-LABEL: s_copysign_f16:18; SI: ; %bb.0:19; SI-NEXT: v_cvt_f16_f32_e32 v0, s020; SI-NEXT: s_brev_b32 s0, -221; SI-NEXT: v_mov_b32_e32 v1, s122; SI-NEXT: v_cvt_f32_f16_e32 v0, v023; SI-NEXT: v_bfi_b32 v0, s0, v0, v124; SI-NEXT: v_cvt_f16_f32_e32 v0, v025; SI-NEXT: v_readfirstlane_b32 s0, v026; SI-NEXT: ; return to shader part epilog27;28; VI-LABEL: s_copysign_f16:29; VI: ; %bb.0:30; VI-NEXT: s_movk_i32 s2, 0x7fff31; VI-NEXT: v_mov_b32_e32 v0, s032; VI-NEXT: v_mov_b32_e32 v1, s133; VI-NEXT: v_bfi_b32 v0, s2, v0, v134; VI-NEXT: v_readfirstlane_b32 s0, v035; VI-NEXT: ; return to shader part epilog36;37; GFX9-LABEL: s_copysign_f16:38; GFX9: ; %bb.0:39; GFX9-NEXT: s_movk_i32 s2, 0x7fff40; GFX9-NEXT: v_mov_b32_e32 v0, s041; GFX9-NEXT: v_mov_b32_e32 v1, s142; GFX9-NEXT: v_bfi_b32 v0, s2, v0, v143; GFX9-NEXT: v_readfirstlane_b32 s0, v044; GFX9-NEXT: ; return to shader part epilog45;46; GFX11-TRUE16-LABEL: s_copysign_f16:47; GFX11-TRUE16: ; %bb.0:48; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s149; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s050; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)51; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v052; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v053; GFX11-TRUE16-NEXT: ; return to shader part epilog54;55; GFX11-FAKE16-LABEL: s_copysign_f16:56; GFX11-FAKE16: ; %bb.0:57; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s158; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)59; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, s0, v060; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v061; GFX11-FAKE16-NEXT: ; return to shader part epilog62 %out = call half @llvm.copysign.f16(half %mag, half %sign)63 %cast = bitcast half %out to i1664 ret i16 %cast65}66 67define amdgpu_ps i16 @s_test_copysign_f16_0(half inreg %mag) {68; SI-LABEL: s_test_copysign_f16_0:69; SI: ; %bb.0:70; SI-NEXT: v_cvt_f16_f32_e32 v0, s071; SI-NEXT: v_and_b32_e32 v0, 0x7fff, v072; SI-NEXT: v_readfirstlane_b32 s0, v073; SI-NEXT: ; return to shader part epilog74;75; VI-LABEL: s_test_copysign_f16_0:76; VI: ; %bb.0:77; VI-NEXT: s_and_b32 s0, s0, 0x7fff78; VI-NEXT: ; return to shader part epilog79;80; GFX9-LABEL: s_test_copysign_f16_0:81; GFX9: ; %bb.0:82; GFX9-NEXT: s_and_b32 s0, s0, 0x7fff83; GFX9-NEXT: ; return to shader part epilog84;85; GFX11-LABEL: s_test_copysign_f16_0:86; GFX11: ; %bb.0:87; GFX11-NEXT: s_and_b32 s0, s0, 0x7fff88; GFX11-NEXT: ; return to shader part epilog89 %result = call half @llvm.copysign.f16(half %mag, half 0.0)90 %cast = bitcast half %result to i1691 ret i16 %cast92}93 94define amdgpu_ps i16 @s_test_copysign_f16_1(half inreg %mag) {95; SI-LABEL: s_test_copysign_f16_1:96; SI: ; %bb.0:97; SI-NEXT: v_cvt_f16_f32_e32 v0, s098; SI-NEXT: v_and_b32_e32 v0, 0x7fff, v099; SI-NEXT: v_readfirstlane_b32 s0, v0100; SI-NEXT: ; return to shader part epilog101;102; VI-LABEL: s_test_copysign_f16_1:103; VI: ; %bb.0:104; VI-NEXT: s_and_b32 s0, s0, 0x7fff105; VI-NEXT: ; return to shader part epilog106;107; GFX9-LABEL: s_test_copysign_f16_1:108; GFX9: ; %bb.0:109; GFX9-NEXT: s_and_b32 s0, s0, 0x7fff110; GFX9-NEXT: ; return to shader part epilog111;112; GFX11-LABEL: s_test_copysign_f16_1:113; GFX11: ; %bb.0:114; GFX11-NEXT: s_and_b32 s0, s0, 0x7fff115; GFX11-NEXT: ; return to shader part epilog116 %result = call half @llvm.copysign.f16(half %mag, half 1.0)117 %cast = bitcast half %result to i16118 ret i16 %cast119}120 121define amdgpu_ps i16 @s_test_copysign_f16_10.0(half inreg %mag) {122; SI-LABEL: s_test_copysign_f16_10.0:123; SI: ; %bb.0:124; SI-NEXT: v_cvt_f16_f32_e32 v0, s0125; SI-NEXT: v_and_b32_e32 v0, 0x7fff, v0126; SI-NEXT: v_readfirstlane_b32 s0, v0127; SI-NEXT: ; return to shader part epilog128;129; VI-LABEL: s_test_copysign_f16_10.0:130; VI: ; %bb.0:131; VI-NEXT: s_and_b32 s0, s0, 0x7fff132; VI-NEXT: ; return to shader part epilog133;134; GFX9-LABEL: s_test_copysign_f16_10.0:135; GFX9: ; %bb.0:136; GFX9-NEXT: s_and_b32 s0, s0, 0x7fff137; GFX9-NEXT: ; return to shader part epilog138;139; GFX11-LABEL: s_test_copysign_f16_10.0:140; GFX11: ; %bb.0:141; GFX11-NEXT: s_and_b32 s0, s0, 0x7fff142; GFX11-NEXT: ; return to shader part epilog143 %result = call half @llvm.copysign.f16(half %mag, half 10.0)144 %cast = bitcast half %result to i16145 ret i16 %cast146}147 148define amdgpu_ps i16 @s_test_copysign_f16_neg1(half inreg %mag) {149; SI-LABEL: s_test_copysign_f16_neg1:150; SI: ; %bb.0:151; SI-NEXT: v_cvt_f16_f32_e32 v0, s0152; SI-NEXT: v_or_b32_e32 v0, 0x8000, v0153; SI-NEXT: v_readfirstlane_b32 s0, v0154; SI-NEXT: ; return to shader part epilog155;156; VI-LABEL: s_test_copysign_f16_neg1:157; VI: ; %bb.0:158; VI-NEXT: s_bitset1_b32 s0, 15159; VI-NEXT: ; return to shader part epilog160;161; GFX9-LABEL: s_test_copysign_f16_neg1:162; GFX9: ; %bb.0:163; GFX9-NEXT: s_bitset1_b32 s0, 15164; GFX9-NEXT: ; return to shader part epilog165;166; GFX11-LABEL: s_test_copysign_f16_neg1:167; GFX11: ; %bb.0:168; GFX11-NEXT: s_bitset1_b32 s0, 15169; GFX11-NEXT: ; return to shader part epilog170 %result = call half @llvm.copysign.f16(half %mag, half -1.0)171 %cast = bitcast half %result to i16172 ret i16 %cast173}174 175define amdgpu_ps i16 @s_test_copysign_f16_neg10(half inreg %mag) {176; SI-LABEL: s_test_copysign_f16_neg10:177; SI: ; %bb.0:178; SI-NEXT: v_cvt_f16_f32_e32 v0, s0179; SI-NEXT: v_or_b32_e32 v0, 0x8000, v0180; SI-NEXT: v_readfirstlane_b32 s0, v0181; SI-NEXT: ; return to shader part epilog182;183; VI-LABEL: s_test_copysign_f16_neg10:184; VI: ; %bb.0:185; VI-NEXT: s_bitset1_b32 s0, 15186; VI-NEXT: ; return to shader part epilog187;188; GFX9-LABEL: s_test_copysign_f16_neg10:189; GFX9: ; %bb.0:190; GFX9-NEXT: s_bitset1_b32 s0, 15191; GFX9-NEXT: ; return to shader part epilog192;193; GFX11-LABEL: s_test_copysign_f16_neg10:194; GFX11: ; %bb.0:195; GFX11-NEXT: s_bitset1_b32 s0, 15196; GFX11-NEXT: ; return to shader part epilog197 %result = call half @llvm.copysign.f16(half %mag, half -10.0)198 %cast = bitcast half %result to i16199 ret i16 %cast200}201 202define amdgpu_ps i16 @s_test_copysign_f16_0_mag(half inreg %sign) {203; SI-LABEL: s_test_copysign_f16_0_mag:204; SI: ; %bb.0:205; SI-NEXT: v_cvt_f16_f32_e32 v0, s0206; SI-NEXT: v_and_b32_e32 v0, 0x8000, v0207; SI-NEXT: v_readfirstlane_b32 s0, v0208; SI-NEXT: ; return to shader part epilog209;210; VI-LABEL: s_test_copysign_f16_0_mag:211; VI: ; %bb.0:212; VI-NEXT: s_and_b32 s0, s0, 0x8000213; VI-NEXT: ; return to shader part epilog214;215; GFX9-LABEL: s_test_copysign_f16_0_mag:216; GFX9: ; %bb.0:217; GFX9-NEXT: s_and_b32 s0, s0, 0x8000218; GFX9-NEXT: ; return to shader part epilog219;220; GFX11-LABEL: s_test_copysign_f16_0_mag:221; GFX11: ; %bb.0:222; GFX11-NEXT: s_and_b32 s0, s0, 0x8000223; GFX11-NEXT: ; return to shader part epilog224 %result = call half @llvm.copysign.f16(half 0.0, half %sign)225 %cast = bitcast half %result to i16226 ret i16 %cast227}228 229 230define amdgpu_ps i16 @s_test_copysign_f16_1_mag(half inreg %sign) {231; SI-LABEL: s_test_copysign_f16_1_mag:232; SI: ; %bb.0:233; SI-NEXT: v_cvt_f16_f32_e32 v0, s0234; SI-NEXT: v_and_b32_e32 v0, 0x8000, v0235; SI-NEXT: v_or_b32_e32 v0, 0x3c00, v0236; SI-NEXT: v_readfirstlane_b32 s0, v0237; SI-NEXT: ; return to shader part epilog238;239; VI-LABEL: s_test_copysign_f16_1_mag:240; VI: ; %bb.0:241; VI-NEXT: s_and_b32 s0, s0, 0x8000242; VI-NEXT: s_or_b32 s0, s0, 0x3c00243; VI-NEXT: ; return to shader part epilog244;245; GFX9-LABEL: s_test_copysign_f16_1_mag:246; GFX9: ; %bb.0:247; GFX9-NEXT: s_and_b32 s0, s0, 0x8000248; GFX9-NEXT: s_or_b32 s0, s0, 0x3c00249; GFX9-NEXT: ; return to shader part epilog250;251; GFX11-LABEL: s_test_copysign_f16_1_mag:252; GFX11: ; %bb.0:253; GFX11-NEXT: s_and_b32 s0, s0, 0x8000254; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)255; GFX11-NEXT: s_or_b32 s0, s0, 0x3c00256; GFX11-NEXT: ; return to shader part epilog257 %result = call half @llvm.copysign.f16(half 1.0, half %sign)258 %cast = bitcast half %result to i16259 ret i16 %cast260}261 262define i16 @s_test_copysign_f16_10_mag(half inreg %sign) {263; SI-LABEL: s_test_copysign_f16_10_mag:264; SI: ; %bb.0:265; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)266; SI-NEXT: v_cvt_f16_f32_e32 v0, s16267; SI-NEXT: v_and_b32_e32 v0, 0x8000, v0268; SI-NEXT: v_or_b32_e32 v0, 0x4900, v0269; SI-NEXT: s_setpc_b64 s[30:31]270;271; VI-LABEL: s_test_copysign_f16_10_mag:272; VI: ; %bb.0:273; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)274; VI-NEXT: s_and_b32 s4, s16, 0x8000275; VI-NEXT: s_or_b32 s4, s4, 0x4900276; VI-NEXT: v_mov_b32_e32 v0, s4277; VI-NEXT: s_setpc_b64 s[30:31]278;279; GFX9-LABEL: s_test_copysign_f16_10_mag:280; GFX9: ; %bb.0:281; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)282; GFX9-NEXT: s_and_b32 s4, s16, 0x8000283; GFX9-NEXT: s_or_b32 s4, s4, 0x4900284; GFX9-NEXT: v_mov_b32_e32 v0, s4285; GFX9-NEXT: s_setpc_b64 s[30:31]286;287; GFX11-LABEL: s_test_copysign_f16_10_mag:288; GFX11: ; %bb.0:289; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)290; GFX11-NEXT: s_and_b32 s0, s0, 0x8000291; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)292; GFX11-NEXT: s_or_b32 s0, s0, 0x4900293; GFX11-NEXT: v_mov_b32_e32 v0, s0294; GFX11-NEXT: s_setpc_b64 s[30:31]295 %result = call half @llvm.copysign.f16(half 10.0, half %sign)296 %cast = bitcast half %result to i16297 ret i16 %cast298}299 300define amdgpu_ps i16 @s_test_copysign_f16_neg1_mag(half inreg %sign) {301; SI-LABEL: s_test_copysign_f16_neg1_mag:302; SI: ; %bb.0:303; SI-NEXT: v_cvt_f16_f32_e32 v0, s0304; SI-NEXT: v_and_b32_e32 v0, 0x8000, v0305; SI-NEXT: v_or_b32_e32 v0, 0x3c00, v0306; SI-NEXT: v_readfirstlane_b32 s0, v0307; SI-NEXT: ; return to shader part epilog308;309; VI-LABEL: s_test_copysign_f16_neg1_mag:310; VI: ; %bb.0:311; VI-NEXT: s_and_b32 s0, s0, 0x8000312; VI-NEXT: s_or_b32 s0, s0, 0x3c00313; VI-NEXT: ; return to shader part epilog314;315; GFX9-LABEL: s_test_copysign_f16_neg1_mag:316; GFX9: ; %bb.0:317; GFX9-NEXT: s_and_b32 s0, s0, 0x8000318; GFX9-NEXT: s_or_b32 s0, s0, 0x3c00319; GFX9-NEXT: ; return to shader part epilog320;321; GFX11-LABEL: s_test_copysign_f16_neg1_mag:322; GFX11: ; %bb.0:323; GFX11-NEXT: s_and_b32 s0, s0, 0x8000324; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)325; GFX11-NEXT: s_or_b32 s0, s0, 0x3c00326; GFX11-NEXT: ; return to shader part epilog327 %result = call half @llvm.copysign.f16(half -1.0, half %sign)328 %cast = bitcast half %result to i16329 ret i16 %cast330}331 332define amdgpu_ps i16 @s_test_copysign_f16_neg10_mag(half inreg %sign) {333; SI-LABEL: s_test_copysign_f16_neg10_mag:334; SI: ; %bb.0:335; SI-NEXT: v_cvt_f16_f32_e32 v0, s0336; SI-NEXT: v_and_b32_e32 v0, 0x8000, v0337; SI-NEXT: v_or_b32_e32 v0, 0x4900, v0338; SI-NEXT: v_readfirstlane_b32 s0, v0339; SI-NEXT: ; return to shader part epilog340;341; VI-LABEL: s_test_copysign_f16_neg10_mag:342; VI: ; %bb.0:343; VI-NEXT: s_and_b32 s0, s0, 0x8000344; VI-NEXT: s_or_b32 s0, s0, 0x4900345; VI-NEXT: ; return to shader part epilog346;347; GFX9-LABEL: s_test_copysign_f16_neg10_mag:348; GFX9: ; %bb.0:349; GFX9-NEXT: s_and_b32 s0, s0, 0x8000350; GFX9-NEXT: s_or_b32 s0, s0, 0x4900351; GFX9-NEXT: ; return to shader part epilog352;353; GFX11-LABEL: s_test_copysign_f16_neg10_mag:354; GFX11: ; %bb.0:355; GFX11-NEXT: s_and_b32 s0, s0, 0x8000356; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)357; GFX11-NEXT: s_or_b32 s0, s0, 0x4900358; GFX11-NEXT: ; return to shader part epilog359 %result = call half @llvm.copysign.f16(half -10.0, half %sign)360 %cast = bitcast half %result to i16361 ret i16 %cast362}363 364define half @v_copysign_f16(half %mag, half %sign) {365; SI-LABEL: v_copysign_f16:366; SI: ; %bb.0:367; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; SI-NEXT: v_cvt_f16_f32_e32 v0, v0369; SI-NEXT: s_brev_b32 s4, -2370; SI-NEXT: v_cvt_f32_f16_e32 v0, v0371; SI-NEXT: v_bfi_b32 v0, s4, v0, v1372; SI-NEXT: s_setpc_b64 s[30:31]373;374; VI-LABEL: v_copysign_f16:375; VI: ; %bb.0:376; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)377; VI-NEXT: s_movk_i32 s4, 0x7fff378; VI-NEXT: v_bfi_b32 v0, s4, v0, v1379; VI-NEXT: s_setpc_b64 s[30:31]380;381; GFX9-LABEL: v_copysign_f16:382; GFX9: ; %bb.0:383; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)384; GFX9-NEXT: s_movk_i32 s4, 0x7fff385; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1386; GFX9-NEXT: s_setpc_b64 s[30:31]387;388; GFX11-LABEL: v_copysign_f16:389; GFX11: ; %bb.0:390; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)391; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1392; GFX11-NEXT: s_setpc_b64 s[30:31]393 %result = call half @llvm.copysign.f16(half %mag, half %sign)394 ret half %result395}396 397define half @v_test_copysign_f16_0(half %mag) {398; SI-LABEL: v_test_copysign_f16_0:399; SI: ; %bb.0:400; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)401; SI-NEXT: v_cvt_f16_f32_e32 v0, v0402; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|403; SI-NEXT: s_setpc_b64 s[30:31]404;405; VI-LABEL: v_test_copysign_f16_0:406; VI: ; %bb.0:407; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)408; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0409; VI-NEXT: s_setpc_b64 s[30:31]410;411; GFX9-LABEL: v_test_copysign_f16_0:412; GFX9: ; %bb.0:413; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)414; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0415; GFX9-NEXT: s_setpc_b64 s[30:31]416;417; GFX11-TRUE16-LABEL: v_test_copysign_f16_0:418; GFX11-TRUE16: ; %bb.0:419; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)420; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l421; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]422;423; GFX11-FAKE16-LABEL: v_test_copysign_f16_0:424; GFX11-FAKE16: ; %bb.0:425; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0427; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]428 %result = call half @llvm.copysign.f16(half %mag, half 0.0)429 ret half %result430}431 432define half @v_test_copysign_f16_1(half %mag) {433; SI-LABEL: v_test_copysign_f16_1:434; SI: ; %bb.0:435; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)436; SI-NEXT: v_cvt_f16_f32_e32 v0, v0437; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|438; SI-NEXT: s_setpc_b64 s[30:31]439;440; VI-LABEL: v_test_copysign_f16_1:441; VI: ; %bb.0:442; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)443; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0444; VI-NEXT: s_setpc_b64 s[30:31]445;446; GFX9-LABEL: v_test_copysign_f16_1:447; GFX9: ; %bb.0:448; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)449; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0450; GFX9-NEXT: s_setpc_b64 s[30:31]451;452; GFX11-TRUE16-LABEL: v_test_copysign_f16_1:453; GFX11-TRUE16: ; %bb.0:454; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)455; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l456; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]457;458; GFX11-FAKE16-LABEL: v_test_copysign_f16_1:459; GFX11-FAKE16: ; %bb.0:460; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)461; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0462; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]463 %result = call half @llvm.copysign.f16(half %mag, half 1.0)464 ret half %result465}466 467define half @v_test_copysign_f16_10(half %mag) {468; SI-LABEL: v_test_copysign_f16_10:469; SI: ; %bb.0:470; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)471; SI-NEXT: v_cvt_f16_f32_e32 v0, v0472; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|473; SI-NEXT: s_setpc_b64 s[30:31]474;475; VI-LABEL: v_test_copysign_f16_10:476; VI: ; %bb.0:477; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)478; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0479; VI-NEXT: s_setpc_b64 s[30:31]480;481; GFX9-LABEL: v_test_copysign_f16_10:482; GFX9: ; %bb.0:483; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)484; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0485; GFX9-NEXT: s_setpc_b64 s[30:31]486;487; GFX11-TRUE16-LABEL: v_test_copysign_f16_10:488; GFX11-TRUE16: ; %bb.0:489; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)490; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l491; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]492;493; GFX11-FAKE16-LABEL: v_test_copysign_f16_10:494; GFX11-FAKE16: ; %bb.0:495; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)496; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0497; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]498 %result = call half @llvm.copysign.f16(half %mag, half 10.0)499 ret half %result500}501 502define half @v_test_copysign_f16_neg1(half %mag) {503; SI-LABEL: v_test_copysign_f16_neg1:504; SI: ; %bb.0:505; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)506; SI-NEXT: v_cvt_f16_f32_e32 v0, v0507; SI-NEXT: v_cvt_f32_f16_e64 v0, -|v0|508; SI-NEXT: s_setpc_b64 s[30:31]509;510; VI-LABEL: v_test_copysign_f16_neg1:511; VI: ; %bb.0:512; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)513; VI-NEXT: v_or_b32_e32 v0, 0x8000, v0514; VI-NEXT: s_setpc_b64 s[30:31]515;516; GFX9-LABEL: v_test_copysign_f16_neg1:517; GFX9: ; %bb.0:518; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)519; GFX9-NEXT: v_or_b32_e32 v0, 0x8000, v0520; GFX9-NEXT: s_setpc_b64 s[30:31]521;522; GFX11-TRUE16-LABEL: v_test_copysign_f16_neg1:523; GFX11-TRUE16: ; %bb.0:524; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)525; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l526; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]527;528; GFX11-FAKE16-LABEL: v_test_copysign_f16_neg1:529; GFX11-FAKE16: ; %bb.0:530; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)531; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, 0x8000, v0532; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]533 %result = call half @llvm.copysign.f16(half %mag, half -1.0)534 ret half %result535}536 537define half @v_test_copysign_f16_neg10(half %mag) {538; SI-LABEL: v_test_copysign_f16_neg10:539; SI: ; %bb.0:540; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)541; SI-NEXT: v_cvt_f16_f32_e32 v0, v0542; SI-NEXT: v_cvt_f32_f16_e64 v0, -|v0|543; SI-NEXT: s_setpc_b64 s[30:31]544;545; VI-LABEL: v_test_copysign_f16_neg10:546; VI: ; %bb.0:547; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)548; VI-NEXT: v_or_b32_e32 v0, 0x8000, v0549; VI-NEXT: s_setpc_b64 s[30:31]550;551; GFX9-LABEL: v_test_copysign_f16_neg10:552; GFX9: ; %bb.0:553; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)554; GFX9-NEXT: v_or_b32_e32 v0, 0x8000, v0555; GFX9-NEXT: s_setpc_b64 s[30:31]556;557; GFX11-TRUE16-LABEL: v_test_copysign_f16_neg10:558; GFX11-TRUE16: ; %bb.0:559; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)560; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l561; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]562;563; GFX11-FAKE16-LABEL: v_test_copysign_f16_neg10:564; GFX11-FAKE16: ; %bb.0:565; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)566; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, 0x8000, v0567; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]568 %result = call half @llvm.copysign.f16(half %mag, half -10.0)569 ret half %result570}571 572define float @v_copysign_out_f32_mag_f16_sign_f32(half %mag, float %sign) {573; SI-LABEL: v_copysign_out_f32_mag_f16_sign_f32:574; SI: ; %bb.0:575; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)576; SI-NEXT: s_brev_b32 s4, -2577; SI-NEXT: v_bfi_b32 v0, s4, v0, v1578; SI-NEXT: s_setpc_b64 s[30:31]579;580; VI-LABEL: v_copysign_out_f32_mag_f16_sign_f32:581; VI: ; %bb.0:582; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)583; VI-NEXT: v_cvt_f32_f16_e32 v0, v0584; VI-NEXT: s_brev_b32 s4, -2585; VI-NEXT: v_bfi_b32 v0, s4, v0, v1586; VI-NEXT: s_setpc_b64 s[30:31]587;588; GFX9-LABEL: v_copysign_out_f32_mag_f16_sign_f32:589; GFX9: ; %bb.0:590; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)591; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0592; GFX9-NEXT: s_brev_b32 s4, -2593; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1594; GFX9-NEXT: s_setpc_b64 s[30:31]595;596; GFX11-TRUE16-LABEL: v_copysign_out_f32_mag_f16_sign_f32:597; GFX11-TRUE16: ; %bb.0:598; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)599; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l600; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)601; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1602; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]603;604; GFX11-FAKE16-LABEL: v_copysign_out_f32_mag_f16_sign_f32:605; GFX11-FAKE16: ; %bb.0:606; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)607; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0608; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)609; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1610; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]611 %mag.ext = fpext half %mag to float612 %out = call float @llvm.copysign.f32(float %mag.ext, float %sign)613 ret float %out614}615 616define double @v_copysign_out_f64_mag_f16_sign_f64(half %mag, double %sign) {617; SI-LABEL: v_copysign_out_f64_mag_f16_sign_f64:618; SI: ; %bb.0:619; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)620; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0621; SI-NEXT: s_brev_b32 s4, -2622; SI-NEXT: v_bfi_b32 v1, s4, v1, v2623; SI-NEXT: s_setpc_b64 s[30:31]624;625; VI-LABEL: v_copysign_out_f64_mag_f16_sign_f64:626; VI: ; %bb.0:627; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)628; VI-NEXT: v_cvt_f32_f16_e32 v0, v0629; VI-NEXT: s_brev_b32 s4, -2630; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0631; VI-NEXT: v_bfi_b32 v1, s4, v1, v2632; VI-NEXT: s_setpc_b64 s[30:31]633;634; GFX9-LABEL: v_copysign_out_f64_mag_f16_sign_f64:635; GFX9: ; %bb.0:636; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)637; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0638; GFX9-NEXT: s_brev_b32 s4, -2639; GFX9-NEXT: v_cvt_f64_f32_e32 v[0:1], v0640; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v2641; GFX9-NEXT: s_setpc_b64 s[30:31]642;643; GFX11-TRUE16-LABEL: v_copysign_out_f64_mag_f16_sign_f64:644; GFX11-TRUE16: ; %bb.0:645; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)646; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l647; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)648; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0649; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2650; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]651;652; GFX11-FAKE16-LABEL: v_copysign_out_f64_mag_f16_sign_f64:653; GFX11-FAKE16: ; %bb.0:654; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)655; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0656; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)657; GFX11-FAKE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0658; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2659; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]660 %mag.ext = fpext half %mag to double661 %out = call double @llvm.copysign.f64(double %mag.ext, double %sign)662 ret double %out663}664 665define float @v_copysign_out_f32_mag_f32_sign_f16(float %mag, half %sign) {666; SI-LABEL: v_copysign_out_f32_mag_f32_sign_f16:667; SI: ; %bb.0:668; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)669; SI-NEXT: s_brev_b32 s4, -2670; SI-NEXT: v_bfi_b32 v0, s4, v0, v1671; SI-NEXT: s_setpc_b64 s[30:31]672;673; VI-LABEL: v_copysign_out_f32_mag_f32_sign_f16:674; VI: ; %bb.0:675; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)676; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1677; VI-NEXT: s_brev_b32 s4, -2678; VI-NEXT: v_bfi_b32 v0, s4, v0, v1679; VI-NEXT: s_setpc_b64 s[30:31]680;681; GFX9-LABEL: v_copysign_out_f32_mag_f32_sign_f16:682; GFX9: ; %bb.0:683; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)684; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1685; GFX9-NEXT: s_brev_b32 s4, -2686; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1687; GFX9-NEXT: s_setpc_b64 s[30:31]688;689; GFX11-TRUE16-LABEL: v_copysign_out_f32_mag_f32_sign_f16:690; GFX11-TRUE16: ; %bb.0:691; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)692; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l693; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)694; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1695; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]696;697; GFX11-FAKE16-LABEL: v_copysign_out_f32_mag_f32_sign_f16:698; GFX11-FAKE16: ; %bb.0:699; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)700; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1701; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)702; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1703; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]704 %sign.ext = fpext half %sign to float705 %out = call float @llvm.copysign.f32(float %mag, float %sign.ext)706 ret float %out707}708 709define double @v_copysign_out_f64_mag_f64_sign_f16(double %mag, half %sign) {710; SI-LABEL: v_copysign_out_f64_mag_f64_sign_f16:711; SI: ; %bb.0:712; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)713; SI-NEXT: s_brev_b32 s4, -2714; SI-NEXT: v_bfi_b32 v1, s4, v1, v2715; SI-NEXT: s_setpc_b64 s[30:31]716;717; VI-LABEL: v_copysign_out_f64_mag_f64_sign_f16:718; VI: ; %bb.0:719; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)720; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2721; VI-NEXT: s_brev_b32 s4, -2722; VI-NEXT: v_bfi_b32 v1, s4, v1, v2723; VI-NEXT: s_setpc_b64 s[30:31]724;725; GFX9-LABEL: v_copysign_out_f64_mag_f64_sign_f16:726; GFX9: ; %bb.0:727; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)728; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2729; GFX9-NEXT: s_brev_b32 s4, -2730; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v2731; GFX9-NEXT: s_setpc_b64 s[30:31]732;733; GFX11-TRUE16-LABEL: v_copysign_out_f64_mag_f64_sign_f16:734; GFX11-TRUE16: ; %bb.0:735; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)736; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v2.l737; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)738; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2739; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]740;741; GFX11-FAKE16-LABEL: v_copysign_out_f64_mag_f64_sign_f16:742; GFX11-FAKE16: ; %bb.0:743; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)744; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2745; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)746; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2747; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]748 %sign.ext = fpext half %sign to double749 %out = call double @llvm.copysign.f64(double %mag, double %sign.ext)750 ret double %out751}752 753define half @v_copysign_out_f16_mag_f16_sign_f32(half %mag, float %sign) {754; SI-LABEL: v_copysign_out_f16_mag_f16_sign_f32:755; SI: ; %bb.0:756; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)757; SI-NEXT: v_cvt_f16_f32_e32 v0, v0758; SI-NEXT: s_brev_b32 s4, -2759; SI-NEXT: v_cvt_f32_f16_e32 v0, v0760; SI-NEXT: v_bfi_b32 v0, s4, v0, v1761; SI-NEXT: s_setpc_b64 s[30:31]762;763; VI-LABEL: v_copysign_out_f16_mag_f16_sign_f32:764; VI: ; %bb.0:765; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)766; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1767; VI-NEXT: s_movk_i32 s4, 0x7fff768; VI-NEXT: v_bfi_b32 v0, s4, v0, v1769; VI-NEXT: s_setpc_b64 s[30:31]770;771; GFX9-LABEL: v_copysign_out_f16_mag_f16_sign_f32:772; GFX9: ; %bb.0:773; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)774; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1775; GFX9-NEXT: s_movk_i32 s4, 0x7fff776; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1777; GFX9-NEXT: s_setpc_b64 s[30:31]778;779; GFX11-LABEL: v_copysign_out_f16_mag_f16_sign_f32:780; GFX11: ; %bb.0:781; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)782; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1783; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)784; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1785; GFX11-NEXT: s_setpc_b64 s[30:31]786 %sign.trunc = fptrunc float %sign to half787 %out = call half @llvm.copysign.f16(half %mag, half %sign.trunc)788 ret half %out789}790 791define half @v_copysign_out_f16_mag_f16_sign_f64(half %mag, double %sign) {792; SI-LABEL: v_copysign_out_f16_mag_f16_sign_f64:793; SI: ; %bb.0:794; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)795; SI-NEXT: v_cvt_f16_f32_e32 v0, v0796; SI-NEXT: s_brev_b32 s4, -2797; SI-NEXT: v_cvt_f32_f16_e32 v0, v0798; SI-NEXT: v_bfi_b32 v0, s4, v0, v2799; SI-NEXT: s_setpc_b64 s[30:31]800;801; VI-LABEL: v_copysign_out_f16_mag_f16_sign_f64:802; VI: ; %bb.0:803; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)804; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2805; VI-NEXT: s_movk_i32 s4, 0x7fff806; VI-NEXT: v_bfi_b32 v0, s4, v0, v1807; VI-NEXT: s_setpc_b64 s[30:31]808;809; GFX9-LABEL: v_copysign_out_f16_mag_f16_sign_f64:810; GFX9: ; %bb.0:811; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)812; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v2813; GFX9-NEXT: s_movk_i32 s4, 0x7fff814; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1815; GFX9-NEXT: s_setpc_b64 s[30:31]816;817; GFX11-LABEL: v_copysign_out_f16_mag_f16_sign_f64:818; GFX11: ; %bb.0:819; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)820; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2821; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)822; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1823; GFX11-NEXT: s_setpc_b64 s[30:31]824 %sign.trunc = fptrunc double %sign to half825 %out = call half @llvm.copysign.f16(half %mag, half %sign.trunc)826 ret half %out827}828 829define half @v_copysign_out_f16_mag_f32_sign_f16(float %mag, half %sign) {830; SI-LABEL: v_copysign_out_f16_mag_f32_sign_f16:831; SI: ; %bb.0:832; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)833; SI-NEXT: v_cvt_f16_f32_e32 v0, v0834; SI-NEXT: s_brev_b32 s4, -2835; SI-NEXT: v_cvt_f32_f16_e32 v0, v0836; SI-NEXT: v_bfi_b32 v0, s4, v0, v1837; SI-NEXT: s_setpc_b64 s[30:31]838;839; VI-LABEL: v_copysign_out_f16_mag_f32_sign_f16:840; VI: ; %bb.0:841; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)842; VI-NEXT: v_cvt_f16_f32_e32 v0, v0843; VI-NEXT: s_movk_i32 s4, 0x7fff844; VI-NEXT: v_bfi_b32 v0, s4, v0, v1845; VI-NEXT: s_setpc_b64 s[30:31]846;847; GFX9-LABEL: v_copysign_out_f16_mag_f32_sign_f16:848; GFX9: ; %bb.0:849; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)850; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0851; GFX9-NEXT: s_movk_i32 s4, 0x7fff852; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v1853; GFX9-NEXT: s_setpc_b64 s[30:31]854;855; GFX11-TRUE16-LABEL: v_copysign_out_f16_mag_f32_sign_f16:856; GFX11-TRUE16: ; %bb.0:857; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)858; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0859; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)860; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1861; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]862;863; GFX11-FAKE16-LABEL: v_copysign_out_f16_mag_f32_sign_f16:864; GFX11-FAKE16: ; %bb.0:865; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)866; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0867; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)868; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1869; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]870 %mag.trunc = fptrunc float %mag to half871 %out = call half @llvm.copysign.f16(half %mag.trunc, half %sign)872 ret half %out873}874 875define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {876; SI-LABEL: v_copysign_out_f16_mag_f64_sign_f16:877; SI: ; %bb.0:878; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)879; SI-NEXT: v_and_b32_e32 v3, 0x1ff, v1880; SI-NEXT: v_or_b32_e32 v0, v3, v0881; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0882; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v1883; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc884; SI-NEXT: v_and_b32_e32 v3, 0xffe, v3885; SI-NEXT: v_bfe_u32 v4, v1, 20, 11886; SI-NEXT: v_or_b32_e32 v0, v3, v0887; SI-NEXT: v_sub_i32_e32 v5, vcc, 0x3f1, v4888; SI-NEXT: v_or_b32_e32 v3, 0x1000, v0889; SI-NEXT: v_med3_i32 v5, v5, 0, 13890; SI-NEXT: v_lshrrev_b32_e32 v6, v5, v3891; SI-NEXT: v_lshlrev_b32_e32 v5, v5, v6892; SI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3893; SI-NEXT: s_movk_i32 s4, 0xfc10894; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc895; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v4896; SI-NEXT: v_lshlrev_b32_e32 v5, 12, v4897; SI-NEXT: v_or_b32_e32 v3, v6, v3898; SI-NEXT: v_or_b32_e32 v5, v0, v5899; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4900; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc901; SI-NEXT: v_and_b32_e32 v5, 7, v3902; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5903; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc904; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5905; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc906; SI-NEXT: v_or_b32_e32 v5, v5, v6907; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3908; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v5909; SI-NEXT: v_mov_b32_e32 v5, 0x7c00910; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4911; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc912; SI-NEXT: v_mov_b32_e32 v6, 0x7e00913; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0914; SI-NEXT: s_movk_i32 s4, 0x40f915; SI-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc916; SI-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4917; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1918; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc919; SI-NEXT: v_and_b32_e32 v1, 0x8000, v1920; SI-NEXT: v_or_b32_e32 v0, v1, v0921; SI-NEXT: v_cvt_f32_f16_e32 v0, v0922; SI-NEXT: s_brev_b32 s4, -2923; SI-NEXT: v_bfi_b32 v0, s4, v0, v2924; SI-NEXT: s_setpc_b64 s[30:31]925;926; VI-LABEL: v_copysign_out_f16_mag_f64_sign_f16:927; VI: ; %bb.0:928; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)929; VI-NEXT: v_and_b32_e32 v3, 0x1ff, v1930; VI-NEXT: v_or_b32_e32 v0, v3, v0931; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0932; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v1933; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc934; VI-NEXT: v_and_b32_e32 v3, 0xffe, v3935; VI-NEXT: v_bfe_u32 v1, v1, 20, 11936; VI-NEXT: v_or_b32_e32 v0, v3, v0937; VI-NEXT: v_sub_u32_e32 v4, vcc, 0x3f1, v1938; VI-NEXT: v_or_b32_e32 v3, 0x1000, v0939; VI-NEXT: v_med3_i32 v4, v4, 0, 13940; VI-NEXT: v_lshrrev_b32_e32 v5, v4, v3941; VI-NEXT: v_lshlrev_b32_e32 v4, v4, v5942; VI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v3943; VI-NEXT: s_movk_i32 s4, 0xfc10944; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc945; VI-NEXT: v_add_u32_e32 v1, vcc, s4, v1946; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v1947; VI-NEXT: v_or_b32_e32 v3, v5, v3948; VI-NEXT: v_or_b32_e32 v4, v0, v4949; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1950; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc951; VI-NEXT: v_and_b32_e32 v4, 7, v3952; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4953; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc954; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4955; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc956; VI-NEXT: v_or_b32_e32 v4, v4, v5957; VI-NEXT: v_lshrrev_b32_e32 v3, 2, v3958; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v4959; VI-NEXT: v_mov_b32_e32 v4, 0x7c00960; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v1961; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc962; VI-NEXT: v_mov_b32_e32 v5, 0x7e00963; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0964; VI-NEXT: s_movk_i32 s4, 0x40f965; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc966; VI-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1967; VI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc968; VI-NEXT: s_movk_i32 s4, 0x7fff969; VI-NEXT: v_bfi_b32 v0, s4, v0, v2970; VI-NEXT: s_setpc_b64 s[30:31]971;972; GFX9-LABEL: v_copysign_out_f16_mag_f64_sign_f16:973; GFX9: ; %bb.0:974; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)975; GFX9-NEXT: s_movk_i32 s4, 0x1ff976; GFX9-NEXT: v_and_or_b32 v0, v1, s4, v0977; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0978; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc979; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v1980; GFX9-NEXT: s_movk_i32 s4, 0xffe981; GFX9-NEXT: v_bfe_u32 v1, v1, 20, 11982; GFX9-NEXT: v_and_or_b32 v0, v3, s4, v0983; GFX9-NEXT: v_sub_u32_e32 v4, 0x3f1, v1984; GFX9-NEXT: v_or_b32_e32 v3, 0x1000, v0985; GFX9-NEXT: v_med3_i32 v4, v4, 0, 13986; GFX9-NEXT: v_lshrrev_b32_e32 v5, v4, v3987; GFX9-NEXT: v_lshlrev_b32_e32 v4, v4, v5988; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v4, v3989; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc990; GFX9-NEXT: v_add_u32_e32 v1, 0xfffffc10, v1991; GFX9-NEXT: v_or_b32_e32 v3, v5, v3992; GFX9-NEXT: v_lshl_or_b32 v4, v1, 12, v0993; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1994; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc995; GFX9-NEXT: v_and_b32_e32 v4, 7, v3996; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4997; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc998; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4999; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc1000; GFX9-NEXT: v_or_b32_e32 v4, v4, v51001; GFX9-NEXT: v_lshrrev_b32_e32 v3, 2, v31002; GFX9-NEXT: v_add_u32_e32 v3, v3, v41003; GFX9-NEXT: v_mov_b32_e32 v4, 0x7c001004; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v11005; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc1006; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e001007; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01008; GFX9-NEXT: s_movk_i32 s4, 0x40f1009; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc1010; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s4, v11011; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc1012; GFX9-NEXT: s_movk_i32 s4, 0x7fff1013; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v21014; GFX9-NEXT: s_setpc_b64 s[30:31]1015;1016; GFX11-TRUE16-LABEL: v_copysign_out_f16_mag_f64_sign_f16:1017; GFX11-TRUE16: ; %bb.0:1018; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1019; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v01020; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v11021; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v1, 20, 111022; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1023; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v01024; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v11025; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0xfffffc10, v11026; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1027; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)1028; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v3, v01029; GFX11-TRUE16-NEXT: v_med3_i32 v3, v4, 0, 131030; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1031; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x1000, v01032; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v41033; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1034; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v3, v51035; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v41036; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v1, 12, v01037; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo1038; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v11039; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1040; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v5, v31041; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo1042; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1043; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 7, v31044; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 2, v31045; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v41046; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo1047; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v41048; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo1049; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v01050; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)1051; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v51052; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0x7e001053; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, 0x7c00, v5 :: v_dual_add_nc_u32 v3, v3, v41054; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v11055; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)1056; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo1057; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v11058; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l1059; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo1060; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1061; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v11062; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1063;1064; GFX11-FAKE16-LABEL: v_copysign_out_f16_mag_f64_sign_f16:1065; GFX11-FAKE16: ; %bb.0:1066; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1067; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v01068; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v11069; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v1, 20, 111070; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1071; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v01072; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v11073; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0xfffffc10, v11074; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo1075; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)1076; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v3, v01077; GFX11-FAKE16-NEXT: v_med3_i32 v3, v4, 0, 131078; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1079; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x1000, v01080; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v41081; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1082; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v3, v51083; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v41084; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 12, v01085; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo1086; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v11087; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1088; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v31089; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo1090; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1091; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 7, v31092; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 2, v31093; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v41094; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo1095; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v41096; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo1097; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v11098; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1099; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v51100; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0x7e00 :: v_dual_add_nc_u32 v3, v3, v41101; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)1102; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo1103; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v01104; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v4, vcc_lo1105; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v11106; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1107; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo1108; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v21109; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1110 %mag.trunc = fptrunc double %mag to half1111 %result = call half @llvm.copysign.f16(half %mag.trunc, half %sign)1112 ret half %result1113}1114 1115define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, half inreg %sign) {1116; SI-LABEL: s_copysign_out_f16_mag_f64_sign_f16:1117; SI: ; %bb.0:1118; SI-NEXT: s_and_b32 s3, s1, 0x1ff1119; SI-NEXT: s_or_b32 s0, s3, s01120; SI-NEXT: s_cselect_b64 s[4:5], -1, 01121; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]1122; SI-NEXT: s_lshr_b32 s0, s1, 81123; SI-NEXT: s_bfe_u32 s4, s1, 0xb00141124; SI-NEXT: s_and_b32 s0, s0, 0xffe1125; SI-NEXT: v_readfirstlane_b32 s3, v01126; SI-NEXT: s_sub_i32 s5, 0x3f1, s41127; SI-NEXT: s_or_b32 s0, s0, s31128; SI-NEXT: v_med3_i32 v0, s5, 0, 131129; SI-NEXT: s_or_b32 s3, s0, 0x10001130; SI-NEXT: v_readfirstlane_b32 s5, v01131; SI-NEXT: s_lshr_b32 s6, s3, s51132; SI-NEXT: s_lshl_b32 s5, s6, s51133; SI-NEXT: s_cmp_lg_u32 s5, s31134; SI-NEXT: s_cselect_b32 s3, 1, 01135; SI-NEXT: s_addk_i32 s4, 0xfc101136; SI-NEXT: s_lshl_b32 s5, s4, 121137; SI-NEXT: s_or_b32 s3, s6, s31138; SI-NEXT: s_or_b32 s5, s0, s51139; SI-NEXT: s_cmp_lt_i32 s4, 11140; SI-NEXT: s_cselect_b32 s3, s3, s51141; SI-NEXT: s_and_b32 s5, s3, 71142; SI-NEXT: s_cmp_gt_i32 s5, 51143; SI-NEXT: s_cselect_b32 s6, 1, 01144; SI-NEXT: s_cmp_eq_u32 s5, 31145; SI-NEXT: s_cselect_b32 s5, 1, 01146; SI-NEXT: s_or_b32 s5, s5, s61147; SI-NEXT: s_lshr_b32 s3, s3, 21148; SI-NEXT: s_add_i32 s3, s3, s51149; SI-NEXT: s_cmp_lt_i32 s4, 311150; SI-NEXT: s_cselect_b32 s3, s3, 0x7c001151; SI-NEXT: s_cmp_lg_u32 s0, 01152; SI-NEXT: s_movk_i32 s0, 0x7e001153; SI-NEXT: s_cselect_b32 s0, s0, 0x7c001154; SI-NEXT: s_cmpk_eq_i32 s4, 0x40f1155; SI-NEXT: s_cselect_b32 s0, s0, s31156; SI-NEXT: s_lshr_b32 s1, s1, 161157; SI-NEXT: s_and_b32 s1, s1, 0x80001158; SI-NEXT: s_or_b32 s0, s1, s01159; SI-NEXT: v_cvt_f32_f16_e32 v0, s01160; SI-NEXT: s_brev_b32 s0, -21161; SI-NEXT: v_mov_b32_e32 v1, s21162; SI-NEXT: v_bfi_b32 v0, s0, v0, v11163; SI-NEXT: v_cvt_f16_f32_e32 v0, v01164; SI-NEXT: v_readfirstlane_b32 s0, v01165; SI-NEXT: ; return to shader part epilog1166;1167; VI-LABEL: s_copysign_out_f16_mag_f64_sign_f16:1168; VI: ; %bb.0:1169; VI-NEXT: s_and_b32 s3, s1, 0x1ff1170; VI-NEXT: s_or_b32 s0, s3, s01171; VI-NEXT: s_cselect_b64 s[4:5], -1, 01172; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]1173; VI-NEXT: s_lshr_b32 s0, s1, 81174; VI-NEXT: s_bfe_u32 s1, s1, 0xb00141175; VI-NEXT: s_and_b32 s0, s0, 0xffe1176; VI-NEXT: v_readfirstlane_b32 s3, v01177; VI-NEXT: s_sub_i32 s4, 0x3f1, s11178; VI-NEXT: s_or_b32 s0, s0, s31179; VI-NEXT: v_med3_i32 v0, s4, 0, 131180; VI-NEXT: s_or_b32 s3, s0, 0x10001181; VI-NEXT: v_readfirstlane_b32 s4, v01182; VI-NEXT: s_lshr_b32 s5, s3, s41183; VI-NEXT: s_lshl_b32 s4, s5, s41184; VI-NEXT: s_cmp_lg_u32 s4, s31185; VI-NEXT: s_cselect_b32 s3, 1, 01186; VI-NEXT: s_addk_i32 s1, 0xfc101187; VI-NEXT: s_lshl_b32 s4, s1, 121188; VI-NEXT: s_or_b32 s3, s5, s31189; VI-NEXT: s_or_b32 s4, s0, s41190; VI-NEXT: s_cmp_lt_i32 s1, 11191; VI-NEXT: s_cselect_b32 s3, s3, s41192; VI-NEXT: s_and_b32 s4, s3, 71193; VI-NEXT: s_cmp_gt_i32 s4, 51194; VI-NEXT: s_cselect_b32 s5, 1, 01195; VI-NEXT: s_cmp_eq_u32 s4, 31196; VI-NEXT: s_cselect_b32 s4, 1, 01197; VI-NEXT: s_or_b32 s4, s4, s51198; VI-NEXT: s_lshr_b32 s3, s3, 21199; VI-NEXT: s_add_i32 s3, s3, s41200; VI-NEXT: s_cmp_lt_i32 s1, 311201; VI-NEXT: s_cselect_b32 s3, s3, 0x7c001202; VI-NEXT: s_cmp_lg_u32 s0, 01203; VI-NEXT: s_movk_i32 s0, 0x7e001204; VI-NEXT: s_cselect_b32 s0, s0, 0x7c001205; VI-NEXT: s_cmpk_eq_i32 s1, 0x40f1206; VI-NEXT: s_cselect_b32 s0, s0, s31207; VI-NEXT: s_movk_i32 s1, 0x7fff1208; VI-NEXT: v_mov_b32_e32 v0, s01209; VI-NEXT: v_mov_b32_e32 v1, s21210; VI-NEXT: v_bfi_b32 v0, s1, v0, v11211; VI-NEXT: v_readfirstlane_b32 s0, v01212; VI-NEXT: ; return to shader part epilog1213;1214; GFX9-LABEL: s_copysign_out_f16_mag_f64_sign_f16:1215; GFX9: ; %bb.0:1216; GFX9-NEXT: s_and_b32 s3, s1, 0x1ff1217; GFX9-NEXT: s_or_b32 s0, s3, s01218; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 01219; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]1220; GFX9-NEXT: s_lshr_b32 s0, s1, 81221; GFX9-NEXT: s_bfe_u32 s1, s1, 0xb00141222; GFX9-NEXT: s_and_b32 s0, s0, 0xffe1223; GFX9-NEXT: v_readfirstlane_b32 s3, v01224; GFX9-NEXT: s_sub_i32 s4, 0x3f1, s11225; GFX9-NEXT: s_or_b32 s0, s0, s31226; GFX9-NEXT: v_med3_i32 v0, s4, 0, 131227; GFX9-NEXT: s_or_b32 s3, s0, 0x10001228; GFX9-NEXT: v_readfirstlane_b32 s4, v01229; GFX9-NEXT: s_lshr_b32 s5, s3, s41230; GFX9-NEXT: s_lshl_b32 s4, s5, s41231; GFX9-NEXT: s_cmp_lg_u32 s4, s31232; GFX9-NEXT: s_cselect_b32 s3, 1, 01233; GFX9-NEXT: s_addk_i32 s1, 0xfc101234; GFX9-NEXT: s_lshl_b32 s4, s1, 121235; GFX9-NEXT: s_or_b32 s3, s5, s31236; GFX9-NEXT: s_or_b32 s4, s0, s41237; GFX9-NEXT: s_cmp_lt_i32 s1, 11238; GFX9-NEXT: s_cselect_b32 s3, s3, s41239; GFX9-NEXT: s_and_b32 s4, s3, 71240; GFX9-NEXT: s_cmp_gt_i32 s4, 51241; GFX9-NEXT: s_cselect_b32 s5, 1, 01242; GFX9-NEXT: s_cmp_eq_u32 s4, 31243; GFX9-NEXT: s_cselect_b32 s4, 1, 01244; GFX9-NEXT: s_or_b32 s4, s4, s51245; GFX9-NEXT: s_lshr_b32 s3, s3, 21246; GFX9-NEXT: s_add_i32 s3, s3, s41247; GFX9-NEXT: s_cmp_lt_i32 s1, 311248; GFX9-NEXT: s_cselect_b32 s3, s3, 0x7c001249; GFX9-NEXT: s_cmp_lg_u32 s0, 01250; GFX9-NEXT: s_movk_i32 s0, 0x7e001251; GFX9-NEXT: s_cselect_b32 s0, s0, 0x7c001252; GFX9-NEXT: s_cmpk_eq_i32 s1, 0x40f1253; GFX9-NEXT: s_cselect_b32 s0, s0, s31254; GFX9-NEXT: s_movk_i32 s1, 0x7fff1255; GFX9-NEXT: v_mov_b32_e32 v0, s01256; GFX9-NEXT: v_mov_b32_e32 v1, s21257; GFX9-NEXT: v_bfi_b32 v0, s1, v0, v11258; GFX9-NEXT: v_readfirstlane_b32 s0, v01259; GFX9-NEXT: ; return to shader part epilog1260;1261; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f64_sign_f16:1262; GFX11-TRUE16: ; %bb.0:1263; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, 0x1ff1264; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)1265; GFX11-TRUE16-NEXT: s_or_b32 s0, s3, s01266; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 01267; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s01268; GFX11-TRUE16-NEXT: s_bfe_u32 s0, s1, 0xb00141269; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 81270; GFX11-TRUE16-NEXT: s_sub_i32 s3, 0x3f1, s01271; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xffe1272; GFX11-TRUE16-NEXT: v_med3_i32 v1, s3, 0, 131273; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v01274; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)1275; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v11276; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s31277; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s21278; GFX11-TRUE16-NEXT: s_or_b32 s3, s1, 0x10001279; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s3, s41280; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1281; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s5, s41282; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s4, s31283; GFX11-TRUE16-NEXT: s_cselect_b32 s3, 1, 01284; GFX11-TRUE16-NEXT: s_addk_i32 s0, 0xfc101285; GFX11-TRUE16-NEXT: s_or_b32 s3, s5, s31286; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s0, 121287; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)1288; GFX11-TRUE16-NEXT: s_or_b32 s4, s1, s41289; GFX11-TRUE16-NEXT: s_cmp_lt_i32 s0, 11290; GFX11-TRUE16-NEXT: s_cselect_b32 s3, s3, s41291; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 71292; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1293; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s4, 51294; GFX11-TRUE16-NEXT: s_cselect_b32 s5, 1, 01295; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 31296; GFX11-TRUE16-NEXT: s_cselect_b32 s4, 1, 01297; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 21298; GFX11-TRUE16-NEXT: s_or_b32 s4, s4, s51299; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1300; GFX11-TRUE16-NEXT: s_add_i32 s3, s3, s41301; GFX11-TRUE16-NEXT: s_cmp_lt_i32 s0, 311302; GFX11-TRUE16-NEXT: s_movk_i32 s4, 0x7e001303; GFX11-TRUE16-NEXT: s_cselect_b32 s3, s3, 0x7c001304; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s1, 01305; GFX11-TRUE16-NEXT: s_cselect_b32 s1, s4, 0x7c001306; GFX11-TRUE16-NEXT: s_cmpk_eq_i32 s0, 0x40f1307; GFX11-TRUE16-NEXT: s_cselect_b32 s0, s1, s31308; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)1309; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s01310; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v11311; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1312; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v01313; GFX11-TRUE16-NEXT: ; return to shader part epilog1314;1315; GFX11-FAKE16-LABEL: s_copysign_out_f16_mag_f64_sign_f16:1316; GFX11-FAKE16: ; %bb.0:1317; GFX11-FAKE16-NEXT: s_and_b32 s3, s1, 0x1ff1318; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)1319; GFX11-FAKE16-NEXT: s_or_b32 s0, s3, s01320; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 01321; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s01322; GFX11-FAKE16-NEXT: s_bfe_u32 s0, s1, 0xb00141323; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, 81324; GFX11-FAKE16-NEXT: s_sub_i32 s3, 0x3f1, s01325; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xffe1326; GFX11-FAKE16-NEXT: v_med3_i32 v1, s3, 0, 131327; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v01328; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s21329; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)1330; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v11331; GFX11-FAKE16-NEXT: s_or_b32 s1, s1, s31332; GFX11-FAKE16-NEXT: s_or_b32 s3, s1, 0x10001333; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1334; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s3, s41335; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s5, s41336; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)1337; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s4, s31338; GFX11-FAKE16-NEXT: s_cselect_b32 s3, 1, 01339; GFX11-FAKE16-NEXT: s_addk_i32 s0, 0xfc101340; GFX11-FAKE16-NEXT: s_or_b32 s3, s5, s31341; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s0, 121342; GFX11-FAKE16-NEXT: s_or_b32 s4, s1, s41343; GFX11-FAKE16-NEXT: s_cmp_lt_i32 s0, 11344; GFX11-FAKE16-NEXT: s_cselect_b32 s3, s3, s41345; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1346; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 71347; GFX11-FAKE16-NEXT: s_cmp_gt_i32 s4, 51348; GFX11-FAKE16-NEXT: s_cselect_b32 s5, 1, 01349; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 31350; GFX11-FAKE16-NEXT: s_cselect_b32 s4, 1, 01351; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 21352; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s51353; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1354; GFX11-FAKE16-NEXT: s_add_i32 s3, s3, s41355; GFX11-FAKE16-NEXT: s_cmp_lt_i32 s0, 311356; GFX11-FAKE16-NEXT: s_movk_i32 s4, 0x7e001357; GFX11-FAKE16-NEXT: s_cselect_b32 s3, s3, 0x7c001358; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s1, 01359; GFX11-FAKE16-NEXT: s_cselect_b32 s1, s4, 0x7c001360; GFX11-FAKE16-NEXT: s_cmpk_eq_i32 s0, 0x40f1361; GFX11-FAKE16-NEXT: s_cselect_b32 s0, s1, s31362; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)1363; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, s0, v01364; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v01365; GFX11-FAKE16-NEXT: ; return to shader part epilog1366 %mag.trunc = fptrunc double %mag to half1367 %result = call half @llvm.copysign.f16(half %mag.trunc, half %sign)1368 %cast = bitcast half %result to i161369 ret i16 %cast1370}1371 1372define amdgpu_ps i32 @s_copysign_v2f16(<2 x half> inreg %arg_mag, <2 x half> inreg %arg_sign) {1373; SI-LABEL: s_copysign_v2f16:1374; SI: ; %bb.0:1375; SI-NEXT: v_cvt_f16_f32_e32 v0, s31376; SI-NEXT: v_cvt_f16_f32_e32 v1, s11377; SI-NEXT: v_cvt_f16_f32_e32 v2, s21378; SI-NEXT: v_cvt_f16_f32_e32 v3, s01379; SI-NEXT: v_cvt_f32_f16_e32 v0, v01380; SI-NEXT: v_cvt_f32_f16_e32 v1, v11381; SI-NEXT: v_cvt_f32_f16_e32 v2, v21382; SI-NEXT: v_cvt_f32_f16_e32 v3, v31383; SI-NEXT: s_brev_b32 s0, -21384; SI-NEXT: v_bfi_b32 v0, s0, v1, v01385; SI-NEXT: v_cvt_f16_f32_e32 v0, v01386; SI-NEXT: v_bfi_b32 v1, s0, v3, v21387; SI-NEXT: v_cvt_f16_f32_e32 v1, v11388; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01389; SI-NEXT: v_or_b32_e32 v0, v1, v01390; SI-NEXT: v_readfirstlane_b32 s0, v01391; SI-NEXT: ; return to shader part epilog1392;1393; VI-LABEL: s_copysign_v2f16:1394; VI: ; %bb.0:1395; VI-NEXT: s_mov_b32 s2, 0x7fff7fff1396; VI-NEXT: v_mov_b32_e32 v0, s01397; VI-NEXT: v_mov_b32_e32 v1, s11398; VI-NEXT: v_bfi_b32 v0, s2, v0, v11399; VI-NEXT: v_readfirstlane_b32 s0, v01400; VI-NEXT: ; return to shader part epilog1401;1402; GFX9-LABEL: s_copysign_v2f16:1403; GFX9: ; %bb.0:1404; GFX9-NEXT: s_mov_b32 s2, 0x7fff7fff1405; GFX9-NEXT: v_mov_b32_e32 v0, s01406; GFX9-NEXT: v_mov_b32_e32 v1, s11407; GFX9-NEXT: v_bfi_b32 v0, s2, v0, v11408; GFX9-NEXT: v_readfirstlane_b32 s0, v01409; GFX9-NEXT: ; return to shader part epilog1410;1411; GFX11-LABEL: s_copysign_v2f16:1412; GFX11: ; %bb.0:1413; GFX11-NEXT: v_mov_b32_e32 v0, s11414; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1415; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v01416; GFX11-NEXT: v_readfirstlane_b32 s0, v01417; GFX11-NEXT: ; return to shader part epilog1418 %out = call <2 x half> @llvm.copysign.v2f16(<2 x half> %arg_mag, <2 x half> %arg_sign)1419 %cast = bitcast <2 x half> %out to i321420 ret i32 %cast1421}1422 1423define amdgpu_ps <3 x i16> @s_copysign_v3f16(<3 x half> inreg %arg_mag, <3 x half> inreg %arg_sign) {1424; SI-LABEL: s_copysign_v3f16:1425; SI: ; %bb.0:1426; SI-NEXT: v_cvt_f16_f32_e32 v2, s41427; SI-NEXT: v_cvt_f16_f32_e32 v3, s11428; SI-NEXT: v_cvt_f16_f32_e32 v4, s51429; SI-NEXT: v_cvt_f16_f32_e32 v5, s21430; SI-NEXT: v_cvt_f16_f32_e32 v0, s31431; SI-NEXT: v_cvt_f16_f32_e32 v1, s01432; SI-NEXT: v_cvt_f32_f16_e32 v2, v21433; SI-NEXT: v_cvt_f32_f16_e32 v3, v31434; SI-NEXT: v_cvt_f32_f16_e32 v4, v41435; SI-NEXT: v_cvt_f32_f16_e32 v5, v51436; SI-NEXT: v_cvt_f32_f16_e32 v0, v01437; SI-NEXT: v_cvt_f32_f16_e32 v1, v11438; SI-NEXT: s_brev_b32 s0, -21439; SI-NEXT: v_bfi_b32 v2, s0, v3, v21440; SI-NEXT: v_cvt_f16_f32_e32 v2, v21441; SI-NEXT: v_bfi_b32 v3, s0, v5, v41442; SI-NEXT: v_bfi_b32 v0, s0, v1, v01443; SI-NEXT: v_cvt_f16_f32_e32 v1, v31444; SI-NEXT: v_cvt_f16_f32_e32 v4, v01445; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v21446; SI-NEXT: v_lshr_b64 v[2:3], v[0:1], 161447; SI-NEXT: v_or_b32_e32 v4, v4, v01448; SI-NEXT: v_readfirstlane_b32 s0, v41449; SI-NEXT: v_readfirstlane_b32 s1, v21450; SI-NEXT: v_readfirstlane_b32 s2, v11451; SI-NEXT: ; return to shader part epilog1452;1453; VI-LABEL: s_copysign_v3f16:1454; VI: ; %bb.0:1455; VI-NEXT: s_mov_b32 s4, 0x7fff7fff1456; VI-NEXT: v_mov_b32_e32 v0, s11457; VI-NEXT: v_mov_b32_e32 v1, s31458; VI-NEXT: v_bfi_b32 v0, s4, v0, v11459; VI-NEXT: v_mov_b32_e32 v1, s01460; VI-NEXT: v_mov_b32_e32 v2, s21461; VI-NEXT: v_bfi_b32 v1, s4, v1, v21462; VI-NEXT: v_readfirstlane_b32 s0, v11463; VI-NEXT: v_readfirstlane_b32 s1, v01464; VI-NEXT: ; return to shader part epilog1465;1466; GFX9-LABEL: s_copysign_v3f16:1467; GFX9: ; %bb.0:1468; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff1469; GFX9-NEXT: v_mov_b32_e32 v0, s11470; GFX9-NEXT: v_mov_b32_e32 v1, s31471; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v11472; GFX9-NEXT: v_mov_b32_e32 v1, s01473; GFX9-NEXT: v_mov_b32_e32 v2, s21474; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v21475; GFX9-NEXT: v_readfirstlane_b32 s0, v11476; GFX9-NEXT: v_readfirstlane_b32 s1, v01477; GFX9-NEXT: ; return to shader part epilog1478;1479; GFX11-LABEL: s_copysign_v3f16:1480; GFX11: ; %bb.0:1481; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s31482; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1483; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v01484; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, s1, v11485; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1486; GFX11-NEXT: v_readfirstlane_b32 s0, v01487; GFX11-NEXT: v_readfirstlane_b32 s1, v11488; GFX11-NEXT: ; return to shader part epilog1489 %out = call <3 x half> @llvm.copysign.v3f16(<3 x half> %arg_mag, <3 x half> %arg_sign)1490 %cast = bitcast <3 x half> %out to <3 x i16>1491 ret <3 x i16> %cast1492}1493 1494define amdgpu_ps <2 x i32> @s_copysign_v4f16(<4 x half> inreg %arg_mag, <4 x half> inreg %arg_sign) {1495; SI-LABEL: s_copysign_v4f16:1496; SI: ; %bb.0:1497; SI-NEXT: v_cvt_f16_f32_e32 v2, s51498; SI-NEXT: v_cvt_f16_f32_e32 v3, s11499; SI-NEXT: v_cvt_f16_f32_e32 v4, s71500; SI-NEXT: v_cvt_f16_f32_e32 v5, s31501; SI-NEXT: v_cvt_f16_f32_e32 v0, s41502; SI-NEXT: v_cvt_f16_f32_e32 v1, s01503; SI-NEXT: v_cvt_f16_f32_e32 v6, s61504; SI-NEXT: v_cvt_f16_f32_e32 v7, s21505; SI-NEXT: v_cvt_f32_f16_e32 v2, v21506; SI-NEXT: v_cvt_f32_f16_e32 v3, v31507; SI-NEXT: v_cvt_f32_f16_e32 v4, v41508; SI-NEXT: v_cvt_f32_f16_e32 v5, v51509; SI-NEXT: v_cvt_f32_f16_e32 v0, v01510; SI-NEXT: v_cvt_f32_f16_e32 v1, v11511; SI-NEXT: v_cvt_f32_f16_e32 v6, v61512; SI-NEXT: v_cvt_f32_f16_e32 v7, v71513; SI-NEXT: s_brev_b32 s0, -21514; SI-NEXT: v_bfi_b32 v4, s0, v5, v41515; SI-NEXT: v_bfi_b32 v2, s0, v3, v21516; SI-NEXT: v_cvt_f16_f32_e32 v4, v41517; SI-NEXT: v_bfi_b32 v5, s0, v7, v61518; SI-NEXT: v_cvt_f16_f32_e32 v2, v21519; SI-NEXT: v_bfi_b32 v0, s0, v1, v01520; SI-NEXT: v_cvt_f16_f32_e32 v5, v51521; SI-NEXT: v_cvt_f16_f32_e32 v0, v01522; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v41523; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21524; SI-NEXT: v_or_b32_e32 v1, v5, v11525; SI-NEXT: v_or_b32_e32 v0, v0, v21526; SI-NEXT: v_readfirstlane_b32 s0, v01527; SI-NEXT: v_readfirstlane_b32 s1, v11528; SI-NEXT: ; return to shader part epilog1529;1530; VI-LABEL: s_copysign_v4f16:1531; VI: ; %bb.0:1532; VI-NEXT: s_mov_b32 s4, 0x7fff7fff1533; VI-NEXT: v_mov_b32_e32 v0, s11534; VI-NEXT: v_mov_b32_e32 v1, s31535; VI-NEXT: v_bfi_b32 v0, s4, v0, v11536; VI-NEXT: v_mov_b32_e32 v1, s01537; VI-NEXT: v_mov_b32_e32 v2, s21538; VI-NEXT: v_bfi_b32 v1, s4, v1, v21539; VI-NEXT: v_readfirstlane_b32 s0, v11540; VI-NEXT: v_readfirstlane_b32 s1, v01541; VI-NEXT: ; return to shader part epilog1542;1543; GFX9-LABEL: s_copysign_v4f16:1544; GFX9: ; %bb.0:1545; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff1546; GFX9-NEXT: v_mov_b32_e32 v0, s11547; GFX9-NEXT: v_mov_b32_e32 v1, s31548; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v11549; GFX9-NEXT: v_mov_b32_e32 v1, s01550; GFX9-NEXT: v_mov_b32_e32 v2, s21551; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v21552; GFX9-NEXT: v_readfirstlane_b32 s0, v11553; GFX9-NEXT: v_readfirstlane_b32 s1, v01554; GFX9-NEXT: ; return to shader part epilog1555;1556; GFX11-LABEL: s_copysign_v4f16:1557; GFX11: ; %bb.0:1558; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s31559; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1560; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v01561; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, s1, v11562; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1563; GFX11-NEXT: v_readfirstlane_b32 s0, v01564; GFX11-NEXT: v_readfirstlane_b32 s1, v11565; GFX11-NEXT: ; return to shader part epilog1566 %out = call <4 x half> @llvm.copysign.v4f16(<4 x half> %arg_mag, <4 x half> %arg_sign)1567 %cast = bitcast <4 x half> %out to <2 x i32>1568 ret <2 x i32> %cast1569}1570 1571define amdgpu_ps <4 x i32> @s_copysign_v8f16(<8 x half> inreg %arg_mag, <8 x half> inreg %arg_sign) {1572; SI-LABEL: s_copysign_v8f16:1573; SI: ; %bb.0:1574; SI-NEXT: v_cvt_f16_f32_e32 v2, s91575; SI-NEXT: v_cvt_f16_f32_e32 v3, s11576; SI-NEXT: v_cvt_f16_f32_e32 v6, s111577; SI-NEXT: v_cvt_f16_f32_e32 v7, s31578; SI-NEXT: v_cvt_f16_f32_e32 v10, s131579; SI-NEXT: v_cvt_f16_f32_e32 v11, s51580; SI-NEXT: v_cvt_f16_f32_e32 v12, s151581; SI-NEXT: v_cvt_f16_f32_e32 v13, s71582; SI-NEXT: v_cvt_f16_f32_e32 v0, s81583; SI-NEXT: v_cvt_f16_f32_e32 v1, s01584; SI-NEXT: v_cvt_f16_f32_e32 v4, s101585; SI-NEXT: v_cvt_f16_f32_e32 v5, s21586; SI-NEXT: v_cvt_f16_f32_e32 v8, s121587; SI-NEXT: v_cvt_f16_f32_e32 v9, s41588; SI-NEXT: v_cvt_f16_f32_e32 v14, s141589; SI-NEXT: v_cvt_f16_f32_e32 v15, s61590; SI-NEXT: v_cvt_f32_f16_e32 v2, v21591; SI-NEXT: v_cvt_f32_f16_e32 v3, v31592; SI-NEXT: v_cvt_f32_f16_e32 v6, v61593; SI-NEXT: v_cvt_f32_f16_e32 v7, v71594; SI-NEXT: v_cvt_f32_f16_e32 v10, v101595; SI-NEXT: v_cvt_f32_f16_e32 v11, v111596; SI-NEXT: v_cvt_f32_f16_e32 v12, v121597; SI-NEXT: v_cvt_f32_f16_e32 v13, v131598; SI-NEXT: v_cvt_f32_f16_e32 v0, v01599; SI-NEXT: v_cvt_f32_f16_e32 v1, v11600; SI-NEXT: v_cvt_f32_f16_e32 v4, v41601; SI-NEXT: v_cvt_f32_f16_e32 v5, v51602; SI-NEXT: v_cvt_f32_f16_e32 v8, v81603; SI-NEXT: v_cvt_f32_f16_e32 v9, v91604; SI-NEXT: v_cvt_f32_f16_e32 v14, v141605; SI-NEXT: v_cvt_f32_f16_e32 v15, v151606; SI-NEXT: s_brev_b32 s0, -21607; SI-NEXT: v_bfi_b32 v12, s0, v13, v121608; SI-NEXT: v_bfi_b32 v10, s0, v11, v101609; SI-NEXT: v_bfi_b32 v6, s0, v7, v61610; SI-NEXT: v_bfi_b32 v2, s0, v3, v21611; SI-NEXT: v_cvt_f16_f32_e32 v12, v121612; SI-NEXT: v_bfi_b32 v13, s0, v15, v141613; SI-NEXT: v_cvt_f16_f32_e32 v10, v101614; SI-NEXT: v_bfi_b32 v8, s0, v9, v81615; SI-NEXT: v_cvt_f16_f32_e32 v6, v61616; SI-NEXT: v_bfi_b32 v4, s0, v5, v41617; SI-NEXT: v_cvt_f16_f32_e32 v2, v21618; SI-NEXT: v_bfi_b32 v0, s0, v1, v01619; SI-NEXT: v_cvt_f16_f32_e32 v13, v131620; SI-NEXT: v_cvt_f16_f32_e32 v8, v81621; SI-NEXT: v_cvt_f16_f32_e32 v4, v41622; SI-NEXT: v_cvt_f16_f32_e32 v0, v01623; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v121624; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v101625; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61626; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21627; SI-NEXT: v_or_b32_e32 v9, v13, v91628; SI-NEXT: v_or_b32_e32 v8, v8, v101629; SI-NEXT: v_or_b32_e32 v1, v4, v11630; SI-NEXT: v_or_b32_e32 v0, v0, v21631; SI-NEXT: v_readfirstlane_b32 s0, v01632; SI-NEXT: v_readfirstlane_b32 s1, v11633; SI-NEXT: v_readfirstlane_b32 s2, v81634; SI-NEXT: v_readfirstlane_b32 s3, v91635; SI-NEXT: ; return to shader part epilog1636;1637; VI-LABEL: s_copysign_v8f16:1638; VI: ; %bb.0:1639; VI-NEXT: s_mov_b32 s8, 0x7fff7fff1640; VI-NEXT: v_mov_b32_e32 v0, s31641; VI-NEXT: v_mov_b32_e32 v1, s71642; VI-NEXT: v_bfi_b32 v0, s8, v0, v11643; VI-NEXT: v_mov_b32_e32 v1, s21644; VI-NEXT: v_mov_b32_e32 v2, s61645; VI-NEXT: v_bfi_b32 v1, s8, v1, v21646; VI-NEXT: v_mov_b32_e32 v2, s11647; VI-NEXT: v_mov_b32_e32 v3, s51648; VI-NEXT: v_bfi_b32 v2, s8, v2, v31649; VI-NEXT: v_mov_b32_e32 v3, s01650; VI-NEXT: v_mov_b32_e32 v4, s41651; VI-NEXT: v_bfi_b32 v3, s8, v3, v41652; VI-NEXT: v_readfirstlane_b32 s0, v31653; VI-NEXT: v_readfirstlane_b32 s1, v21654; VI-NEXT: v_readfirstlane_b32 s2, v11655; VI-NEXT: v_readfirstlane_b32 s3, v01656; VI-NEXT: ; return to shader part epilog1657;1658; GFX9-LABEL: s_copysign_v8f16:1659; GFX9: ; %bb.0:1660; GFX9-NEXT: s_mov_b32 s8, 0x7fff7fff1661; GFX9-NEXT: v_mov_b32_e32 v0, s31662; GFX9-NEXT: v_mov_b32_e32 v1, s71663; GFX9-NEXT: v_bfi_b32 v0, s8, v0, v11664; GFX9-NEXT: v_mov_b32_e32 v1, s21665; GFX9-NEXT: v_mov_b32_e32 v2, s61666; GFX9-NEXT: v_bfi_b32 v1, s8, v1, v21667; GFX9-NEXT: v_mov_b32_e32 v2, s11668; GFX9-NEXT: v_mov_b32_e32 v3, s51669; GFX9-NEXT: v_bfi_b32 v2, s8, v2, v31670; GFX9-NEXT: v_mov_b32_e32 v3, s01671; GFX9-NEXT: v_mov_b32_e32 v4, s41672; GFX9-NEXT: v_bfi_b32 v3, s8, v3, v41673; GFX9-NEXT: v_readfirstlane_b32 s0, v31674; GFX9-NEXT: v_readfirstlane_b32 s1, v21675; GFX9-NEXT: v_readfirstlane_b32 s2, v11676; GFX9-NEXT: v_readfirstlane_b32 s3, v01677; GFX9-NEXT: ; return to shader part epilog1678;1679; GFX11-LABEL: s_copysign_v8f16:1680; GFX11: ; %bb.0:1681; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s51682; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s71683; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)1684; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v01685; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, s1, v11686; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)1687; GFX11-NEXT: v_bfi_b32 v2, 0x7fff7fff, s2, v21688; GFX11-NEXT: v_bfi_b32 v3, 0x7fff7fff, s3, v31689; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1690; GFX11-NEXT: v_readfirstlane_b32 s0, v01691; GFX11-NEXT: v_readfirstlane_b32 s1, v11692; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1693; GFX11-NEXT: v_readfirstlane_b32 s2, v21694; GFX11-NEXT: v_readfirstlane_b32 s3, v31695; GFX11-NEXT: ; return to shader part epilog1696 %out = call <8 x half> @llvm.copysign.v8f16(<8 x half> %arg_mag, <8 x half> %arg_sign)1697 %cast = bitcast <8 x half> %out to <4 x i32>1698 ret <4 x i32> %cast1699}1700 1701define amdgpu_ps <8 x i32> @s_copysign_v16f16(<16 x half> inreg %arg_mag, <16 x half> inreg %arg_sign) {1702; SI-LABEL: s_copysign_v16f16:1703; SI: ; %bb.0:1704; SI-NEXT: v_cvt_f16_f32_e32 v16, s311705; SI-NEXT: v_cvt_f16_f32_e32 v17, s151706; SI-NEXT: v_cvt_f16_f32_e32 v18, s301707; SI-NEXT: v_cvt_f16_f32_e32 v19, s141708; SI-NEXT: v_cvt_f32_f16_e32 v16, v161709; SI-NEXT: v_cvt_f32_f16_e32 v17, v171710; SI-NEXT: v_cvt_f32_f16_e32 v18, v181711; SI-NEXT: v_cvt_f32_f16_e32 v19, v191712; SI-NEXT: v_cvt_f16_f32_e32 v1, s01713; SI-NEXT: s_brev_b32 s0, -21714; SI-NEXT: v_cvt_f16_f32_e32 v12, s281715; SI-NEXT: v_cvt_f16_f32_e32 v13, s121716; SI-NEXT: v_bfi_b32 v16, s0, v17, v161717; SI-NEXT: v_cvt_f16_f32_e32 v17, s291718; SI-NEXT: v_bfi_b32 v18, s0, v19, v181719; SI-NEXT: v_cvt_f16_f32_e32 v19, s131720; SI-NEXT: v_cvt_f32_f16_e32 v12, v121721; SI-NEXT: v_cvt_f32_f16_e32 v13, v131722; SI-NEXT: v_cvt_f32_f16_e32 v17, v171723; SI-NEXT: v_cvt_f32_f16_e32 v19, v191724; SI-NEXT: v_cvt_f16_f32_e32 v16, v161725; SI-NEXT: v_bfi_b32 v12, s0, v13, v121726; SI-NEXT: v_cvt_f16_f32_e32 v13, s111727; SI-NEXT: v_bfi_b32 v17, s0, v19, v171728; SI-NEXT: v_cvt_f16_f32_e32 v19, s271729; SI-NEXT: v_cvt_f16_f32_e32 v17, v171730; SI-NEXT: v_cvt_f16_f32_e32 v18, v181731; SI-NEXT: v_cvt_f16_f32_e32 v12, v121732; SI-NEXT: v_cvt_f32_f16_e32 v19, v191733; SI-NEXT: v_cvt_f32_f16_e32 v13, v131734; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v161735; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v171736; SI-NEXT: v_cvt_f16_f32_e32 v14, s251737; SI-NEXT: v_cvt_f16_f32_e32 v15, s261738; SI-NEXT: v_or_b32_e32 v16, v18, v161739; SI-NEXT: v_cvt_f16_f32_e32 v18, s101740; SI-NEXT: v_or_b32_e32 v12, v12, v171741; SI-NEXT: v_cvt_f16_f32_e32 v17, s91742; SI-NEXT: v_cvt_f16_f32_e32 v11, s241743; SI-NEXT: v_bfi_b32 v13, s0, v13, v191744; SI-NEXT: v_cvt_f16_f32_e32 v19, s81745; SI-NEXT: v_cvt_f32_f16_e32 v15, v151746; SI-NEXT: v_cvt_f32_f16_e32 v18, v181747; SI-NEXT: v_cvt_f32_f16_e32 v14, v141748; SI-NEXT: v_cvt_f32_f16_e32 v17, v171749; SI-NEXT: v_cvt_f32_f16_e32 v11, v111750; SI-NEXT: v_cvt_f32_f16_e32 v19, v191751; SI-NEXT: v_bfi_b32 v15, s0, v18, v151752; SI-NEXT: v_bfi_b32 v14, s0, v17, v141753; SI-NEXT: v_cvt_f16_f32_e32 v13, v131754; SI-NEXT: v_bfi_b32 v11, s0, v19, v111755; SI-NEXT: v_cvt_f16_f32_e32 v15, v151756; SI-NEXT: v_cvt_f16_f32_e32 v14, v141757; SI-NEXT: v_cvt_f16_f32_e32 v11, v111758; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v131759; SI-NEXT: v_cvt_f16_f32_e32 v2, s171760; SI-NEXT: v_cvt_f16_f32_e32 v3, s11761; SI-NEXT: v_cvt_f16_f32_e32 v6, s191762; SI-NEXT: v_cvt_f16_f32_e32 v7, s31763; SI-NEXT: v_cvt_f16_f32_e32 v10, s211764; SI-NEXT: v_cvt_f16_f32_e32 v18, s51765; SI-NEXT: v_cvt_f16_f32_e32 v19, s231766; SI-NEXT: v_or_b32_e32 v13, v15, v131767; SI-NEXT: v_cvt_f16_f32_e32 v15, s71768; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v141769; SI-NEXT: v_cvt_f16_f32_e32 v0, s161770; SI-NEXT: v_cvt_f16_f32_e32 v4, s181771; SI-NEXT: v_cvt_f16_f32_e32 v5, s21772; SI-NEXT: v_cvt_f16_f32_e32 v8, s201773; SI-NEXT: v_cvt_f16_f32_e32 v9, s41774; SI-NEXT: v_cvt_f16_f32_e32 v17, s221775; SI-NEXT: v_or_b32_e32 v11, v11, v141776; SI-NEXT: v_cvt_f16_f32_e32 v14, s61777; SI-NEXT: v_cvt_f32_f16_e32 v2, v21778; SI-NEXT: v_cvt_f32_f16_e32 v3, v31779; SI-NEXT: v_cvt_f32_f16_e32 v6, v61780; SI-NEXT: v_cvt_f32_f16_e32 v7, v71781; SI-NEXT: v_cvt_f32_f16_e32 v10, v101782; SI-NEXT: v_cvt_f32_f16_e32 v19, v191783; SI-NEXT: v_cvt_f32_f16_e32 v15, v151784; SI-NEXT: v_cvt_f32_f16_e32 v18, v181785; SI-NEXT: v_cvt_f32_f16_e32 v0, v01786; SI-NEXT: v_cvt_f32_f16_e32 v1, v11787; SI-NEXT: v_cvt_f32_f16_e32 v4, v41788; SI-NEXT: v_cvt_f32_f16_e32 v5, v51789; SI-NEXT: v_cvt_f32_f16_e32 v8, v81790; SI-NEXT: v_cvt_f32_f16_e32 v9, v91791; SI-NEXT: v_cvt_f32_f16_e32 v17, v171792; SI-NEXT: v_cvt_f32_f16_e32 v14, v141793; SI-NEXT: v_bfi_b32 v15, s0, v15, v191794; SI-NEXT: v_bfi_b32 v10, s0, v18, v101795; SI-NEXT: v_bfi_b32 v6, s0, v7, v61796; SI-NEXT: v_bfi_b32 v2, s0, v3, v21797; SI-NEXT: v_cvt_f16_f32_e32 v15, v151798; SI-NEXT: v_bfi_b32 v14, s0, v14, v171799; SI-NEXT: v_cvt_f16_f32_e32 v10, v101800; SI-NEXT: v_bfi_b32 v8, s0, v9, v81801; SI-NEXT: v_cvt_f16_f32_e32 v6, v61802; SI-NEXT: v_bfi_b32 v4, s0, v5, v41803; SI-NEXT: v_cvt_f16_f32_e32 v2, v21804; SI-NEXT: v_bfi_b32 v0, s0, v1, v01805; SI-NEXT: v_cvt_f16_f32_e32 v14, v141806; SI-NEXT: v_cvt_f16_f32_e32 v8, v81807; SI-NEXT: v_cvt_f16_f32_e32 v4, v41808; SI-NEXT: v_cvt_f16_f32_e32 v0, v01809; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v151810; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v101811; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v61812; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21813; SI-NEXT: v_or_b32_e32 v9, v14, v91814; SI-NEXT: v_or_b32_e32 v8, v8, v101815; SI-NEXT: v_or_b32_e32 v1, v4, v11816; SI-NEXT: v_or_b32_e32 v0, v0, v21817; SI-NEXT: v_readfirstlane_b32 s0, v01818; SI-NEXT: v_readfirstlane_b32 s1, v11819; SI-NEXT: v_readfirstlane_b32 s2, v81820; SI-NEXT: v_readfirstlane_b32 s3, v91821; SI-NEXT: v_readfirstlane_b32 s4, v111822; SI-NEXT: v_readfirstlane_b32 s5, v131823; SI-NEXT: v_readfirstlane_b32 s6, v121824; SI-NEXT: v_readfirstlane_b32 s7, v161825; SI-NEXT: ; return to shader part epilog1826;1827; VI-LABEL: s_copysign_v16f16:1828; VI: ; %bb.0:1829; VI-NEXT: s_mov_b32 s16, 0x7fff7fff1830; VI-NEXT: v_mov_b32_e32 v0, s71831; VI-NEXT: v_mov_b32_e32 v1, s151832; VI-NEXT: v_bfi_b32 v0, s16, v0, v11833; VI-NEXT: v_mov_b32_e32 v1, s61834; VI-NEXT: v_mov_b32_e32 v2, s141835; VI-NEXT: v_bfi_b32 v1, s16, v1, v21836; VI-NEXT: v_mov_b32_e32 v2, s51837; VI-NEXT: v_mov_b32_e32 v3, s131838; VI-NEXT: v_bfi_b32 v2, s16, v2, v31839; VI-NEXT: v_mov_b32_e32 v3, s41840; VI-NEXT: v_mov_b32_e32 v4, s121841; VI-NEXT: v_bfi_b32 v3, s16, v3, v41842; VI-NEXT: v_mov_b32_e32 v4, s31843; VI-NEXT: v_mov_b32_e32 v5, s111844; VI-NEXT: v_bfi_b32 v4, s16, v4, v51845; VI-NEXT: v_mov_b32_e32 v5, s21846; VI-NEXT: v_mov_b32_e32 v6, s101847; VI-NEXT: v_bfi_b32 v5, s16, v5, v61848; VI-NEXT: v_mov_b32_e32 v6, s11849; VI-NEXT: v_mov_b32_e32 v7, s91850; VI-NEXT: v_bfi_b32 v6, s16, v6, v71851; VI-NEXT: v_mov_b32_e32 v7, s01852; VI-NEXT: v_mov_b32_e32 v8, s81853; VI-NEXT: v_bfi_b32 v7, s16, v7, v81854; VI-NEXT: v_readfirstlane_b32 s0, v71855; VI-NEXT: v_readfirstlane_b32 s1, v61856; VI-NEXT: v_readfirstlane_b32 s2, v51857; VI-NEXT: v_readfirstlane_b32 s3, v41858; VI-NEXT: v_readfirstlane_b32 s4, v31859; VI-NEXT: v_readfirstlane_b32 s5, v21860; VI-NEXT: v_readfirstlane_b32 s6, v11861; VI-NEXT: v_readfirstlane_b32 s7, v01862; VI-NEXT: ; return to shader part epilog1863;1864; GFX9-LABEL: s_copysign_v16f16:1865; GFX9: ; %bb.0:1866; GFX9-NEXT: s_mov_b32 s16, 0x7fff7fff1867; GFX9-NEXT: v_mov_b32_e32 v0, s71868; GFX9-NEXT: v_mov_b32_e32 v1, s151869; GFX9-NEXT: v_bfi_b32 v0, s16, v0, v11870; GFX9-NEXT: v_mov_b32_e32 v1, s61871; GFX9-NEXT: v_mov_b32_e32 v2, s141872; GFX9-NEXT: v_bfi_b32 v1, s16, v1, v21873; GFX9-NEXT: v_mov_b32_e32 v2, s51874; GFX9-NEXT: v_mov_b32_e32 v3, s131875; GFX9-NEXT: v_bfi_b32 v2, s16, v2, v31876; GFX9-NEXT: v_mov_b32_e32 v3, s41877; GFX9-NEXT: v_mov_b32_e32 v4, s121878; GFX9-NEXT: v_bfi_b32 v3, s16, v3, v41879; GFX9-NEXT: v_mov_b32_e32 v4, s31880; GFX9-NEXT: v_mov_b32_e32 v5, s111881; GFX9-NEXT: v_bfi_b32 v4, s16, v4, v51882; GFX9-NEXT: v_mov_b32_e32 v5, s21883; GFX9-NEXT: v_mov_b32_e32 v6, s101884; GFX9-NEXT: v_bfi_b32 v5, s16, v5, v61885; GFX9-NEXT: v_mov_b32_e32 v6, s11886; GFX9-NEXT: v_mov_b32_e32 v7, s91887; GFX9-NEXT: v_bfi_b32 v6, s16, v6, v71888; GFX9-NEXT: v_mov_b32_e32 v7, s01889; GFX9-NEXT: v_mov_b32_e32 v8, s81890; GFX9-NEXT: v_bfi_b32 v7, s16, v7, v81891; GFX9-NEXT: v_readfirstlane_b32 s0, v71892; GFX9-NEXT: v_readfirstlane_b32 s1, v61893; GFX9-NEXT: v_readfirstlane_b32 s2, v51894; GFX9-NEXT: v_readfirstlane_b32 s3, v41895; GFX9-NEXT: v_readfirstlane_b32 s4, v31896; GFX9-NEXT: v_readfirstlane_b32 s5, v21897; GFX9-NEXT: v_readfirstlane_b32 s6, v11898; GFX9-NEXT: v_readfirstlane_b32 s7, v01899; GFX9-NEXT: ; return to shader part epilog1900;1901; GFX11-LABEL: s_copysign_v16f16:1902; GFX11: ; %bb.0:1903; GFX11-NEXT: v_dual_mov_b32 v0, s15 :: v_dual_mov_b32 v1, s141904; GFX11-NEXT: v_dual_mov_b32 v2, s13 :: v_dual_mov_b32 v3, s81905; GFX11-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s101906; GFX11-NEXT: v_dual_mov_b32 v6, s11 :: v_dual_mov_b32 v7, s121907; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)1908; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, s7, v01909; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, s6, v11910; GFX11-NEXT: v_bfi_b32 v2, 0x7fff7fff, s5, v21911; GFX11-NEXT: v_bfi_b32 v3, 0x7fff7fff, s0, v31912; GFX11-NEXT: v_bfi_b32 v4, 0x7fff7fff, s1, v41913; GFX11-NEXT: v_bfi_b32 v5, 0x7fff7fff, s2, v51914; GFX11-NEXT: v_bfi_b32 v6, 0x7fff7fff, s3, v61915; GFX11-NEXT: v_bfi_b32 v7, 0x7fff7fff, s4, v71916; GFX11-NEXT: v_readfirstlane_b32 s0, v31917; GFX11-NEXT: v_readfirstlane_b32 s1, v41918; GFX11-NEXT: v_readfirstlane_b32 s2, v51919; GFX11-NEXT: v_readfirstlane_b32 s3, v61920; GFX11-NEXT: v_readfirstlane_b32 s4, v71921; GFX11-NEXT: v_readfirstlane_b32 s5, v21922; GFX11-NEXT: v_readfirstlane_b32 s6, v11923; GFX11-NEXT: v_readfirstlane_b32 s7, v01924; GFX11-NEXT: ; return to shader part epilog1925 %out = call <16 x half> @llvm.copysign.v16f16(<16 x half> %arg_mag, <16 x half> %arg_sign)1926 %cast = bitcast <16 x half> %out to <8 x i32>1927 ret <8 x i32> %cast1928}1929 1930define <2 x half> @v_copysign_v2f16(<2 x half> %mag, <2 x half> %sign) {1931; SI-LABEL: v_copysign_v2f16:1932; SI: ; %bb.0:1933; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1934; SI-NEXT: v_cvt_f16_f32_e32 v3, v31935; SI-NEXT: v_cvt_f16_f32_e32 v2, v21936; SI-NEXT: v_cvt_f16_f32_e32 v0, v01937; SI-NEXT: v_cvt_f16_f32_e32 v1, v11938; SI-NEXT: v_cvt_f32_f16_e32 v3, v31939; SI-NEXT: v_cvt_f32_f16_e32 v2, v21940; SI-NEXT: v_cvt_f32_f16_e32 v0, v01941; SI-NEXT: v_cvt_f32_f16_e32 v1, v11942; SI-NEXT: s_brev_b32 s4, -21943; SI-NEXT: v_bfi_b32 v0, s4, v0, v21944; SI-NEXT: v_bfi_b32 v1, s4, v1, v31945; SI-NEXT: s_setpc_b64 s[30:31]1946;1947; VI-LABEL: v_copysign_v2f16:1948; VI: ; %bb.0:1949; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1950; VI-NEXT: s_mov_b32 s4, 0x7fff7fff1951; VI-NEXT: v_bfi_b32 v0, s4, v0, v11952; VI-NEXT: s_setpc_b64 s[30:31]1953;1954; GFX9-LABEL: v_copysign_v2f16:1955; GFX9: ; %bb.0:1956; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1957; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff1958; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v11959; GFX9-NEXT: s_setpc_b64 s[30:31]1960;1961; GFX11-LABEL: v_copysign_v2f16:1962; GFX11: ; %bb.0:1963; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1964; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v11965; GFX11-NEXT: s_setpc_b64 s[30:31]1966 %result = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag, <2 x half> %sign)1967 ret <2 x half> %result1968}1969 1970define <3 x half> @v_copysign_v3f16(<3 x half> %mag, <3 x half> %sign) {1971; SI-LABEL: v_copysign_v3f16:1972; SI: ; %bb.0:1973; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1974; SI-NEXT: v_cvt_f16_f32_e32 v5, v51975; SI-NEXT: v_cvt_f16_f32_e32 v2, v21976; SI-NEXT: v_cvt_f16_f32_e32 v4, v41977; SI-NEXT: v_cvt_f16_f32_e32 v3, v31978; SI-NEXT: v_cvt_f16_f32_e32 v0, v01979; SI-NEXT: v_cvt_f16_f32_e32 v1, v11980; SI-NEXT: v_cvt_f32_f16_e32 v5, v51981; SI-NEXT: v_cvt_f32_f16_e32 v4, v41982; SI-NEXT: v_cvt_f32_f16_e32 v3, v31983; SI-NEXT: v_cvt_f32_f16_e32 v0, v01984; SI-NEXT: v_cvt_f32_f16_e32 v1, v11985; SI-NEXT: v_cvt_f32_f16_e32 v2, v21986; SI-NEXT: s_brev_b32 s4, -21987; SI-NEXT: v_bfi_b32 v0, s4, v0, v31988; SI-NEXT: v_bfi_b32 v1, s4, v1, v41989; SI-NEXT: v_bfi_b32 v2, s4, v2, v51990; SI-NEXT: s_setpc_b64 s[30:31]1991;1992; VI-LABEL: v_copysign_v3f16:1993; VI: ; %bb.0:1994; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1995; VI-NEXT: s_mov_b32 s4, 0x7fff7fff1996; VI-NEXT: v_bfi_b32 v0, s4, v0, v21997; VI-NEXT: v_bfi_b32 v1, s4, v1, v31998; VI-NEXT: s_setpc_b64 s[30:31]1999;2000; GFX9-LABEL: v_copysign_v3f16:2001; GFX9: ; %bb.0:2002; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2003; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff2004; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v22005; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v32006; GFX9-NEXT: s_setpc_b64 s[30:31]2007;2008; GFX11-LABEL: v_copysign_v3f16:2009; GFX11: ; %bb.0:2010; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2011; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v22012; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v32013; GFX11-NEXT: s_setpc_b64 s[30:31]2014 %result = call <3 x half> @llvm.copysign.v3f16(<3 x half> %mag, <3 x half> %sign)2015 ret <3 x half> %result2016}2017 2018define <4 x half> @v_copysign_v4f16(<4 x half> %mag, <4 x half> %sign) {2019; SI-LABEL: v_copysign_v4f16:2020; SI: ; %bb.0:2021; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2022; SI-NEXT: v_cvt_f16_f32_e32 v7, v72023; SI-NEXT: v_cvt_f16_f32_e32 v3, v32024; SI-NEXT: v_cvt_f16_f32_e32 v6, v62025; SI-NEXT: v_cvt_f16_f32_e32 v2, v22026; SI-NEXT: v_cvt_f16_f32_e32 v5, v52027; SI-NEXT: v_cvt_f16_f32_e32 v4, v42028; SI-NEXT: v_cvt_f16_f32_e32 v0, v02029; SI-NEXT: v_cvt_f16_f32_e32 v1, v12030; SI-NEXT: v_cvt_f32_f16_e32 v7, v72031; SI-NEXT: v_cvt_f32_f16_e32 v3, v32032; SI-NEXT: v_cvt_f32_f16_e32 v6, v62033; SI-NEXT: v_cvt_f32_f16_e32 v5, v52034; SI-NEXT: v_cvt_f32_f16_e32 v4, v42035; SI-NEXT: v_cvt_f32_f16_e32 v0, v02036; SI-NEXT: v_cvt_f32_f16_e32 v1, v12037; SI-NEXT: v_cvt_f32_f16_e32 v2, v22038; SI-NEXT: s_brev_b32 s4, -22039; SI-NEXT: v_bfi_b32 v0, s4, v0, v42040; SI-NEXT: v_bfi_b32 v1, s4, v1, v52041; SI-NEXT: v_bfi_b32 v2, s4, v2, v62042; SI-NEXT: v_bfi_b32 v3, s4, v3, v72043; SI-NEXT: s_setpc_b64 s[30:31]2044;2045; VI-LABEL: v_copysign_v4f16:2046; VI: ; %bb.0:2047; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2048; VI-NEXT: s_mov_b32 s4, 0x7fff7fff2049; VI-NEXT: v_bfi_b32 v0, s4, v0, v22050; VI-NEXT: v_bfi_b32 v1, s4, v1, v32051; VI-NEXT: s_setpc_b64 s[30:31]2052;2053; GFX9-LABEL: v_copysign_v4f16:2054; GFX9: ; %bb.0:2055; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2056; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff2057; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v22058; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v32059; GFX9-NEXT: s_setpc_b64 s[30:31]2060;2061; GFX11-LABEL: v_copysign_v4f16:2062; GFX11: ; %bb.0:2063; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2064; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v22065; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v32066; GFX11-NEXT: s_setpc_b64 s[30:31]2067 %result = call <4 x half> @llvm.copysign.v4f16(<4 x half> %mag, <4 x half> %sign)2068 ret <4 x half> %result2069}2070 2071define <8 x half> @v_copysign_v8f16(<8 x half> %mag, <8 x half> %sign) {2072; SI-LABEL: v_copysign_v8f16:2073; SI: ; %bb.0:2074; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2075; SI-NEXT: v_cvt_f16_f32_e32 v15, v152076; SI-NEXT: v_cvt_f16_f32_e32 v7, v72077; SI-NEXT: v_cvt_f16_f32_e32 v14, v142078; SI-NEXT: v_cvt_f16_f32_e32 v6, v62079; SI-NEXT: v_cvt_f16_f32_e32 v13, v132080; SI-NEXT: v_cvt_f16_f32_e32 v5, v52081; SI-NEXT: v_cvt_f16_f32_e32 v12, v122082; SI-NEXT: v_cvt_f16_f32_e32 v4, v42083; SI-NEXT: v_cvt_f16_f32_e32 v11, v112084; SI-NEXT: v_cvt_f16_f32_e32 v3, v32085; SI-NEXT: v_cvt_f16_f32_e32 v10, v102086; SI-NEXT: v_cvt_f16_f32_e32 v2, v22087; SI-NEXT: v_cvt_f16_f32_e32 v9, v92088; SI-NEXT: v_cvt_f16_f32_e32 v8, v82089; SI-NEXT: v_cvt_f16_f32_e32 v0, v02090; SI-NEXT: v_cvt_f16_f32_e32 v1, v12091; SI-NEXT: v_cvt_f32_f16_e32 v15, v152092; SI-NEXT: v_cvt_f32_f16_e32 v7, v72093; SI-NEXT: v_cvt_f32_f16_e32 v14, v142094; SI-NEXT: v_cvt_f32_f16_e32 v6, v62095; SI-NEXT: v_cvt_f32_f16_e32 v13, v132096; SI-NEXT: v_cvt_f32_f16_e32 v5, v52097; SI-NEXT: v_cvt_f32_f16_e32 v12, v122098; SI-NEXT: v_cvt_f32_f16_e32 v4, v42099; SI-NEXT: v_cvt_f32_f16_e32 v11, v112100; SI-NEXT: v_cvt_f32_f16_e32 v3, v32101; SI-NEXT: v_cvt_f32_f16_e32 v10, v102102; SI-NEXT: v_cvt_f32_f16_e32 v9, v92103; SI-NEXT: v_cvt_f32_f16_e32 v8, v82104; SI-NEXT: v_cvt_f32_f16_e32 v0, v02105; SI-NEXT: v_cvt_f32_f16_e32 v1, v12106; SI-NEXT: v_cvt_f32_f16_e32 v2, v22107; SI-NEXT: s_brev_b32 s4, -22108; SI-NEXT: v_bfi_b32 v0, s4, v0, v82109; SI-NEXT: v_bfi_b32 v1, s4, v1, v92110; SI-NEXT: v_bfi_b32 v2, s4, v2, v102111; SI-NEXT: v_bfi_b32 v3, s4, v3, v112112; SI-NEXT: v_bfi_b32 v4, s4, v4, v122113; SI-NEXT: v_bfi_b32 v5, s4, v5, v132114; SI-NEXT: v_bfi_b32 v6, s4, v6, v142115; SI-NEXT: v_bfi_b32 v7, s4, v7, v152116; SI-NEXT: s_setpc_b64 s[30:31]2117;2118; VI-LABEL: v_copysign_v8f16:2119; VI: ; %bb.0:2120; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2121; VI-NEXT: s_mov_b32 s4, 0x7fff7fff2122; VI-NEXT: v_bfi_b32 v0, s4, v0, v42123; VI-NEXT: v_bfi_b32 v1, s4, v1, v52124; VI-NEXT: v_bfi_b32 v2, s4, v2, v62125; VI-NEXT: v_bfi_b32 v3, s4, v3, v72126; VI-NEXT: s_setpc_b64 s[30:31]2127;2128; GFX9-LABEL: v_copysign_v8f16:2129; GFX9: ; %bb.0:2130; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2131; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff2132; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v42133; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v52134; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v62135; GFX9-NEXT: v_bfi_b32 v3, s4, v3, v72136; GFX9-NEXT: s_setpc_b64 s[30:31]2137;2138; GFX11-LABEL: v_copysign_v8f16:2139; GFX11: ; %bb.0:2140; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2141; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v42142; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v52143; GFX11-NEXT: v_bfi_b32 v2, 0x7fff7fff, v2, v62144; GFX11-NEXT: v_bfi_b32 v3, 0x7fff7fff, v3, v72145; GFX11-NEXT: s_setpc_b64 s[30:31]2146 %result = call <8 x half> @llvm.copysign.v8f16(<8 x half> %mag, <8 x half> %sign)2147 ret <8 x half> %result2148}2149 2150define <16 x half> @v_copysign_v16f16(<16 x half> %mag, <16 x half> %sign) {2151; SI-LABEL: v_copysign_v16f16:2152; SI: ; %bb.0:2153; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2154; SI-NEXT: v_cvt_f16_f32_e32 v16, v162155; SI-NEXT: v_cvt_f16_f32_e32 v0, v02156; SI-NEXT: s_brev_b32 s4, -22157; SI-NEXT: v_cvt_f16_f32_e32 v1, v12158; SI-NEXT: v_cvt_f32_f16_e32 v16, v162159; SI-NEXT: v_cvt_f32_f16_e32 v0, v02160; SI-NEXT: v_cvt_f16_f32_e32 v2, v22161; SI-NEXT: v_cvt_f32_f16_e32 v1, v12162; SI-NEXT: v_cvt_f16_f32_e32 v3, v32163; SI-NEXT: v_bfi_b32 v0, s4, v0, v162164; SI-NEXT: v_cvt_f16_f32_e32 v16, v172165; SI-NEXT: v_cvt_f32_f16_e32 v2, v22166; SI-NEXT: v_cvt_f32_f16_e32 v3, v32167; SI-NEXT: v_cvt_f16_f32_e32 v17, v202168; SI-NEXT: v_cvt_f32_f16_e32 v16, v162169; SI-NEXT: v_cvt_f16_f32_e32 v4, v42170; SI-NEXT: v_cvt_f16_f32_e32 v5, v52171; SI-NEXT: v_cvt_f16_f32_e32 v6, v62172; SI-NEXT: v_bfi_b32 v1, s4, v1, v162173; SI-NEXT: v_cvt_f16_f32_e32 v16, v182174; SI-NEXT: v_cvt_f16_f32_e32 v18, v212175; SI-NEXT: v_cvt_f32_f16_e32 v17, v172176; SI-NEXT: v_cvt_f32_f16_e32 v4, v42177; SI-NEXT: v_cvt_f32_f16_e32 v16, v162178; SI-NEXT: v_cvt_f32_f16_e32 v18, v182179; SI-NEXT: v_cvt_f32_f16_e32 v5, v52180; SI-NEXT: v_cvt_f32_f16_e32 v6, v62181; SI-NEXT: v_bfi_b32 v2, s4, v2, v162182; SI-NEXT: v_cvt_f16_f32_e32 v16, v192183; SI-NEXT: v_cvt_f16_f32_e32 v19, v222184; SI-NEXT: v_cvt_f16_f32_e32 v20, v232185; SI-NEXT: v_cvt_f16_f32_e32 v7, v72186; SI-NEXT: v_cvt_f32_f16_e32 v16, v162187; SI-NEXT: v_cvt_f32_f16_e32 v19, v192188; SI-NEXT: v_bfi_b32 v4, s4, v4, v172189; SI-NEXT: v_bfi_b32 v5, s4, v5, v182190; SI-NEXT: v_bfi_b32 v3, s4, v3, v162191; SI-NEXT: buffer_load_dword v16, off, s[0:3], s322192; SI-NEXT: v_bfi_b32 v6, s4, v6, v192193; SI-NEXT: v_cvt_f16_f32_e32 v17, v242194; SI-NEXT: v_cvt_f16_f32_e32 v8, v82195; SI-NEXT: v_cvt_f16_f32_e32 v18, v252196; SI-NEXT: v_cvt_f16_f32_e32 v9, v92197; SI-NEXT: v_cvt_f16_f32_e32 v19, v262198; SI-NEXT: v_cvt_f16_f32_e32 v10, v102199; SI-NEXT: v_cvt_f32_f16_e32 v20, v202200; SI-NEXT: v_cvt_f32_f16_e32 v7, v72201; SI-NEXT: v_cvt_f32_f16_e32 v17, v172202; SI-NEXT: v_cvt_f32_f16_e32 v8, v82203; SI-NEXT: v_cvt_f32_f16_e32 v18, v182204; SI-NEXT: v_cvt_f32_f16_e32 v9, v92205; SI-NEXT: v_cvt_f32_f16_e32 v19, v192206; SI-NEXT: v_cvt_f32_f16_e32 v10, v102207; SI-NEXT: v_bfi_b32 v7, s4, v7, v202208; SI-NEXT: v_cvt_f16_f32_e32 v20, v272209; SI-NEXT: v_cvt_f16_f32_e32 v11, v112210; SI-NEXT: v_bfi_b32 v8, s4, v8, v172211; SI-NEXT: v_bfi_b32 v9, s4, v9, v182212; SI-NEXT: v_bfi_b32 v10, s4, v10, v192213; SI-NEXT: v_cvt_f16_f32_e32 v17, v282214; SI-NEXT: v_cvt_f16_f32_e32 v12, v122215; SI-NEXT: v_cvt_f16_f32_e32 v18, v292216; SI-NEXT: v_cvt_f16_f32_e32 v13, v132217; SI-NEXT: v_cvt_f16_f32_e32 v19, v302218; SI-NEXT: v_cvt_f16_f32_e32 v14, v142219; SI-NEXT: v_cvt_f16_f32_e32 v15, v152220; SI-NEXT: v_cvt_f32_f16_e32 v20, v202221; SI-NEXT: v_cvt_f32_f16_e32 v11, v112222; SI-NEXT: v_cvt_f32_f16_e32 v17, v172223; SI-NEXT: v_cvt_f32_f16_e32 v12, v122224; SI-NEXT: v_cvt_f32_f16_e32 v18, v182225; SI-NEXT: v_cvt_f32_f16_e32 v13, v132226; SI-NEXT: v_cvt_f32_f16_e32 v19, v192227; SI-NEXT: v_cvt_f32_f16_e32 v14, v142228; SI-NEXT: v_cvt_f32_f16_e32 v15, v152229; SI-NEXT: v_bfi_b32 v11, s4, v11, v202230; SI-NEXT: v_bfi_b32 v12, s4, v12, v172231; SI-NEXT: v_bfi_b32 v13, s4, v13, v182232; SI-NEXT: v_bfi_b32 v14, s4, v14, v192233; SI-NEXT: s_waitcnt vmcnt(0)2234; SI-NEXT: v_cvt_f16_f32_e32 v16, v162235; SI-NEXT: v_cvt_f32_f16_e32 v16, v162236; SI-NEXT: v_bfi_b32 v15, s4, v15, v162237; SI-NEXT: s_setpc_b64 s[30:31]2238;2239; VI-LABEL: v_copysign_v16f16:2240; VI: ; %bb.0:2241; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2242; VI-NEXT: s_mov_b32 s4, 0x7fff7fff2243; VI-NEXT: v_bfi_b32 v0, s4, v0, v82244; VI-NEXT: v_bfi_b32 v1, s4, v1, v92245; VI-NEXT: v_bfi_b32 v2, s4, v2, v102246; VI-NEXT: v_bfi_b32 v3, s4, v3, v112247; VI-NEXT: v_bfi_b32 v4, s4, v4, v122248; VI-NEXT: v_bfi_b32 v5, s4, v5, v132249; VI-NEXT: v_bfi_b32 v6, s4, v6, v142250; VI-NEXT: v_bfi_b32 v7, s4, v7, v152251; VI-NEXT: s_setpc_b64 s[30:31]2252;2253; GFX9-LABEL: v_copysign_v16f16:2254; GFX9: ; %bb.0:2255; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2256; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff2257; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v82258; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v92259; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v102260; GFX9-NEXT: v_bfi_b32 v3, s4, v3, v112261; GFX9-NEXT: v_bfi_b32 v4, s4, v4, v122262; GFX9-NEXT: v_bfi_b32 v5, s4, v5, v132263; GFX9-NEXT: v_bfi_b32 v6, s4, v6, v142264; GFX9-NEXT: v_bfi_b32 v7, s4, v7, v152265; GFX9-NEXT: s_setpc_b64 s[30:31]2266;2267; GFX11-LABEL: v_copysign_v16f16:2268; GFX11: ; %bb.0:2269; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2270; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v82271; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v92272; GFX11-NEXT: v_bfi_b32 v2, 0x7fff7fff, v2, v102273; GFX11-NEXT: v_bfi_b32 v3, 0x7fff7fff, v3, v112274; GFX11-NEXT: v_bfi_b32 v4, 0x7fff7fff, v4, v122275; GFX11-NEXT: v_bfi_b32 v5, 0x7fff7fff, v5, v132276; GFX11-NEXT: v_bfi_b32 v6, 0x7fff7fff, v6, v142277; GFX11-NEXT: v_bfi_b32 v7, 0x7fff7fff, v7, v152278; GFX11-NEXT: s_setpc_b64 s[30:31]2279 %result = call <16 x half> @llvm.copysign.v16f16(<16 x half> %mag, <16 x half> %sign)2280 ret <16 x half> %result2281}2282 2283define <32 x half> @v_copysign_v32f32(<32 x half> %mag, <32 x half> %sign) {2284; SI-LABEL: v_copysign_v32f32:2285; SI: ; %bb.0:2286; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2287; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:42288; SI-NEXT: buffer_load_dword v32, off, s[0:3], s322289; SI-NEXT: v_cvt_f16_f32_e32 v0, v02290; SI-NEXT: s_brev_b32 s4, -22291; SI-NEXT: v_cvt_f16_f32_e32 v1, v12292; SI-NEXT: v_cvt_f16_f32_e32 v2, v22293; SI-NEXT: v_cvt_f32_f16_e32 v0, v02294; SI-NEXT: v_cvt_f16_f32_e32 v3, v32295; SI-NEXT: v_cvt_f32_f16_e32 v1, v12296; SI-NEXT: v_cvt_f32_f16_e32 v2, v22297; SI-NEXT: v_cvt_f16_f32_e32 v4, v42298; SI-NEXT: v_cvt_f32_f16_e32 v3, v32299; SI-NEXT: v_cvt_f16_f32_e32 v5, v52300; SI-NEXT: v_cvt_f16_f32_e32 v6, v62301; SI-NEXT: v_cvt_f32_f16_e32 v4, v42302; SI-NEXT: v_cvt_f16_f32_e32 v7, v72303; SI-NEXT: v_cvt_f32_f16_e32 v5, v52304; SI-NEXT: v_cvt_f32_f16_e32 v6, v62305; SI-NEXT: v_cvt_f16_f32_e32 v8, v82306; SI-NEXT: v_cvt_f32_f16_e32 v7, v72307; SI-NEXT: v_cvt_f16_f32_e32 v9, v92308; SI-NEXT: v_cvt_f16_f32_e32 v10, v102309; SI-NEXT: v_cvt_f32_f16_e32 v8, v82310; SI-NEXT: v_cvt_f16_f32_e32 v11, v112311; SI-NEXT: v_cvt_f32_f16_e32 v9, v92312; SI-NEXT: v_cvt_f32_f16_e32 v10, v102313; SI-NEXT: v_cvt_f16_f32_e32 v12, v122314; SI-NEXT: v_cvt_f32_f16_e32 v11, v112315; SI-NEXT: v_cvt_f16_f32_e32 v13, v132316; SI-NEXT: v_cvt_f16_f32_e32 v14, v142317; SI-NEXT: v_cvt_f32_f16_e32 v12, v122318; SI-NEXT: v_cvt_f16_f32_e32 v15, v152319; SI-NEXT: v_cvt_f32_f16_e32 v13, v132320; SI-NEXT: v_cvt_f32_f16_e32 v14, v142321; SI-NEXT: v_cvt_f16_f32_e32 v16, v162322; SI-NEXT: v_cvt_f32_f16_e32 v15, v152323; SI-NEXT: v_cvt_f16_f32_e32 v17, v172324; SI-NEXT: v_cvt_f16_f32_e32 v18, v182325; SI-NEXT: v_cvt_f32_f16_e32 v16, v162326; SI-NEXT: v_cvt_f16_f32_e32 v19, v192327; SI-NEXT: v_cvt_f32_f16_e32 v17, v172328; SI-NEXT: v_cvt_f32_f16_e32 v18, v182329; SI-NEXT: v_cvt_f16_f32_e32 v20, v202330; SI-NEXT: v_cvt_f32_f16_e32 v19, v192331; SI-NEXT: v_cvt_f16_f32_e32 v21, v212332; SI-NEXT: v_cvt_f16_f32_e32 v22, v222333; SI-NEXT: v_cvt_f32_f16_e32 v20, v202334; SI-NEXT: v_cvt_f16_f32_e32 v23, v232335; SI-NEXT: v_cvt_f32_f16_e32 v21, v212336; SI-NEXT: v_cvt_f32_f16_e32 v22, v222337; SI-NEXT: v_cvt_f16_f32_e32 v24, v242338; SI-NEXT: v_cvt_f32_f16_e32 v23, v232339; SI-NEXT: v_cvt_f16_f32_e32 v25, v252340; SI-NEXT: v_cvt_f16_f32_e32 v26, v262341; SI-NEXT: v_cvt_f32_f16_e32 v24, v242342; SI-NEXT: v_cvt_f16_f32_e32 v27, v272343; SI-NEXT: v_cvt_f32_f16_e32 v25, v252344; SI-NEXT: v_cvt_f32_f16_e32 v26, v262345; SI-NEXT: v_cvt_f16_f32_e32 v28, v282346; SI-NEXT: v_cvt_f32_f16_e32 v27, v272347; SI-NEXT: v_cvt_f16_f32_e32 v29, v292348; SI-NEXT: v_cvt_f16_f32_e32 v30, v302349; SI-NEXT: v_cvt_f32_f16_e32 v28, v282350; SI-NEXT: v_cvt_f32_f16_e32 v29, v292351; SI-NEXT: v_cvt_f32_f16_e32 v30, v302352; SI-NEXT: s_waitcnt vmcnt(1)2353; SI-NEXT: v_cvt_f16_f32_e32 v31, v312354; SI-NEXT: s_waitcnt vmcnt(0)2355; SI-NEXT: v_cvt_f16_f32_e32 v32, v322356; SI-NEXT: v_cvt_f32_f16_e32 v31, v312357; SI-NEXT: v_cvt_f32_f16_e32 v32, v322358; SI-NEXT: v_bfi_b32 v0, s4, v0, v312359; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:82360; SI-NEXT: s_waitcnt vmcnt(0)2361; SI-NEXT: v_cvt_f16_f32_e32 v31, v312362; SI-NEXT: v_cvt_f32_f16_e32 v31, v312363; SI-NEXT: v_bfi_b32 v1, s4, v1, v312364; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:122365; SI-NEXT: s_waitcnt vmcnt(0)2366; SI-NEXT: v_cvt_f16_f32_e32 v31, v312367; SI-NEXT: v_cvt_f32_f16_e32 v31, v312368; SI-NEXT: v_bfi_b32 v2, s4, v2, v312369; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:162370; SI-NEXT: s_waitcnt vmcnt(0)2371; SI-NEXT: v_cvt_f16_f32_e32 v31, v312372; SI-NEXT: v_cvt_f32_f16_e32 v31, v312373; SI-NEXT: v_bfi_b32 v3, s4, v3, v312374; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:202375; SI-NEXT: s_waitcnt vmcnt(0)2376; SI-NEXT: v_cvt_f16_f32_e32 v31, v312377; SI-NEXT: v_cvt_f32_f16_e32 v31, v312378; SI-NEXT: v_bfi_b32 v4, s4, v4, v312379; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:242380; SI-NEXT: s_waitcnt vmcnt(0)2381; SI-NEXT: v_cvt_f16_f32_e32 v31, v312382; SI-NEXT: v_cvt_f32_f16_e32 v31, v312383; SI-NEXT: v_bfi_b32 v5, s4, v5, v312384; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:282385; SI-NEXT: s_waitcnt vmcnt(0)2386; SI-NEXT: v_cvt_f16_f32_e32 v31, v312387; SI-NEXT: v_cvt_f32_f16_e32 v31, v312388; SI-NEXT: v_bfi_b32 v6, s4, v6, v312389; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:322390; SI-NEXT: s_waitcnt vmcnt(0)2391; SI-NEXT: v_cvt_f16_f32_e32 v31, v312392; SI-NEXT: v_cvt_f32_f16_e32 v31, v312393; SI-NEXT: v_bfi_b32 v7, s4, v7, v312394; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:362395; SI-NEXT: s_waitcnt vmcnt(0)2396; SI-NEXT: v_cvt_f16_f32_e32 v31, v312397; SI-NEXT: v_cvt_f32_f16_e32 v31, v312398; SI-NEXT: v_bfi_b32 v8, s4, v8, v312399; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:402400; SI-NEXT: s_waitcnt vmcnt(0)2401; SI-NEXT: v_cvt_f16_f32_e32 v31, v312402; SI-NEXT: v_cvt_f32_f16_e32 v31, v312403; SI-NEXT: v_bfi_b32 v9, s4, v9, v312404; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:442405; SI-NEXT: s_waitcnt vmcnt(0)2406; SI-NEXT: v_cvt_f16_f32_e32 v31, v312407; SI-NEXT: v_cvt_f32_f16_e32 v31, v312408; SI-NEXT: v_bfi_b32 v10, s4, v10, v312409; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:482410; SI-NEXT: s_waitcnt vmcnt(0)2411; SI-NEXT: v_cvt_f16_f32_e32 v31, v312412; SI-NEXT: v_cvt_f32_f16_e32 v31, v312413; SI-NEXT: v_bfi_b32 v11, s4, v11, v312414; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:522415; SI-NEXT: s_waitcnt vmcnt(0)2416; SI-NEXT: v_cvt_f16_f32_e32 v31, v312417; SI-NEXT: v_cvt_f32_f16_e32 v31, v312418; SI-NEXT: v_bfi_b32 v12, s4, v12, v312419; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:562420; SI-NEXT: s_waitcnt vmcnt(0)2421; SI-NEXT: v_cvt_f16_f32_e32 v31, v312422; SI-NEXT: v_cvt_f32_f16_e32 v31, v312423; SI-NEXT: v_bfi_b32 v13, s4, v13, v312424; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:602425; SI-NEXT: s_waitcnt vmcnt(0)2426; SI-NEXT: v_cvt_f16_f32_e32 v31, v312427; SI-NEXT: v_cvt_f32_f16_e32 v31, v312428; SI-NEXT: v_bfi_b32 v14, s4, v14, v312429; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:642430; SI-NEXT: s_waitcnt vmcnt(0)2431; SI-NEXT: v_cvt_f16_f32_e32 v31, v312432; SI-NEXT: v_cvt_f32_f16_e32 v31, v312433; SI-NEXT: v_bfi_b32 v15, s4, v15, v312434; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:682435; SI-NEXT: s_waitcnt vmcnt(0)2436; SI-NEXT: v_cvt_f16_f32_e32 v31, v312437; SI-NEXT: v_cvt_f32_f16_e32 v31, v312438; SI-NEXT: v_bfi_b32 v16, s4, v16, v312439; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:722440; SI-NEXT: s_waitcnt vmcnt(0)2441; SI-NEXT: v_cvt_f16_f32_e32 v31, v312442; SI-NEXT: v_cvt_f32_f16_e32 v31, v312443; SI-NEXT: v_bfi_b32 v17, s4, v17, v312444; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:762445; SI-NEXT: s_waitcnt vmcnt(0)2446; SI-NEXT: v_cvt_f16_f32_e32 v31, v312447; SI-NEXT: v_cvt_f32_f16_e32 v31, v312448; SI-NEXT: v_bfi_b32 v18, s4, v18, v312449; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:802450; SI-NEXT: s_waitcnt vmcnt(0)2451; SI-NEXT: v_cvt_f16_f32_e32 v31, v312452; SI-NEXT: v_cvt_f32_f16_e32 v31, v312453; SI-NEXT: v_bfi_b32 v19, s4, v19, v312454; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:842455; SI-NEXT: s_waitcnt vmcnt(0)2456; SI-NEXT: v_cvt_f16_f32_e32 v31, v312457; SI-NEXT: v_cvt_f32_f16_e32 v31, v312458; SI-NEXT: v_bfi_b32 v20, s4, v20, v312459; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:882460; SI-NEXT: s_waitcnt vmcnt(0)2461; SI-NEXT: v_cvt_f16_f32_e32 v31, v312462; SI-NEXT: v_cvt_f32_f16_e32 v31, v312463; SI-NEXT: v_bfi_b32 v21, s4, v21, v312464; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:922465; SI-NEXT: s_waitcnt vmcnt(0)2466; SI-NEXT: v_cvt_f16_f32_e32 v31, v312467; SI-NEXT: v_cvt_f32_f16_e32 v31, v312468; SI-NEXT: v_bfi_b32 v22, s4, v22, v312469; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:962470; SI-NEXT: s_waitcnt vmcnt(0)2471; SI-NEXT: v_cvt_f16_f32_e32 v31, v312472; SI-NEXT: v_cvt_f32_f16_e32 v31, v312473; SI-NEXT: v_bfi_b32 v23, s4, v23, v312474; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1002475; SI-NEXT: s_waitcnt vmcnt(0)2476; SI-NEXT: v_cvt_f16_f32_e32 v31, v312477; SI-NEXT: v_cvt_f32_f16_e32 v31, v312478; SI-NEXT: v_bfi_b32 v24, s4, v24, v312479; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1042480; SI-NEXT: s_waitcnt vmcnt(0)2481; SI-NEXT: v_cvt_f16_f32_e32 v31, v312482; SI-NEXT: v_cvt_f32_f16_e32 v31, v312483; SI-NEXT: v_bfi_b32 v25, s4, v25, v312484; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1082485; SI-NEXT: s_waitcnt vmcnt(0)2486; SI-NEXT: v_cvt_f16_f32_e32 v31, v312487; SI-NEXT: v_cvt_f32_f16_e32 v31, v312488; SI-NEXT: v_bfi_b32 v26, s4, v26, v312489; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1122490; SI-NEXT: s_waitcnt vmcnt(0)2491; SI-NEXT: v_cvt_f16_f32_e32 v31, v312492; SI-NEXT: v_cvt_f32_f16_e32 v31, v312493; SI-NEXT: v_bfi_b32 v27, s4, v27, v312494; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1162495; SI-NEXT: s_waitcnt vmcnt(0)2496; SI-NEXT: v_cvt_f16_f32_e32 v31, v312497; SI-NEXT: v_cvt_f32_f16_e32 v31, v312498; SI-NEXT: v_bfi_b32 v28, s4, v28, v312499; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1202500; SI-NEXT: s_waitcnt vmcnt(0)2501; SI-NEXT: v_cvt_f16_f32_e32 v31, v312502; SI-NEXT: v_cvt_f32_f16_e32 v31, v312503; SI-NEXT: v_bfi_b32 v29, s4, v29, v312504; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1242505; SI-NEXT: s_waitcnt vmcnt(0)2506; SI-NEXT: v_cvt_f16_f32_e32 v31, v312507; SI-NEXT: v_cvt_f32_f16_e32 v31, v312508; SI-NEXT: v_bfi_b32 v30, s4, v30, v312509; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1282510; SI-NEXT: s_waitcnt vmcnt(0)2511; SI-NEXT: v_cvt_f16_f32_e32 v31, v312512; SI-NEXT: v_cvt_f32_f16_e32 v31, v312513; SI-NEXT: v_bfi_b32 v31, s4, v32, v312514; SI-NEXT: s_setpc_b64 s[30:31]2515;2516; VI-LABEL: v_copysign_v32f32:2517; VI: ; %bb.0:2518; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2519; VI-NEXT: s_mov_b32 s4, 0x7fff7fff2520; VI-NEXT: v_bfi_b32 v0, s4, v0, v162521; VI-NEXT: buffer_load_dword v16, off, s[0:3], s322522; VI-NEXT: v_bfi_b32 v1, s4, v1, v172523; VI-NEXT: v_bfi_b32 v2, s4, v2, v182524; VI-NEXT: v_bfi_b32 v3, s4, v3, v192525; VI-NEXT: v_bfi_b32 v4, s4, v4, v202526; VI-NEXT: v_bfi_b32 v5, s4, v5, v212527; VI-NEXT: v_bfi_b32 v6, s4, v6, v222528; VI-NEXT: v_bfi_b32 v7, s4, v7, v232529; VI-NEXT: v_bfi_b32 v8, s4, v8, v242530; VI-NEXT: v_bfi_b32 v9, s4, v9, v252531; VI-NEXT: v_bfi_b32 v10, s4, v10, v262532; VI-NEXT: v_bfi_b32 v11, s4, v11, v272533; VI-NEXT: v_bfi_b32 v12, s4, v12, v282534; VI-NEXT: v_bfi_b32 v13, s4, v13, v292535; VI-NEXT: v_bfi_b32 v14, s4, v14, v302536; VI-NEXT: s_waitcnt vmcnt(0)2537; VI-NEXT: v_bfi_b32 v15, s4, v15, v162538; VI-NEXT: s_setpc_b64 s[30:31]2539;2540; GFX9-LABEL: v_copysign_v32f32:2541; GFX9: ; %bb.0:2542; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2543; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff2544; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v162545; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s322546; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v172547; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v182548; GFX9-NEXT: v_bfi_b32 v3, s4, v3, v192549; GFX9-NEXT: v_bfi_b32 v4, s4, v4, v202550; GFX9-NEXT: v_bfi_b32 v5, s4, v5, v212551; GFX9-NEXT: v_bfi_b32 v6, s4, v6, v222552; GFX9-NEXT: v_bfi_b32 v7, s4, v7, v232553; GFX9-NEXT: v_bfi_b32 v8, s4, v8, v242554; GFX9-NEXT: v_bfi_b32 v9, s4, v9, v252555; GFX9-NEXT: v_bfi_b32 v10, s4, v10, v262556; GFX9-NEXT: v_bfi_b32 v11, s4, v11, v272557; GFX9-NEXT: v_bfi_b32 v12, s4, v12, v282558; GFX9-NEXT: v_bfi_b32 v13, s4, v13, v292559; GFX9-NEXT: v_bfi_b32 v14, s4, v14, v302560; GFX9-NEXT: s_waitcnt vmcnt(0)2561; GFX9-NEXT: v_bfi_b32 v15, s4, v15, v162562; GFX9-NEXT: s_setpc_b64 s[30:31]2563;2564; GFX11-LABEL: v_copysign_v32f32:2565; GFX11: ; %bb.0:2566; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2567; GFX11-NEXT: scratch_load_b32 v31, off, s322568; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v162569; GFX11-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v172570; GFX11-NEXT: v_bfi_b32 v2, 0x7fff7fff, v2, v182571; GFX11-NEXT: v_bfi_b32 v3, 0x7fff7fff, v3, v192572; GFX11-NEXT: v_bfi_b32 v4, 0x7fff7fff, v4, v202573; GFX11-NEXT: v_bfi_b32 v5, 0x7fff7fff, v5, v212574; GFX11-NEXT: v_bfi_b32 v6, 0x7fff7fff, v6, v222575; GFX11-NEXT: v_bfi_b32 v7, 0x7fff7fff, v7, v232576; GFX11-NEXT: v_bfi_b32 v8, 0x7fff7fff, v8, v242577; GFX11-NEXT: v_bfi_b32 v9, 0x7fff7fff, v9, v252578; GFX11-NEXT: v_bfi_b32 v10, 0x7fff7fff, v10, v262579; GFX11-NEXT: v_bfi_b32 v11, 0x7fff7fff, v11, v272580; GFX11-NEXT: v_bfi_b32 v12, 0x7fff7fff, v12, v282581; GFX11-NEXT: v_bfi_b32 v13, 0x7fff7fff, v13, v292582; GFX11-NEXT: v_bfi_b32 v14, 0x7fff7fff, v14, v302583; GFX11-NEXT: s_waitcnt vmcnt(0)2584; GFX11-NEXT: v_bfi_b32 v15, 0x7fff7fff, v15, v312585; GFX11-NEXT: s_setpc_b64 s[30:31]2586 %result = call <32 x half> @llvm.copysign.v32f16(<32 x half> %mag, <32 x half> %sign)2587 ret <32 x half> %result2588}2589 2590define amdgpu_ps i32 @s_copysign_out_f32_mag_f16_sign_f32(half inreg %mag, float inreg %sign) {2591; SI-LABEL: s_copysign_out_f32_mag_f16_sign_f32:2592; SI: ; %bb.0:2593; SI-NEXT: s_brev_b32 s2, -22594; SI-NEXT: v_mov_b32_e32 v0, s02595; SI-NEXT: v_mov_b32_e32 v1, s12596; SI-NEXT: v_bfi_b32 v0, s2, v0, v12597; SI-NEXT: v_readfirstlane_b32 s0, v02598; SI-NEXT: ; return to shader part epilog2599;2600; VI-LABEL: s_copysign_out_f32_mag_f16_sign_f32:2601; VI: ; %bb.0:2602; VI-NEXT: v_cvt_f32_f16_e32 v0, s02603; VI-NEXT: s_brev_b32 s0, -22604; VI-NEXT: v_mov_b32_e32 v1, s12605; VI-NEXT: v_bfi_b32 v0, s0, v0, v12606; VI-NEXT: v_readfirstlane_b32 s0, v02607; VI-NEXT: ; return to shader part epilog2608;2609; GFX9-LABEL: s_copysign_out_f32_mag_f16_sign_f32:2610; GFX9: ; %bb.0:2611; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s02612; GFX9-NEXT: s_brev_b32 s0, -22613; GFX9-NEXT: v_mov_b32_e32 v1, s12614; GFX9-NEXT: v_bfi_b32 v0, s0, v0, v12615; GFX9-NEXT: v_readfirstlane_b32 s0, v02616; GFX9-NEXT: ; return to shader part epilog2617;2618; GFX11-LABEL: s_copysign_out_f32_mag_f16_sign_f32:2619; GFX11: ; %bb.0:2620; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s02621; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2622; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s12623; GFX11-NEXT: v_readfirstlane_b32 s0, v02624; GFX11-NEXT: ; return to shader part epilog2625 %mag.ext = fpext half %mag to float2626 %out = call float @llvm.copysign.f32(float %mag.ext, float %sign)2627 %cast = bitcast float %out to i322628 ret i32 %cast2629}2630 2631define amdgpu_ps <2 x i32> @s_copysign_out_f64_mag_f16_sign_f64(half inreg %mag, double inreg %sign) {2632; SI-LABEL: s_copysign_out_f64_mag_f16_sign_f64:2633; SI: ; %bb.0:2634; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], s02635; SI-NEXT: s_brev_b32 s0, -22636; SI-NEXT: v_mov_b32_e32 v2, s22637; SI-NEXT: v_bfi_b32 v1, s0, v1, v22638; SI-NEXT: v_readfirstlane_b32 s1, v12639; SI-NEXT: v_readfirstlane_b32 s0, v02640; SI-NEXT: ; return to shader part epilog2641;2642; VI-LABEL: s_copysign_out_f64_mag_f16_sign_f64:2643; VI: ; %bb.0:2644; VI-NEXT: v_cvt_f32_f16_e32 v0, s02645; VI-NEXT: s_brev_b32 s0, -22646; VI-NEXT: v_mov_b32_e32 v2, s22647; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v02648; VI-NEXT: v_bfi_b32 v1, s0, v1, v22649; VI-NEXT: v_readfirstlane_b32 s0, v02650; VI-NEXT: v_readfirstlane_b32 s1, v12651; VI-NEXT: ; return to shader part epilog2652;2653; GFX9-LABEL: s_copysign_out_f64_mag_f16_sign_f64:2654; GFX9: ; %bb.0:2655; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s02656; GFX9-NEXT: s_brev_b32 s0, -22657; GFX9-NEXT: v_mov_b32_e32 v2, s22658; GFX9-NEXT: v_cvt_f64_f32_e32 v[0:1], v02659; GFX9-NEXT: v_bfi_b32 v1, s0, v1, v22660; GFX9-NEXT: v_readfirstlane_b32 s0, v02661; GFX9-NEXT: v_readfirstlane_b32 s1, v12662; GFX9-NEXT: ; return to shader part epilog2663;2664; GFX11-LABEL: s_copysign_out_f64_mag_f16_sign_f64:2665; GFX11: ; %bb.0:2666; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s02667; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2668; GFX11-NEXT: v_cvt_f64_f32_e32 v[0:1], v02669; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s22670; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2671; GFX11-NEXT: v_readfirstlane_b32 s0, v02672; GFX11-NEXT: v_readfirstlane_b32 s1, v12673; GFX11-NEXT: ; return to shader part epilog2674 %mag.ext = fpext half %mag to double2675 %out = call double @llvm.copysign.f64(double %mag.ext, double %sign)2676 %cast = bitcast double %out to <2 x i32>2677 ret <2 x i32> %cast2678}2679 2680define amdgpu_ps i32 @s_copysign_out_f32_mag_f32_sign_f16(float inreg %mag, half inreg %sign) {2681; SI-LABEL: s_copysign_out_f32_mag_f32_sign_f16:2682; SI: ; %bb.0:2683; SI-NEXT: s_brev_b32 s2, -22684; SI-NEXT: v_mov_b32_e32 v0, s02685; SI-NEXT: v_mov_b32_e32 v1, s12686; SI-NEXT: v_bfi_b32 v0, s2, v0, v12687; SI-NEXT: v_readfirstlane_b32 s0, v02688; SI-NEXT: ; return to shader part epilog2689;2690; VI-LABEL: s_copysign_out_f32_mag_f32_sign_f16:2691; VI: ; %bb.0:2692; VI-NEXT: v_lshlrev_b32_e64 v0, 16, s12693; VI-NEXT: s_brev_b32 s1, -22694; VI-NEXT: v_mov_b32_e32 v1, s02695; VI-NEXT: v_bfi_b32 v0, s1, v1, v02696; VI-NEXT: v_readfirstlane_b32 s0, v02697; VI-NEXT: ; return to shader part epilog2698;2699; GFX9-LABEL: s_copysign_out_f32_mag_f32_sign_f16:2700; GFX9: ; %bb.0:2701; GFX9-NEXT: v_lshlrev_b32_e64 v0, 16, s12702; GFX9-NEXT: s_brev_b32 s1, -22703; GFX9-NEXT: v_mov_b32_e32 v1, s02704; GFX9-NEXT: v_bfi_b32 v0, s1, v1, v02705; GFX9-NEXT: v_readfirstlane_b32 s0, v02706; GFX9-NEXT: ; return to shader part epilog2707;2708; GFX11-TRUE16-LABEL: s_copysign_out_f32_mag_f32_sign_f16:2709; GFX11-TRUE16: ; %bb.0:2710; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s12711; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2712; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v02713; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v02714; GFX11-TRUE16-NEXT: ; return to shader part epilog2715;2716; GFX11-FAKE16-LABEL: s_copysign_out_f32_mag_f32_sign_f16:2717; GFX11-FAKE16: ; %bb.0:2718; GFX11-FAKE16-NEXT: v_lshlrev_b32_e64 v0, 16, s12719; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2720; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v02721; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v02722; GFX11-FAKE16-NEXT: ; return to shader part epilog2723 %sign.ext = fpext half %sign to float2724 %out = call float @llvm.copysign.f32(float %mag, float %sign.ext)2725 %cast = bitcast float %out to i322726 ret i32 %cast2727}2728 2729define amdgpu_ps <2 x i32> @s_copysign_out_f64_mag_f64_sign_f16(double inreg %mag, half inreg %sign) {2730; SI-LABEL: s_copysign_out_f64_mag_f64_sign_f16:2731; SI: ; %bb.0:2732; SI-NEXT: s_brev_b32 s3, -22733; SI-NEXT: v_mov_b32_e32 v0, s12734; SI-NEXT: v_mov_b32_e32 v1, s22735; SI-NEXT: v_bfi_b32 v0, s3, v0, v12736; SI-NEXT: v_readfirstlane_b32 s1, v02737; SI-NEXT: ; return to shader part epilog2738;2739; VI-LABEL: s_copysign_out_f64_mag_f64_sign_f16:2740; VI: ; %bb.0:2741; VI-NEXT: v_lshlrev_b32_e64 v0, 16, s22742; VI-NEXT: s_brev_b32 s2, -22743; VI-NEXT: v_mov_b32_e32 v1, s12744; VI-NEXT: v_bfi_b32 v0, s2, v1, v02745; VI-NEXT: v_readfirstlane_b32 s1, v02746; VI-NEXT: ; return to shader part epilog2747;2748; GFX9-LABEL: s_copysign_out_f64_mag_f64_sign_f16:2749; GFX9: ; %bb.0:2750; GFX9-NEXT: v_lshlrev_b32_e64 v0, 16, s22751; GFX9-NEXT: s_brev_b32 s2, -22752; GFX9-NEXT: v_mov_b32_e32 v1, s12753; GFX9-NEXT: v_bfi_b32 v0, s2, v1, v02754; GFX9-NEXT: v_readfirstlane_b32 s1, v02755; GFX9-NEXT: ; return to shader part epilog2756;2757; GFX11-TRUE16-LABEL: s_copysign_out_f64_mag_f64_sign_f16:2758; GFX11-TRUE16: ; %bb.0:2759; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s22760; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2761; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v02762; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v02763; GFX11-TRUE16-NEXT: ; return to shader part epilog2764;2765; GFX11-FAKE16-LABEL: s_copysign_out_f64_mag_f64_sign_f16:2766; GFX11-FAKE16: ; %bb.0:2767; GFX11-FAKE16-NEXT: v_lshlrev_b32_e64 v0, 16, s22768; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2769; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v02770; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s1, v02771; GFX11-FAKE16-NEXT: ; return to shader part epilog2772 %sign.ext = fpext half %sign to double2773 %out = call double @llvm.copysign.f64(double %mag, double %sign.ext)2774 %cast = bitcast double %out to <2 x i32>2775 ret <2 x i32> %cast2776}2777 2778define amdgpu_ps i16 @s_copysign_out_f16_mag_f16_sign_f32(half inreg %mag, float inreg %sign) {2779; SI-LABEL: s_copysign_out_f16_mag_f16_sign_f32:2780; SI: ; %bb.0:2781; SI-NEXT: v_cvt_f16_f32_e32 v0, s02782; SI-NEXT: s_brev_b32 s0, -22783; SI-NEXT: v_mov_b32_e32 v1, s12784; SI-NEXT: v_cvt_f32_f16_e32 v0, v02785; SI-NEXT: v_bfi_b32 v0, s0, v0, v12786; SI-NEXT: v_cvt_f16_f32_e32 v0, v02787; SI-NEXT: v_readfirstlane_b32 s0, v02788; SI-NEXT: ; return to shader part epilog2789;2790; VI-LABEL: s_copysign_out_f16_mag_f16_sign_f32:2791; VI: ; %bb.0:2792; VI-NEXT: v_lshrrev_b32_e64 v0, 16, s12793; VI-NEXT: s_movk_i32 s1, 0x7fff2794; VI-NEXT: v_mov_b32_e32 v1, s02795; VI-NEXT: v_bfi_b32 v0, s1, v1, v02796; VI-NEXT: v_readfirstlane_b32 s0, v02797; VI-NEXT: ; return to shader part epilog2798;2799; GFX9-LABEL: s_copysign_out_f16_mag_f16_sign_f32:2800; GFX9: ; %bb.0:2801; GFX9-NEXT: v_lshrrev_b32_e64 v0, 16, s12802; GFX9-NEXT: s_movk_i32 s1, 0x7fff2803; GFX9-NEXT: v_mov_b32_e32 v1, s02804; GFX9-NEXT: v_bfi_b32 v0, s1, v1, v02805; GFX9-NEXT: v_readfirstlane_b32 s0, v02806; GFX9-NEXT: ; return to shader part epilog2807;2808; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f16_sign_f32:2809; GFX11-TRUE16: ; %bb.0:2810; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s02811; GFX11-TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s12812; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2813; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v12814; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v02815; GFX11-TRUE16-NEXT: ; return to shader part epilog2816;2817; GFX11-FAKE16-LABEL: s_copysign_out_f16_mag_f16_sign_f32:2818; GFX11-FAKE16: ; %bb.0:2819; GFX11-FAKE16-NEXT: v_lshrrev_b32_e64 v0, 16, s12820; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2821; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, s0, v02822; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v02823; GFX11-FAKE16-NEXT: ; return to shader part epilog2824 %sign.trunc = fptrunc float %sign to half2825 %out = call half @llvm.copysign.f16(half %mag, half %sign.trunc)2826 %cast = bitcast half %out to i162827 ret i16 %cast2828}2829 2830define amdgpu_ps i16 @s_copysign_out_f16_mag_f16_sign_f64(half inreg %mag, double inreg %sign) {2831; SI-LABEL: s_copysign_out_f16_mag_f16_sign_f64:2832; SI: ; %bb.0:2833; SI-NEXT: v_cvt_f16_f32_e32 v0, s02834; SI-NEXT: s_brev_b32 s0, -22835; SI-NEXT: v_mov_b32_e32 v1, s22836; SI-NEXT: v_cvt_f32_f16_e32 v0, v02837; SI-NEXT: v_bfi_b32 v0, s0, v0, v12838; SI-NEXT: v_cvt_f16_f32_e32 v0, v02839; SI-NEXT: v_readfirstlane_b32 s0, v02840; SI-NEXT: ; return to shader part epilog2841;2842; VI-LABEL: s_copysign_out_f16_mag_f16_sign_f64:2843; VI: ; %bb.0:2844; VI-NEXT: v_lshrrev_b32_e64 v0, 16, s22845; VI-NEXT: s_movk_i32 s1, 0x7fff2846; VI-NEXT: v_mov_b32_e32 v1, s02847; VI-NEXT: v_bfi_b32 v0, s1, v1, v02848; VI-NEXT: v_readfirstlane_b32 s0, v02849; VI-NEXT: ; return to shader part epilog2850;2851; GFX9-LABEL: s_copysign_out_f16_mag_f16_sign_f64:2852; GFX9: ; %bb.0:2853; GFX9-NEXT: v_lshrrev_b32_e64 v0, 16, s22854; GFX9-NEXT: s_movk_i32 s1, 0x7fff2855; GFX9-NEXT: v_mov_b32_e32 v1, s02856; GFX9-NEXT: v_bfi_b32 v0, s1, v1, v02857; GFX9-NEXT: v_readfirstlane_b32 s0, v02858; GFX9-NEXT: ; return to shader part epilog2859;2860; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f16_sign_f64:2861; GFX11-TRUE16: ; %bb.0:2862; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s02863; GFX11-TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s22864; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2865; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v12866; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v02867; GFX11-TRUE16-NEXT: ; return to shader part epilog2868;2869; GFX11-FAKE16-LABEL: s_copysign_out_f16_mag_f16_sign_f64:2870; GFX11-FAKE16: ; %bb.0:2871; GFX11-FAKE16-NEXT: v_lshrrev_b32_e64 v0, 16, s22872; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2873; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, s0, v02874; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v02875; GFX11-FAKE16-NEXT: ; return to shader part epilog2876 %sign.trunc = fptrunc double %sign to half2877 %out = call half @llvm.copysign.f16(half %mag, half %sign.trunc)2878 %cast = bitcast half %out to i162879 ret i16 %cast2880}2881 2882define amdgpu_ps i16 @s_copysign_out_f16_mag_f32_sign_f16(float inreg %mag, half inreg %sign) {2883; SI-LABEL: s_copysign_out_f16_mag_f32_sign_f16:2884; SI: ; %bb.0:2885; SI-NEXT: v_cvt_f16_f32_e32 v0, s02886; SI-NEXT: s_brev_b32 s0, -22887; SI-NEXT: v_mov_b32_e32 v1, s12888; SI-NEXT: v_cvt_f32_f16_e32 v0, v02889; SI-NEXT: v_bfi_b32 v0, s0, v0, v12890; SI-NEXT: v_cvt_f16_f32_e32 v0, v02891; SI-NEXT: v_readfirstlane_b32 s0, v02892; SI-NEXT: ; return to shader part epilog2893;2894; VI-LABEL: s_copysign_out_f16_mag_f32_sign_f16:2895; VI: ; %bb.0:2896; VI-NEXT: v_cvt_f16_f32_e32 v0, s02897; VI-NEXT: s_movk_i32 s0, 0x7fff2898; VI-NEXT: v_mov_b32_e32 v1, s12899; VI-NEXT: v_bfi_b32 v0, s0, v0, v12900; VI-NEXT: v_readfirstlane_b32 s0, v02901; VI-NEXT: ; return to shader part epilog2902;2903; GFX9-LABEL: s_copysign_out_f16_mag_f32_sign_f16:2904; GFX9: ; %bb.0:2905; GFX9-NEXT: v_cvt_f16_f32_e32 v0, s02906; GFX9-NEXT: s_movk_i32 s0, 0x7fff2907; GFX9-NEXT: v_mov_b32_e32 v1, s12908; GFX9-NEXT: v_bfi_b32 v0, s0, v0, v12909; GFX9-NEXT: v_readfirstlane_b32 s0, v02910; GFX9-NEXT: ; return to shader part epilog2911;2912; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f32_sign_f16:2913; GFX11-TRUE16: ; %bb.0:2914; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s02915; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s12916; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2917; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v12918; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v02919; GFX11-TRUE16-NEXT: ; return to shader part epilog2920;2921; GFX11-FAKE16-LABEL: s_copysign_out_f16_mag_f32_sign_f16:2922; GFX11-FAKE16: ; %bb.0:2923; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s02924; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2925; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s12926; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v02927; GFX11-FAKE16-NEXT: ; return to shader part epilog2928 %mag.trunc = fptrunc float %mag to half2929 %out = call half @llvm.copysign.f16(half %mag.trunc, half %sign)2930 %cast = bitcast half %out to i162931 ret i16 %cast2932}2933 2934define <2 x float> @v_copysign_out_v2f32_mag_v2f16_sign_v2f32(<2 x half> %mag, <2 x float> %sign) {2935; SI-LABEL: v_copysign_out_v2f32_mag_v2f16_sign_v2f32:2936; SI: ; %bb.0:2937; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2938; SI-NEXT: v_cvt_f16_f32_e32 v0, v02939; SI-NEXT: v_cvt_f16_f32_e32 v1, v12940; SI-NEXT: s_brev_b32 s4, -22941; SI-NEXT: v_cvt_f32_f16_e32 v0, v02942; SI-NEXT: v_cvt_f32_f16_e32 v1, v12943; SI-NEXT: v_bfi_b32 v0, s4, v0, v22944; SI-NEXT: v_bfi_b32 v1, s4, v1, v32945; SI-NEXT: s_setpc_b64 s[30:31]2946;2947; VI-LABEL: v_copysign_out_v2f32_mag_v2f16_sign_v2f32:2948; VI: ; %bb.0:2949; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2950; VI-NEXT: v_cvt_f32_f16_e32 v3, v02951; VI-NEXT: v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12952; VI-NEXT: s_brev_b32 s4, -22953; VI-NEXT: v_bfi_b32 v0, s4, v3, v12954; VI-NEXT: v_bfi_b32 v1, s4, v4, v22955; VI-NEXT: s_setpc_b64 s[30:31]2956;2957; GFX9-LABEL: v_copysign_out_v2f32_mag_v2f16_sign_v2f32:2958; GFX9: ; %bb.0:2959; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2960; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v02961; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12962; GFX9-NEXT: s_brev_b32 s4, -22963; GFX9-NEXT: v_bfi_b32 v0, s4, v3, v12964; GFX9-NEXT: v_bfi_b32 v1, s4, v4, v22965; GFX9-NEXT: s_setpc_b64 s[30:31]2966;2967; GFX11-TRUE16-LABEL: v_copysign_out_v2f32_mag_v2f16_sign_v2f32:2968; GFX11-TRUE16: ; %bb.0:2969; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2970; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l2971; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.h2972; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2973; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v12974; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v4, v22975; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]2976;2977; GFX11-FAKE16-LABEL: v_copysign_out_v2f32_mag_v2f16_sign_v2f32:2978; GFX11-FAKE16: ; %bb.0:2979; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2980; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v02981; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v02982; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2983; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v32984; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v12985; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)2986; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v22987; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]2988 %mag.ext = fpext <2 x half> %mag to <2 x float>2989 %out = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag.ext, <2 x float> %sign)2990 ret <2 x float> %out2991}2992 2993define <2 x float> @v_copysign_out_v2f32_mag_v2f32_sign_v2f16(<2 x float> %mag, <2 x half> %sign) {2994; SI-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2f16:2995; SI: ; %bb.0:2996; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2997; SI-NEXT: v_cvt_f16_f32_e32 v2, v22998; SI-NEXT: v_cvt_f16_f32_e32 v3, v32999; SI-NEXT: s_brev_b32 s4, -23000; SI-NEXT: v_cvt_f32_f16_e32 v2, v23001; SI-NEXT: v_cvt_f32_f16_e32 v3, v33002; SI-NEXT: v_bfi_b32 v0, s4, v0, v23003; SI-NEXT: v_bfi_b32 v1, s4, v1, v33004; SI-NEXT: s_setpc_b64 s[30:31]3005;3006; VI-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2f16:3007; VI: ; %bb.0:3008; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3009; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v23010; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23011; VI-NEXT: s_brev_b32 s4, -23012; VI-NEXT: v_bfi_b32 v0, s4, v0, v23013; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v33014; VI-NEXT: v_bfi_b32 v1, s4, v1, v23015; VI-NEXT: s_setpc_b64 s[30:31]3016;3017; GFX9-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2f16:3018; GFX9: ; %bb.0:3019; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3020; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v23021; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v23022; GFX9-NEXT: s_brev_b32 s4, -23023; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v23024; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v33025; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v23026; GFX9-NEXT: s_setpc_b64 s[30:31]3027;3028; GFX11-TRUE16-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2f16:3029; GFX11-TRUE16: ; %bb.0:3030; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3031; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l3032; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v23033; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3034; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v33035; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]3036;3037; GFX11-FAKE16-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2f16:3038; GFX11-FAKE16: ; %bb.0:3039; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3040; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v23041; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v23042; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3043; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v33044; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v23045; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3046; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v33047; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]3048 %sign.ext = fpext <2 x half> %sign to <2 x float>3049 %out = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag, <2 x float> %sign.ext)3050 ret <2 x float> %out3051}3052 3053define <2 x double> @v_copysign_out_v2f64_mag_v2f64_sign_v2f16(<2 x double> %mag, <2 x half> %sign) {3054; SI-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2f16:3055; SI: ; %bb.0:3056; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3057; SI-NEXT: s_brev_b32 s4, -23058; SI-NEXT: v_bfi_b32 v1, s4, v1, v43059; SI-NEXT: v_bfi_b32 v3, s4, v3, v53060; SI-NEXT: s_setpc_b64 s[30:31]3061;3062; VI-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2f16:3063; VI: ; %bb.0:3064; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3065; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v43066; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v43067; VI-NEXT: s_brev_b32 s4, -23068; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v43069; VI-NEXT: v_bfi_b32 v1, s4, v1, v53070; VI-NEXT: v_bfi_b32 v3, s4, v3, v43071; VI-NEXT: s_setpc_b64 s[30:31]3072;3073; GFX9-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2f16:3074; GFX9: ; %bb.0:3075; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3076; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v43077; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v43078; GFX9-NEXT: s_brev_b32 s4, -23079; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v43080; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v53081; GFX9-NEXT: v_bfi_b32 v3, s4, v3, v43082; GFX9-NEXT: s_setpc_b64 s[30:31]3083;3084; GFX11-TRUE16-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2f16:3085; GFX11-TRUE16: ; %bb.0:3086; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3087; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l3088; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v43089; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3090; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v53091; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]3092;3093; GFX11-FAKE16-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2f16:3094; GFX11-FAKE16: ; %bb.0:3095; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3096; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v43097; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v43098; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3099; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v53100; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v43101; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3102; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v53103; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]3104 %sign.ext = fpext <2 x half> %sign to <2 x double>3105 %out = call <2 x double> @llvm.copysign.v2f64(<2 x double> %mag, <2 x double> %sign.ext)3106 ret <2 x double> %out3107}3108 3109define <2 x half> @v_copysign_out_v2f16_mag_v2f32_sign_v2f16(<2 x float> %mag, <2 x half> %sign) {3110; SI-LABEL: v_copysign_out_v2f16_mag_v2f32_sign_v2f16:3111; SI: ; %bb.0:3112; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3113; SI-NEXT: v_cvt_f16_f32_e32 v3, v33114; SI-NEXT: v_cvt_f16_f32_e32 v2, v23115; SI-NEXT: v_cvt_f16_f32_e32 v0, v03116; SI-NEXT: v_cvt_f16_f32_e32 v1, v13117; SI-NEXT: v_cvt_f32_f16_e32 v3, v33118; SI-NEXT: v_cvt_f32_f16_e32 v2, v23119; SI-NEXT: v_cvt_f32_f16_e32 v0, v03120; SI-NEXT: v_cvt_f32_f16_e32 v1, v13121; SI-NEXT: s_brev_b32 s4, -23122; SI-NEXT: v_bfi_b32 v0, s4, v0, v23123; SI-NEXT: v_bfi_b32 v1, s4, v1, v33124; SI-NEXT: s_setpc_b64 s[30:31]3125;3126; VI-LABEL: v_copysign_out_v2f16_mag_v2f32_sign_v2f16:3127; VI: ; %bb.0:3128; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3129; VI-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD3130; VI-NEXT: v_cvt_f16_f32_e32 v0, v03131; VI-NEXT: s_mov_b32 s4, 0x7fff7fff3132; VI-NEXT: v_or_b32_e32 v0, v0, v13133; VI-NEXT: v_bfi_b32 v0, s4, v0, v23134; VI-NEXT: s_setpc_b64 s[30:31]3135;3136; GFX9-LABEL: v_copysign_out_v2f16_mag_v2f32_sign_v2f16:3137; GFX9: ; %bb.0:3138; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3139; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v13140; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v03141; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff3142; GFX9-NEXT: v_pack_b32_f16 v0, v0, v13143; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v23144; GFX9-NEXT: s_setpc_b64 s[30:31]3145;3146; GFX11-TRUE16-LABEL: v_copysign_out_v2f16_mag_v2f32_sign_v2f16:3147; GFX11-TRUE16: ; %bb.0:3148; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3149; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v13150; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v03151; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3152; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v1.l3153; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v23154; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]3155;3156; GFX11-FAKE16-LABEL: v_copysign_out_v2f16_mag_v2f32_sign_v2f16:3157; GFX11-FAKE16: ; %bb.0:3158; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3159; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v13160; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v03161; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3162; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v13163; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v23164; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]3165 %mag.trunc = fptrunc <2 x float> %mag to <2 x half>3166 %out = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag.trunc, <2 x half> %sign)3167 ret <2 x half> %out3168}3169 3170define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag, <2 x half> %sign) {3171; SI-LABEL: v_copysign_out_v2f16_mag_v2f64_sign_v2f16:3172; SI: ; %bb.0:3173; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3174; SI-NEXT: v_and_b32_e32 v7, 0x1ff, v33175; SI-NEXT: v_or_b32_e32 v2, v7, v23176; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v33177; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23178; SI-NEXT: v_and_b32_e32 v6, 0xffe, v63179; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc3180; SI-NEXT: v_bfe_u32 v7, v3, 20, 113181; SI-NEXT: s_movk_i32 s4, 0x3f13182; SI-NEXT: v_or_b32_e32 v2, v6, v23183; SI-NEXT: v_sub_i32_e32 v8, vcc, s4, v73184; SI-NEXT: v_or_b32_e32 v6, 0x1000, v23185; SI-NEXT: v_med3_i32 v8, v8, 0, 133186; SI-NEXT: v_lshrrev_b32_e32 v9, v8, v63187; SI-NEXT: v_lshlrev_b32_e32 v8, v8, v93188; SI-NEXT: v_cmp_ne_u32_e32 vcc, v8, v63189; SI-NEXT: s_movk_i32 s5, 0xfc103190; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc3191; SI-NEXT: v_add_i32_e32 v7, vcc, s5, v73192; SI-NEXT: v_lshlrev_b32_e32 v8, 12, v73193; SI-NEXT: v_or_b32_e32 v6, v9, v63194; SI-NEXT: v_or_b32_e32 v8, v2, v83195; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v73196; SI-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3197; SI-NEXT: v_and_b32_e32 v8, 7, v63198; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v83199; SI-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc3200; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v83201; SI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc3202; SI-NEXT: v_or_b32_e32 v8, v8, v93203; SI-NEXT: v_lshrrev_b32_e32 v6, 2, v63204; SI-NEXT: v_add_i32_e32 v6, vcc, v6, v83205; SI-NEXT: v_mov_b32_e32 v8, 0x7c003206; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v73207; SI-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3208; SI-NEXT: v_mov_b32_e32 v9, 0x7e003209; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23210; SI-NEXT: s_movk_i32 s6, 0x40f3211; SI-NEXT: v_cndmask_b32_e32 v2, v8, v9, vcc3212; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v73213; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc3214; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v33215; SI-NEXT: v_and_b32_e32 v6, 0x1ff, v13216; SI-NEXT: v_and_b32_e32 v3, 0x8000, v33217; SI-NEXT: v_or_b32_e32 v0, v6, v03218; SI-NEXT: v_or_b32_e32 v2, v3, v23219; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v13220; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03221; SI-NEXT: v_and_b32_e32 v3, 0xffe, v33222; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc3223; SI-NEXT: v_bfe_u32 v6, v1, 20, 113224; SI-NEXT: v_or_b32_e32 v0, v3, v03225; SI-NEXT: v_sub_i32_e32 v7, vcc, s4, v63226; SI-NEXT: v_or_b32_e32 v3, 0x1000, v03227; SI-NEXT: v_med3_i32 v7, v7, 0, 133228; SI-NEXT: v_lshrrev_b32_e32 v10, v7, v33229; SI-NEXT: v_lshlrev_b32_e32 v7, v7, v103230; SI-NEXT: v_cmp_ne_u32_e32 vcc, v7, v33231; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc3232; SI-NEXT: v_add_i32_e32 v6, vcc, s5, v63233; SI-NEXT: v_lshlrev_b32_e32 v7, 12, v63234; SI-NEXT: v_or_b32_e32 v3, v10, v33235; SI-NEXT: v_or_b32_e32 v7, v0, v73236; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v63237; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc3238; SI-NEXT: v_and_b32_e32 v7, 7, v33239; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v73240; SI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc3241; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v73242; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc3243; SI-NEXT: v_or_b32_e32 v7, v7, v103244; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v33245; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v73246; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v63247; SI-NEXT: v_cvt_f16_f32_e32 v5, v53248; SI-NEXT: v_cvt_f16_f32_e32 v4, v43249; SI-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc3250; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03251; SI-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc3252; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v63253; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13254; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc3255; SI-NEXT: v_and_b32_e32 v1, 0x8000, v13256; SI-NEXT: v_or_b32_e32 v0, v1, v03257; SI-NEXT: v_cvt_f32_f16_e32 v5, v53258; SI-NEXT: v_cvt_f32_f16_e32 v4, v43259; SI-NEXT: v_cvt_f32_f16_e32 v0, v03260; SI-NEXT: v_cvt_f32_f16_e32 v1, v23261; SI-NEXT: s_brev_b32 s4, -23262; SI-NEXT: v_bfi_b32 v0, s4, v0, v43263; SI-NEXT: v_bfi_b32 v1, s4, v1, v53264; SI-NEXT: s_setpc_b64 s[30:31]3265;3266; VI-LABEL: v_copysign_out_v2f16_mag_v2f64_sign_v2f16:3267; VI: ; %bb.0:3268; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3269; VI-NEXT: v_and_b32_e32 v6, 0x1ff, v33270; VI-NEXT: v_or_b32_e32 v2, v6, v23271; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v33272; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23273; VI-NEXT: v_and_b32_e32 v5, 0xffe, v53274; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc3275; VI-NEXT: v_bfe_u32 v3, v3, 20, 113276; VI-NEXT: s_movk_i32 s4, 0x3f13277; VI-NEXT: v_or_b32_e32 v2, v5, v23278; VI-NEXT: v_sub_u32_e32 v6, vcc, s4, v33279; VI-NEXT: v_or_b32_e32 v5, 0x1000, v23280; VI-NEXT: v_med3_i32 v6, v6, 0, 133281; VI-NEXT: v_lshrrev_b32_e32 v7, v6, v53282; VI-NEXT: v_lshlrev_b32_e32 v6, v6, v73283; VI-NEXT: v_cmp_ne_u32_e32 vcc, v6, v53284; VI-NEXT: s_movk_i32 s5, 0xfc103285; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc3286; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v33287; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v33288; VI-NEXT: v_or_b32_e32 v5, v7, v53289; VI-NEXT: v_or_b32_e32 v6, v2, v63290; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v33291; VI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc3292; VI-NEXT: v_and_b32_e32 v6, 7, v53293; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v63294; VI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc3295; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v63296; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc3297; VI-NEXT: v_or_b32_e32 v6, v6, v73298; VI-NEXT: v_lshrrev_b32_e32 v5, 2, v53299; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v63300; VI-NEXT: v_mov_b32_e32 v6, 0x7c003301; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v33302; VI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc3303; VI-NEXT: v_mov_b32_e32 v7, 0x7e003304; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23305; VI-NEXT: s_movk_i32 s6, 0x40f3306; VI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc3307; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v33308; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc3309; VI-NEXT: v_and_b32_e32 v5, 0x1ff, v13310; VI-NEXT: v_or_b32_e32 v0, v5, v03311; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v13312; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03313; VI-NEXT: v_and_b32_e32 v3, 0xffe, v33314; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc3315; VI-NEXT: v_bfe_u32 v1, v1, 20, 113316; VI-NEXT: v_or_b32_e32 v0, v3, v03317; VI-NEXT: v_sub_u32_e32 v5, vcc, s4, v13318; VI-NEXT: v_or_b32_e32 v3, 0x1000, v03319; VI-NEXT: v_med3_i32 v5, v5, 0, 133320; VI-NEXT: v_lshrrev_b32_e32 v8, v5, v33321; VI-NEXT: v_lshlrev_b32_e32 v5, v5, v83322; VI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v33323; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc3324; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v13325; VI-NEXT: v_lshlrev_b32_e32 v5, 12, v13326; VI-NEXT: v_or_b32_e32 v3, v8, v33327; VI-NEXT: v_or_b32_e32 v5, v0, v53328; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v13329; VI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc3330; VI-NEXT: v_and_b32_e32 v5, 7, v33331; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v53332; VI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc3333; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v53334; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc3335; VI-NEXT: v_or_b32_e32 v5, v5, v83336; VI-NEXT: v_lshrrev_b32_e32 v3, 2, v33337; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v53338; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v13339; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc3340; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03341; VI-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc3342; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v13343; VI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc3344; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23345; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v03346; VI-NEXT: v_or_b32_e32 v0, v0, v23347; VI-NEXT: s_mov_b32 s4, 0x7fff7fff3348; VI-NEXT: v_bfi_b32 v0, s4, v0, v43349; VI-NEXT: s_setpc_b64 s[30:31]3350;3351; GFX9-LABEL: v_copysign_out_v2f16_mag_v2f64_sign_v2f16:3352; GFX9: ; %bb.0:3353; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3354; GFX9-NEXT: s_movk_i32 s4, 0x1ff3355; GFX9-NEXT: v_and_or_b32 v0, v1, s4, v03356; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03357; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc3358; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v13359; GFX9-NEXT: s_movk_i32 s5, 0xffe3360; GFX9-NEXT: v_bfe_u32 v6, v1, 20, 113361; GFX9-NEXT: v_and_or_b32 v0, v5, s5, v03362; GFX9-NEXT: v_sub_u32_e32 v7, 0x3f1, v63363; GFX9-NEXT: v_or_b32_e32 v5, 0x1000, v03364; GFX9-NEXT: v_med3_i32 v7, v7, 0, 133365; GFX9-NEXT: v_lshrrev_b32_e32 v8, v7, v53366; GFX9-NEXT: v_lshlrev_b32_e32 v7, v7, v83367; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v7, v53368; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc3369; GFX9-NEXT: v_add_u32_e32 v6, 0xfffffc10, v63370; GFX9-NEXT: v_or_b32_e32 v5, v8, v53371; GFX9-NEXT: v_lshl_or_b32 v7, v6, 12, v03372; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v63373; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc3374; GFX9-NEXT: v_and_b32_e32 v7, 7, v53375; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v73376; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc3377; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v73378; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc3379; GFX9-NEXT: v_or_b32_e32 v7, v7, v83380; GFX9-NEXT: v_lshrrev_b32_e32 v5, 2, v53381; GFX9-NEXT: v_add_u32_e32 v5, v5, v73382; GFX9-NEXT: v_mov_b32_e32 v7, 0x7c003383; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v63384; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc3385; GFX9-NEXT: v_mov_b32_e32 v8, 0x7e003386; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03387; GFX9-NEXT: s_movk_i32 s6, 0x40f3388; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc3389; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v63390; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc3391; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v13392; GFX9-NEXT: s_mov_b32 s7, 0x80003393; GFX9-NEXT: v_and_or_b32 v0, v1, s7, v03394; GFX9-NEXT: v_and_or_b32 v1, v3, s4, v23395; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13396; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc3397; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v33398; GFX9-NEXT: v_bfe_u32 v5, v3, 20, 113399; GFX9-NEXT: v_and_or_b32 v1, v2, s5, v13400; GFX9-NEXT: v_sub_u32_e32 v6, 0x3f1, v53401; GFX9-NEXT: v_or_b32_e32 v2, 0x1000, v13402; GFX9-NEXT: v_med3_i32 v6, v6, 0, 133403; GFX9-NEXT: v_lshrrev_b32_e32 v9, v6, v23404; GFX9-NEXT: v_lshlrev_b32_e32 v6, v6, v93405; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v6, v23406; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc3407; GFX9-NEXT: v_add_u32_e32 v5, 0xfffffc10, v53408; GFX9-NEXT: v_or_b32_e32 v2, v9, v23409; GFX9-NEXT: v_lshl_or_b32 v6, v5, 12, v13410; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v53411; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc3412; GFX9-NEXT: v_and_b32_e32 v6, 7, v23413; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v63414; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc3415; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v63416; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc3417; GFX9-NEXT: v_or_b32_e32 v6, v6, v93418; GFX9-NEXT: v_lshrrev_b32_e32 v2, 2, v23419; GFX9-NEXT: v_add_u32_e32 v2, v2, v63420; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v53421; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc3422; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13423; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc3424; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v53425; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc3426; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v33427; GFX9-NEXT: v_and_or_b32 v1, v2, s7, v13428; GFX9-NEXT: s_mov_b32 s4, 0x50401003429; GFX9-NEXT: v_perm_b32 v0, v1, v0, s43430; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff3431; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v43432; GFX9-NEXT: s_setpc_b64 s[30:31]3433;3434; GFX11-TRUE16-LABEL: v_copysign_out_v2f16_mag_v2f64_sign_v2f16:3435; GFX11-TRUE16: ; %bb.0:3436; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3437; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v23438; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v03439; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v33440; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 20, 113441; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 20, 113442; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v23443; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v13444; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)3445; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v63446; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v63447; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo3448; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v03449; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v5, v23450; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3451; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v73452; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)3453; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v8, v03454; GFX11-TRUE16-NEXT: v_med3_i32 v8, v9, 0, 133455; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x1000, v23456; GFX11-TRUE16-NEXT: v_med3_i32 v5, v5, 0, 133457; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)3458; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x1000, v03459; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, v8, v93460; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3461; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, v5, v103462; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, v8, v113463; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3464; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v5, v123465; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v93466; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v6, 12, v23467; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo3468; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)3469; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v103470; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v11, v83471; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo3472; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v63473; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0xfffffc10, v73474; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)3475; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v12, v53476; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo3477; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v7, 12, v03478; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v73479; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)3480; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v10, v5 :: v_dual_mov_b32 v10, 0x7e003481; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 7, v83482; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 2, v83483; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)3484; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 7, v53485; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 2, v53486; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v93487; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo3488; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v93489; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo3490; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v113491; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3492; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v123493; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo3494; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v113495; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.h3496; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, 03497; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v8, v93498; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo3499; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v23500; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3501; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v133502; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v10, vcc_lo3503; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v63504; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v3, vcc_lo3505; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v03506; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, 0x7c00, v10 :: v_dual_add_nc_u32 v5, v5, v113507; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v73508; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)3509; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v5, vcc_lo3510; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v63511; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo3512; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v73513; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x8000, v12, v23514; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo3515; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v1.h3516; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)3517; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x8000, v12, v03518; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l3519; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3520; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v43521; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]3522;3523; GFX11-FAKE16-LABEL: v_copysign_out_v2f16_mag_v2f64_sign_v2f16:3524; GFX11-FAKE16: ; %bb.0:3525; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3526; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v03527; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v23528; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v13529; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v1, 20, 113530; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v3, 20, 113531; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v03532; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v33533; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, 0x7e003534; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v63535; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0xfffffc10, v63536; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo3537; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v23538; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v13539; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v33540; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)3541; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v5, v03542; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo3543; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v73544; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffe, v8, v23545; GFX11-FAKE16-NEXT: v_med3_i32 v8, v9, 0, 133546; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x1000, v03547; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)3548; GFX11-FAKE16-NEXT: v_med3_i32 v5, v5, 0, 133549; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x1000, v23550; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3551; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, v8, v93552; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, v5, v103553; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3554; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, v8, v113555; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v5, v123556; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)3557; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v93558; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v6, 12, v03559; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo3560; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v103561; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)3562; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v83563; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo3564; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v63565; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0xfffffc10, v73566; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v12, v53567; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo3568; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)3569; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v7, 12, v23570; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v73571; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 7, v83572; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 2, v83573; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)3574; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc_lo3575; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v93576; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3577; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 7, v53578; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 2, v53579; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo3580; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v93581; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo3582; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v103583; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)3584; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v113585; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo3586; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v103587; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v93588; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo3589; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v03590; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3591; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v123592; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v13, vcc_lo3593; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v23594; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v13, vcc_lo3595; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v63596; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, 0x7c00, v8 :: v_dual_add_nc_u32 v5, v5, v103597; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v73598; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)3599; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v5, vcc_lo3600; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v63601; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc_lo3602; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v73603; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)3604; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x8000, v1, v03605; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo3606; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0x8000, v3, v23607; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3608; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401003609; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v43610; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]3611 %mag.trunc = fptrunc <2 x double> %mag to <2 x half>3612 %result = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag.trunc, <2 x half> %sign)3613 ret <2 x half> %result3614}3615 3616define <2 x half> @v_copysign_out_v2f16_mag_v2f16_sign_v2f32(<2 x half> %mag, <2 x float> %sign) {3617; SI-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f32:3618; SI: ; %bb.0:3619; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3620; SI-NEXT: v_cvt_f16_f32_e32 v1, v13621; SI-NEXT: v_cvt_f16_f32_e32 v0, v03622; SI-NEXT: v_cvt_f16_f32_e32 v2, v23623; SI-NEXT: v_cvt_f16_f32_e32 v3, v33624; SI-NEXT: v_cvt_f32_f16_e32 v1, v13625; SI-NEXT: v_cvt_f32_f16_e32 v0, v03626; SI-NEXT: v_cvt_f32_f16_e32 v2, v23627; SI-NEXT: v_cvt_f32_f16_e32 v3, v33628; SI-NEXT: s_brev_b32 s4, -23629; SI-NEXT: v_bfi_b32 v0, s4, v0, v23630; SI-NEXT: v_bfi_b32 v1, s4, v1, v33631; SI-NEXT: s_setpc_b64 s[30:31]3632;3633; VI-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f32:3634; VI: ; %bb.0:3635; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3636; VI-NEXT: v_cvt_f16_f32_sdwa v2, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD3637; VI-NEXT: v_cvt_f16_f32_e32 v1, v13638; VI-NEXT: s_mov_b32 s4, 0x7fff7fff3639; VI-NEXT: v_or_b32_e32 v1, v1, v23640; VI-NEXT: v_bfi_b32 v0, s4, v0, v13641; VI-NEXT: s_setpc_b64 s[30:31]3642;3643; GFX9-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f32:3644; GFX9: ; %bb.0:3645; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3646; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v23647; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v13648; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff3649; GFX9-NEXT: v_pack_b32_f16 v1, v1, v23650; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v13651; GFX9-NEXT: s_setpc_b64 s[30:31]3652;3653; GFX11-TRUE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f32:3654; GFX11-TRUE16: ; %bb.0:3655; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3656; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v23657; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v13658; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3659; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v2.l3660; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v13661; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]3662;3663; GFX11-FAKE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f32:3664; GFX11-FAKE16: ; %bb.0:3665; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3666; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v23667; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v13668; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3669; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v23670; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v13671; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]3672 %sign.trunc = fptrunc <2 x float> %sign to <2 x half>3673 %out = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag, <2 x half> %sign.trunc)3674 ret <2 x half> %out3675}3676 3677define <2 x half> @v_copysign_out_v2f16_mag_v2f16_sign_v2f64(<2 x half> %mag, <2 x double> %sign) {3678; SI-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:3679; SI: ; %bb.0:3680; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3681; SI-NEXT: v_cvt_f16_f32_e32 v0, v03682; SI-NEXT: v_cvt_f16_f32_e32 v1, v13683; SI-NEXT: s_brev_b32 s4, -23684; SI-NEXT: v_cvt_f32_f16_e32 v0, v03685; SI-NEXT: v_cvt_f32_f16_e32 v1, v13686; SI-NEXT: v_bfi_b32 v0, s4, v0, v33687; SI-NEXT: v_bfi_b32 v1, s4, v1, v53688; SI-NEXT: s_setpc_b64 s[30:31]3689;3690; VI-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:3691; VI: ; %bb.0:3692; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3693; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v43694; VI-NEXT: v_and_b32_e32 v2, 0x8000, v23695; VI-NEXT: v_or_b32_e32 v1, v2, v13696; VI-NEXT: s_mov_b32 s4, 0x7fff7fff3697; VI-NEXT: v_bfi_b32 v0, s4, v0, v13698; VI-NEXT: s_setpc_b64 s[30:31]3699;3700; GFX9-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:3701; GFX9: ; %bb.0:3702; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3703; GFX9-NEXT: s_mov_b32 s4, 0x50401003704; GFX9-NEXT: v_perm_b32 v1, v4, v2, s43705; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff3706; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v13707; GFX9-NEXT: s_setpc_b64 s[30:31]3708;3709; GFX11-TRUE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:3710; GFX11-TRUE16: ; %bb.0:3711; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3712; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l3713; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3714; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v23715; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]3716;3717; GFX11-FAKE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:3718; GFX11-FAKE16: ; %bb.0:3719; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3720; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v2, 0x50401003721; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3722; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v13723; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]3724 %sign.trunc = fptrunc <2 x double> %sign to <2 x half>3725 %out = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag, <2 x half> %sign.trunc)3726 ret <2 x half> %out3727}3728 3729define amdgpu_ps <2 x i32> @s_copysign_out_v2f32_mag_v2f16_sign_v2f32(<2 x half> inreg %mag, <2 x float> inreg %sign) {3730; SI-LABEL: s_copysign_out_v2f32_mag_v2f16_sign_v2f32:3731; SI: ; %bb.0:3732; SI-NEXT: v_cvt_f16_f32_e32 v0, s13733; SI-NEXT: v_cvt_f16_f32_e32 v1, s03734; SI-NEXT: s_brev_b32 s0, -23735; SI-NEXT: v_mov_b32_e32 v2, s33736; SI-NEXT: v_cvt_f32_f16_e32 v0, v03737; SI-NEXT: v_cvt_f32_f16_e32 v1, v13738; SI-NEXT: v_bfi_b32 v0, s0, v0, v23739; SI-NEXT: v_mov_b32_e32 v2, s23740; SI-NEXT: v_bfi_b32 v1, s0, v1, v23741; SI-NEXT: v_readfirstlane_b32 s0, v13742; SI-NEXT: v_readfirstlane_b32 s1, v03743; SI-NEXT: ; return to shader part epilog3744;3745; VI-LABEL: s_copysign_out_v2f32_mag_v2f16_sign_v2f32:3746; VI: ; %bb.0:3747; VI-NEXT: s_lshr_b32 s3, s0, 163748; VI-NEXT: v_cvt_f32_f16_e32 v0, s03749; VI-NEXT: v_cvt_f32_f16_e32 v1, s33750; VI-NEXT: s_brev_b32 s0, -23751; VI-NEXT: v_mov_b32_e32 v2, s13752; VI-NEXT: v_bfi_b32 v0, s0, v0, v23753; VI-NEXT: v_mov_b32_e32 v2, s23754; VI-NEXT: v_bfi_b32 v1, s0, v1, v23755; VI-NEXT: v_readfirstlane_b32 s0, v03756; VI-NEXT: v_readfirstlane_b32 s1, v13757; VI-NEXT: ; return to shader part epilog3758;3759; GFX9-LABEL: s_copysign_out_v2f32_mag_v2f16_sign_v2f32:3760; GFX9: ; %bb.0:3761; GFX9-NEXT: s_lshr_b32 s3, s0, 163762; GFX9-NEXT: v_cvt_f32_f16_e32 v0, s03763; GFX9-NEXT: v_cvt_f32_f16_e32 v1, s33764; GFX9-NEXT: s_brev_b32 s0, -23765; GFX9-NEXT: v_mov_b32_e32 v2, s13766; GFX9-NEXT: v_bfi_b32 v0, s0, v0, v23767; GFX9-NEXT: v_mov_b32_e32 v2, s23768; GFX9-NEXT: v_bfi_b32 v1, s0, v1, v23769; GFX9-NEXT: v_readfirstlane_b32 s0, v03770; GFX9-NEXT: v_readfirstlane_b32 s1, v13771; GFX9-NEXT: ; return to shader part epilog3772;3773; GFX11-LABEL: s_copysign_out_v2f32_mag_v2f16_sign_v2f32:3774; GFX11: ; %bb.0:3775; GFX11-NEXT: s_lshr_b32 s3, s0, 163776; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s03777; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s33778; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3779; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s13780; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s23781; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3782; GFX11-NEXT: v_readfirstlane_b32 s0, v03783; GFX11-NEXT: v_readfirstlane_b32 s1, v13784; GFX11-NEXT: ; return to shader part epilog3785 %mag.ext = fpext <2 x half> %mag to <2 x float>3786 %out = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag.ext, <2 x float> %sign)3787 %cast = bitcast <2 x float> %out to <2 x i32>3788 ret <2 x i32> %cast3789}3790 3791define amdgpu_ps <2 x i32> @s_copysign_out_v2f32_mag_v2f32_sign_v2f16(<2 x float> inreg %mag, <2 x half> inreg %sign) {3792; SI-LABEL: s_copysign_out_v2f32_mag_v2f32_sign_v2f16:3793; SI: ; %bb.0:3794; SI-NEXT: v_cvt_f16_f32_e32 v0, s33795; SI-NEXT: v_cvt_f16_f32_e32 v1, s23796; SI-NEXT: s_brev_b32 s2, -23797; SI-NEXT: v_mov_b32_e32 v2, s13798; SI-NEXT: v_cvt_f32_f16_e32 v0, v03799; SI-NEXT: v_cvt_f32_f16_e32 v1, v13800; SI-NEXT: v_bfi_b32 v0, s2, v2, v03801; SI-NEXT: v_mov_b32_e32 v2, s03802; SI-NEXT: v_bfi_b32 v1, s2, v2, v13803; SI-NEXT: v_readfirstlane_b32 s0, v13804; SI-NEXT: v_readfirstlane_b32 s1, v03805; SI-NEXT: ; return to shader part epilog3806;3807; VI-LABEL: s_copysign_out_v2f32_mag_v2f32_sign_v2f16:3808; VI: ; %bb.0:3809; VI-NEXT: s_lshr_b32 s3, s2, 163810; VI-NEXT: v_lshlrev_b32_e64 v0, 16, s23811; VI-NEXT: s_brev_b32 s2, -23812; VI-NEXT: v_mov_b32_e32 v1, s03813; VI-NEXT: v_bfi_b32 v0, s2, v1, v03814; VI-NEXT: v_lshlrev_b32_e64 v1, 16, s33815; VI-NEXT: v_mov_b32_e32 v2, s13816; VI-NEXT: v_bfi_b32 v1, s2, v2, v13817; VI-NEXT: v_readfirstlane_b32 s0, v03818; VI-NEXT: v_readfirstlane_b32 s1, v13819; VI-NEXT: ; return to shader part epilog3820;3821; GFX9-LABEL: s_copysign_out_v2f32_mag_v2f32_sign_v2f16:3822; GFX9: ; %bb.0:3823; GFX9-NEXT: s_lshr_b32 s3, s2, 163824; GFX9-NEXT: v_lshlrev_b32_e64 v0, 16, s23825; GFX9-NEXT: s_brev_b32 s2, -23826; GFX9-NEXT: v_mov_b32_e32 v1, s03827; GFX9-NEXT: v_bfi_b32 v0, s2, v1, v03828; GFX9-NEXT: v_lshlrev_b32_e64 v1, 16, s33829; GFX9-NEXT: v_mov_b32_e32 v2, s13830; GFX9-NEXT: v_bfi_b32 v1, s2, v2, v13831; GFX9-NEXT: v_readfirstlane_b32 s0, v03832; GFX9-NEXT: v_readfirstlane_b32 s1, v13833; GFX9-NEXT: ; return to shader part epilog3834;3835; GFX11-TRUE16-LABEL: s_copysign_out_v2f32_mag_v2f32_sign_v2f16:3836; GFX11-TRUE16: ; %bb.0:3837; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s2, 163838; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s23839; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, s33840; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3841; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v03842; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v13843; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3844; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v03845; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v13846; GFX11-TRUE16-NEXT: ; return to shader part epilog3847;3848; GFX11-FAKE16-LABEL: s_copysign_out_v2f32_mag_v2f32_sign_v2f16:3849; GFX11-FAKE16: ; %bb.0:3850; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s2, 163851; GFX11-FAKE16-NEXT: v_lshlrev_b32_e64 v0, 16, s23852; GFX11-FAKE16-NEXT: v_lshlrev_b32_e64 v1, 16, s33853; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3854; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v03855; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v13856; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3857; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v03858; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s1, v13859; GFX11-FAKE16-NEXT: ; return to shader part epilog3860 %sign.ext = fpext <2 x half> %sign to <2 x float>3861 %out = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag, <2 x float> %sign.ext)3862 %cast = bitcast <2 x float> %out to <2 x i32>3863 ret <2 x i32> %cast3864}3865 3866define amdgpu_ps <4 x i32> @s_copysign_out_v2f64_mag_v2f64_sign_v2f16(<2 x double> inreg %mag, <2 x half> inreg %sign) {3867; SI-LABEL: s_copysign_out_v2f64_mag_v2f64_sign_v2f16:3868; SI: ; %bb.0:3869; SI-NEXT: s_brev_b32 s6, -23870; SI-NEXT: v_mov_b32_e32 v0, s33871; SI-NEXT: v_mov_b32_e32 v1, s53872; SI-NEXT: v_bfi_b32 v0, s6, v0, v13873; SI-NEXT: v_mov_b32_e32 v1, s13874; SI-NEXT: v_mov_b32_e32 v2, s43875; SI-NEXT: v_bfi_b32 v1, s6, v1, v23876; SI-NEXT: v_readfirstlane_b32 s1, v13877; SI-NEXT: v_readfirstlane_b32 s3, v03878; SI-NEXT: ; return to shader part epilog3879;3880; VI-LABEL: s_copysign_out_v2f64_mag_v2f64_sign_v2f16:3881; VI: ; %bb.0:3882; VI-NEXT: v_lshlrev_b32_e64 v0, 16, s43883; VI-NEXT: s_brev_b32 s5, -23884; VI-NEXT: v_mov_b32_e32 v1, s13885; VI-NEXT: s_lshr_b32 s1, s4, 163886; VI-NEXT: v_bfi_b32 v0, s5, v1, v03887; VI-NEXT: v_lshlrev_b32_e64 v1, 16, s13888; VI-NEXT: v_mov_b32_e32 v2, s33889; VI-NEXT: v_bfi_b32 v1, s5, v2, v13890; VI-NEXT: v_readfirstlane_b32 s1, v03891; VI-NEXT: v_readfirstlane_b32 s3, v13892; VI-NEXT: ; return to shader part epilog3893;3894; GFX9-LABEL: s_copysign_out_v2f64_mag_v2f64_sign_v2f16:3895; GFX9: ; %bb.0:3896; GFX9-NEXT: v_lshlrev_b32_e64 v0, 16, s43897; GFX9-NEXT: s_brev_b32 s5, -23898; GFX9-NEXT: v_mov_b32_e32 v1, s13899; GFX9-NEXT: s_lshr_b32 s1, s4, 163900; GFX9-NEXT: v_bfi_b32 v0, s5, v1, v03901; GFX9-NEXT: v_lshlrev_b32_e64 v1, 16, s13902; GFX9-NEXT: v_mov_b32_e32 v2, s33903; GFX9-NEXT: v_bfi_b32 v1, s5, v2, v13904; GFX9-NEXT: v_readfirstlane_b32 s1, v03905; GFX9-NEXT: v_readfirstlane_b32 s3, v13906; GFX9-NEXT: ; return to shader part epilog3907;3908; GFX11-TRUE16-LABEL: s_copysign_out_v2f64_mag_v2f64_sign_v2f16:3909; GFX11-TRUE16: ; %bb.0:3910; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s4, 163911; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s43912; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, s53913; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3914; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v03915; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v13916; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3917; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v03918; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v13919; GFX11-TRUE16-NEXT: ; return to shader part epilog3920;3921; GFX11-FAKE16-LABEL: s_copysign_out_v2f64_mag_v2f64_sign_v2f16:3922; GFX11-FAKE16: ; %bb.0:3923; GFX11-FAKE16-NEXT: v_lshlrev_b32_e64 v0, 16, s43924; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s4, 163925; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)3926; GFX11-FAKE16-NEXT: v_lshlrev_b32_e64 v1, 16, s43927; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v03928; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3929; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v13930; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s1, v03931; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3932; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v13933; GFX11-FAKE16-NEXT: ; return to shader part epilog3934 %sign.ext = fpext <2 x half> %sign to <2 x double>3935 %out = call <2 x double> @llvm.copysign.v2f64(<2 x double> %mag, <2 x double> %sign.ext)3936 %cast = bitcast <2 x double> %out to <4 x i32>3937 ret <4 x i32> %cast3938}3939 3940define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f32_sign_v2f16(<2 x float> inreg %mag, <2 x half> inreg %sign) {3941; SI-LABEL: s_copysign_out_v2f16_mag_v2f32_sign_v2f16:3942; SI: ; %bb.0:3943; SI-NEXT: v_cvt_f16_f32_e32 v0, s33944; SI-NEXT: v_cvt_f16_f32_e32 v1, s13945; SI-NEXT: v_cvt_f16_f32_e32 v2, s23946; SI-NEXT: v_cvt_f16_f32_e32 v3, s03947; SI-NEXT: v_cvt_f32_f16_e32 v0, v03948; SI-NEXT: v_cvt_f32_f16_e32 v1, v13949; SI-NEXT: v_cvt_f32_f16_e32 v2, v23950; SI-NEXT: v_cvt_f32_f16_e32 v3, v33951; SI-NEXT: s_brev_b32 s0, -23952; SI-NEXT: v_bfi_b32 v0, s0, v1, v03953; SI-NEXT: v_cvt_f16_f32_e32 v0, v03954; SI-NEXT: v_bfi_b32 v1, s0, v3, v23955; SI-NEXT: v_cvt_f16_f32_e32 v1, v13956; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v03957; SI-NEXT: v_or_b32_e32 v0, v1, v03958; SI-NEXT: v_readfirstlane_b32 s0, v03959; SI-NEXT: ; return to shader part epilog3960;3961; VI-LABEL: s_copysign_out_v2f16_mag_v2f32_sign_v2f16:3962; VI: ; %bb.0:3963; VI-NEXT: v_mov_b32_e32 v0, s13964; VI-NEXT: v_cvt_f16_f32_e32 v1, s03965; VI-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD3966; VI-NEXT: s_mov_b32 s0, 0x7fff7fff3967; VI-NEXT: v_or_b32_e32 v0, v1, v03968; VI-NEXT: v_mov_b32_e32 v1, s23969; VI-NEXT: v_bfi_b32 v0, s0, v0, v13970; VI-NEXT: v_readfirstlane_b32 s0, v03971; VI-NEXT: ; return to shader part epilog3972;3973; GFX9-LABEL: s_copysign_out_v2f16_mag_v2f32_sign_v2f16:3974; GFX9: ; %bb.0:3975; GFX9-NEXT: v_cvt_f16_f32_e32 v0, s13976; GFX9-NEXT: v_cvt_f16_f32_e32 v1, s03977; GFX9-NEXT: s_mov_b32 s0, 0x7fff7fff3978; GFX9-NEXT: v_pack_b32_f16 v0, v1, v03979; GFX9-NEXT: v_mov_b32_e32 v1, s23980; GFX9-NEXT: v_bfi_b32 v0, s0, v0, v13981; GFX9-NEXT: v_readfirstlane_b32 s0, v03982; GFX9-NEXT: ; return to shader part epilog3983;3984; GFX11-TRUE16-LABEL: s_copysign_out_v2f16_mag_v2f32_sign_v2f16:3985; GFX11-TRUE16: ; %bb.0:3986; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s13987; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s03988; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3989; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l3990; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, s23991; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3992; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v03993; GFX11-TRUE16-NEXT: ; return to shader part epilog3994;3995; GFX11-FAKE16-LABEL: s_copysign_out_v2f16_mag_v2f32_sign_v2f16:3996; GFX11-FAKE16: ; %bb.0:3997; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s13998; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, s03999; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4000; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v04001; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, s24002; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4003; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v04004; GFX11-FAKE16-NEXT: ; return to shader part epilog4005 %mag.trunc = fptrunc <2 x float> %mag to <2 x half>4006 %out = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag.trunc, <2 x half> %sign)4007 %cast = bitcast <2 x half> %out to i324008 ret i32 %cast4009}4010 4011define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> inreg %mag, <2 x half> inreg %sign) {4012; SI-LABEL: s_copysign_out_v2f16_mag_v2f64_sign_v2f16:4013; SI: ; %bb.0:4014; SI-NEXT: v_cvt_f16_f32_e32 v1, s44015; SI-NEXT: s_lshr_b32 s4, s1, 84016; SI-NEXT: s_and_b32 s6, s4, 0xffe4017; SI-NEXT: s_and_b32 s4, s1, 0x1ff4018; SI-NEXT: s_or_b32 s0, s4, s04019; SI-NEXT: v_cvt_f16_f32_e32 v0, s54020; SI-NEXT: s_cselect_b64 s[4:5], -1, 04021; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]4022; SI-NEXT: v_readfirstlane_b32 s0, v24023; SI-NEXT: s_bfe_u32 s5, s1, 0xb00144024; SI-NEXT: s_or_b32 s0, s6, s04025; SI-NEXT: s_sub_i32 s6, 0x3f1, s54026; SI-NEXT: v_med3_i32 v2, s6, 0, 134027; SI-NEXT: s_or_b32 s4, s0, 0x10004028; SI-NEXT: v_readfirstlane_b32 s6, v24029; SI-NEXT: s_lshr_b32 s7, s4, s64030; SI-NEXT: s_lshl_b32 s6, s7, s64031; SI-NEXT: s_cmp_lg_u32 s6, s44032; SI-NEXT: s_cselect_b32 s4, 1, 04033; SI-NEXT: s_addk_i32 s5, 0xfc104034; SI-NEXT: s_lshl_b32 s6, s5, 124035; SI-NEXT: s_or_b32 s4, s7, s44036; SI-NEXT: s_or_b32 s6, s0, s64037; SI-NEXT: s_cmp_lt_i32 s5, 14038; SI-NEXT: s_cselect_b32 s4, s4, s64039; SI-NEXT: s_and_b32 s6, s4, 74040; SI-NEXT: s_cmp_gt_i32 s6, 54041; SI-NEXT: s_cselect_b32 s7, 1, 04042; SI-NEXT: s_cmp_eq_u32 s6, 34043; SI-NEXT: s_cselect_b32 s6, 1, 04044; SI-NEXT: s_or_b32 s6, s6, s74045; SI-NEXT: s_lshr_b32 s4, s4, 24046; SI-NEXT: s_add_i32 s4, s4, s64047; SI-NEXT: s_cmp_lt_i32 s5, 314048; SI-NEXT: s_cselect_b32 s4, s4, 0x7c004049; SI-NEXT: s_cmp_lg_u32 s0, 04050; SI-NEXT: s_movk_i32 s6, 0x7e004051; SI-NEXT: s_cselect_b32 s0, s6, 0x7c004052; SI-NEXT: s_cmpk_eq_i32 s5, 0x40f4053; SI-NEXT: s_cselect_b32 s0, s0, s44054; SI-NEXT: s_lshr_b32 s1, s1, 164055; SI-NEXT: s_and_b32 s1, s1, 0x80004056; SI-NEXT: s_or_b32 s4, s1, s04057; SI-NEXT: s_lshr_b32 s0, s3, 84058; SI-NEXT: s_and_b32 s5, s0, 0xffe4059; SI-NEXT: s_and_b32 s0, s3, 0x1ff4060; SI-NEXT: s_or_b32 s0, s0, s24061; SI-NEXT: s_cselect_b64 s[0:1], -1, 04062; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]4063; SI-NEXT: v_readfirstlane_b32 s0, v24064; SI-NEXT: s_bfe_u32 s2, s3, 0xb00144065; SI-NEXT: s_or_b32 s0, s5, s04066; SI-NEXT: s_sub_i32 s5, 0x3f1, s24067; SI-NEXT: v_med3_i32 v2, s5, 0, 134068; SI-NEXT: s_or_b32 s1, s0, 0x10004069; SI-NEXT: v_readfirstlane_b32 s5, v24070; SI-NEXT: s_lshr_b32 s7, s1, s54071; SI-NEXT: s_lshl_b32 s5, s7, s54072; SI-NEXT: s_cmp_lg_u32 s5, s14073; SI-NEXT: s_cselect_b32 s1, 1, 04074; SI-NEXT: s_addk_i32 s2, 0xfc104075; SI-NEXT: s_lshl_b32 s5, s2, 124076; SI-NEXT: s_or_b32 s1, s7, s14077; SI-NEXT: s_or_b32 s5, s0, s54078; SI-NEXT: s_cmp_lt_i32 s2, 14079; SI-NEXT: s_cselect_b32 s1, s1, s54080; SI-NEXT: s_and_b32 s5, s1, 74081; SI-NEXT: s_cmp_gt_i32 s5, 54082; SI-NEXT: s_cselect_b32 s7, 1, 04083; SI-NEXT: s_cmp_eq_u32 s5, 34084; SI-NEXT: s_cselect_b32 s5, 1, 04085; SI-NEXT: s_or_b32 s5, s5, s74086; SI-NEXT: s_lshr_b32 s1, s1, 24087; SI-NEXT: s_add_i32 s1, s1, s54088; SI-NEXT: s_cmp_lt_i32 s2, 314089; SI-NEXT: s_cselect_b32 s1, s1, 0x7c004090; SI-NEXT: s_cmp_lg_u32 s0, 04091; SI-NEXT: s_cselect_b32 s0, s6, 0x7c004092; SI-NEXT: s_cmpk_eq_i32 s2, 0x40f4093; SI-NEXT: s_cselect_b32 s0, s0, s14094; SI-NEXT: s_lshr_b32 s1, s3, 164095; SI-NEXT: s_and_b32 s1, s1, 0x80004096; SI-NEXT: s_or_b32 s0, s1, s04097; SI-NEXT: v_cvt_f32_f16_e32 v0, v04098; SI-NEXT: v_cvt_f32_f16_e32 v2, s04099; SI-NEXT: v_cvt_f32_f16_e32 v1, v14100; SI-NEXT: v_cvt_f32_f16_e32 v3, s44101; SI-NEXT: s_brev_b32 s0, -24102; SI-NEXT: v_bfi_b32 v0, s0, v2, v04103; SI-NEXT: v_cvt_f16_f32_e32 v0, v04104; SI-NEXT: v_bfi_b32 v1, s0, v3, v14105; SI-NEXT: v_cvt_f16_f32_e32 v1, v14106; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v04107; SI-NEXT: v_or_b32_e32 v0, v1, v04108; SI-NEXT: v_readfirstlane_b32 s0, v04109; SI-NEXT: ; return to shader part epilog4110;4111; VI-LABEL: s_copysign_out_v2f16_mag_v2f64_sign_v2f16:4112; VI: ; %bb.0:4113; VI-NEXT: s_lshr_b32 s5, s3, 84114; VI-NEXT: s_and_b32 s5, s5, 0xffe4115; VI-NEXT: s_and_b32 s6, s3, 0x1ff4116; VI-NEXT: s_or_b32 s2, s6, s24117; VI-NEXT: s_cselect_b64 s[6:7], -1, 04118; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]4119; VI-NEXT: s_bfe_u32 s3, s3, 0xb00144120; VI-NEXT: v_readfirstlane_b32 s2, v04121; VI-NEXT: s_sub_i32 s6, 0x3f1, s34122; VI-NEXT: s_or_b32 s2, s5, s24123; VI-NEXT: v_med3_i32 v0, s6, 0, 134124; VI-NEXT: s_or_b32 s5, s2, 0x10004125; VI-NEXT: v_readfirstlane_b32 s6, v04126; VI-NEXT: s_lshr_b32 s7, s5, s64127; VI-NEXT: s_lshl_b32 s6, s7, s64128; VI-NEXT: s_cmp_lg_u32 s6, s54129; VI-NEXT: s_cselect_b32 s5, 1, 04130; VI-NEXT: s_addk_i32 s3, 0xfc104131; VI-NEXT: s_lshl_b32 s6, s3, 124132; VI-NEXT: s_or_b32 s5, s7, s54133; VI-NEXT: s_or_b32 s6, s2, s64134; VI-NEXT: s_cmp_lt_i32 s3, 14135; VI-NEXT: s_cselect_b32 s5, s5, s64136; VI-NEXT: s_and_b32 s6, s5, 74137; VI-NEXT: s_cmp_gt_i32 s6, 54138; VI-NEXT: s_cselect_b32 s7, 1, 04139; VI-NEXT: s_cmp_eq_u32 s6, 34140; VI-NEXT: s_cselect_b32 s6, 1, 04141; VI-NEXT: s_or_b32 s6, s6, s74142; VI-NEXT: s_lshr_b32 s5, s5, 24143; VI-NEXT: s_add_i32 s5, s5, s64144; VI-NEXT: s_cmp_lt_i32 s3, 314145; VI-NEXT: s_cselect_b32 s5, s5, 0x7c004146; VI-NEXT: s_cmp_lg_u32 s2, 04147; VI-NEXT: s_movk_i32 s6, 0x7e004148; VI-NEXT: s_cselect_b32 s2, s6, 0x7c004149; VI-NEXT: s_cmpk_eq_i32 s3, 0x40f4150; VI-NEXT: s_cselect_b32 s2, s2, s54151; VI-NEXT: s_lshl_b32 s5, s2, 164152; VI-NEXT: s_lshr_b32 s2, s1, 84153; VI-NEXT: s_and_b32 s7, s2, 0xffe4154; VI-NEXT: s_and_b32 s2, s1, 0x1ff4155; VI-NEXT: s_or_b32 s0, s2, s04156; VI-NEXT: s_cselect_b64 s[2:3], -1, 04157; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]4158; VI-NEXT: s_bfe_u32 s1, s1, 0xb00144159; VI-NEXT: v_readfirstlane_b32 s0, v04160; VI-NEXT: s_sub_i32 s3, 0x3f1, s14161; VI-NEXT: s_or_b32 s0, s7, s04162; VI-NEXT: v_med3_i32 v0, s3, 0, 134163; VI-NEXT: s_or_b32 s2, s0, 0x10004164; VI-NEXT: v_readfirstlane_b32 s3, v04165; VI-NEXT: s_lshr_b32 s7, s2, s34166; VI-NEXT: s_lshl_b32 s3, s7, s34167; VI-NEXT: s_cmp_lg_u32 s3, s24168; VI-NEXT: s_cselect_b32 s2, 1, 04169; VI-NEXT: s_addk_i32 s1, 0xfc104170; VI-NEXT: s_lshl_b32 s3, s1, 124171; VI-NEXT: s_or_b32 s2, s7, s24172; VI-NEXT: s_or_b32 s3, s0, s34173; VI-NEXT: s_cmp_lt_i32 s1, 14174; VI-NEXT: s_cselect_b32 s2, s2, s34175; VI-NEXT: s_and_b32 s3, s2, 74176; VI-NEXT: s_cmp_gt_i32 s3, 54177; VI-NEXT: s_cselect_b32 s7, 1, 04178; VI-NEXT: s_cmp_eq_u32 s3, 34179; VI-NEXT: s_cselect_b32 s3, 1, 04180; VI-NEXT: s_or_b32 s3, s3, s74181; VI-NEXT: s_lshr_b32 s2, s2, 24182; VI-NEXT: s_add_i32 s2, s2, s34183; VI-NEXT: s_cmp_lt_i32 s1, 314184; VI-NEXT: s_cselect_b32 s2, s2, 0x7c004185; VI-NEXT: s_cmp_lg_u32 s0, 04186; VI-NEXT: s_cselect_b32 s0, s6, 0x7c004187; VI-NEXT: s_cmpk_eq_i32 s1, 0x40f4188; VI-NEXT: s_cselect_b32 s0, s0, s24189; VI-NEXT: s_and_b32 s0, s0, 0x7fff4190; VI-NEXT: s_or_b32 s0, s0, s54191; VI-NEXT: s_mov_b32 s1, 0x7fff7fff4192; VI-NEXT: v_mov_b32_e32 v0, s04193; VI-NEXT: v_mov_b32_e32 v1, s44194; VI-NEXT: v_bfi_b32 v0, s1, v0, v14195; VI-NEXT: v_readfirstlane_b32 s0, v04196; VI-NEXT: ; return to shader part epilog4197;4198; GFX9-LABEL: s_copysign_out_v2f16_mag_v2f64_sign_v2f16:4199; GFX9: ; %bb.0:4200; GFX9-NEXT: s_lshr_b32 s5, s3, 84201; GFX9-NEXT: s_and_b32 s5, s5, 0xffe4202; GFX9-NEXT: s_and_b32 s6, s3, 0x1ff4203; GFX9-NEXT: s_or_b32 s2, s6, s24204; GFX9-NEXT: s_cselect_b64 s[6:7], -1, 04205; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]4206; GFX9-NEXT: s_bfe_u32 s6, s3, 0xb00144207; GFX9-NEXT: v_readfirstlane_b32 s2, v04208; GFX9-NEXT: s_sub_i32 s7, 0x3f1, s64209; GFX9-NEXT: s_or_b32 s2, s5, s24210; GFX9-NEXT: v_med3_i32 v0, s7, 0, 134211; GFX9-NEXT: s_or_b32 s5, s2, 0x10004212; GFX9-NEXT: v_readfirstlane_b32 s7, v04213; GFX9-NEXT: s_lshr_b32 s8, s5, s74214; GFX9-NEXT: s_lshl_b32 s7, s8, s74215; GFX9-NEXT: s_cmp_lg_u32 s7, s54216; GFX9-NEXT: s_cselect_b32 s5, 1, 04217; GFX9-NEXT: s_addk_i32 s6, 0xfc104218; GFX9-NEXT: s_lshl_b32 s7, s6, 124219; GFX9-NEXT: s_or_b32 s5, s8, s54220; GFX9-NEXT: s_or_b32 s7, s2, s74221; GFX9-NEXT: s_cmp_lt_i32 s6, 14222; GFX9-NEXT: s_cselect_b32 s5, s5, s74223; GFX9-NEXT: s_and_b32 s7, s5, 74224; GFX9-NEXT: s_cmp_gt_i32 s7, 54225; GFX9-NEXT: s_cselect_b32 s8, 1, 04226; GFX9-NEXT: s_cmp_eq_u32 s7, 34227; GFX9-NEXT: s_cselect_b32 s7, 1, 04228; GFX9-NEXT: s_or_b32 s7, s7, s84229; GFX9-NEXT: s_lshr_b32 s5, s5, 24230; GFX9-NEXT: s_add_i32 s5, s5, s74231; GFX9-NEXT: s_cmp_lt_i32 s6, 314232; GFX9-NEXT: s_cselect_b32 s5, s5, 0x7c004233; GFX9-NEXT: s_cmp_lg_u32 s2, 04234; GFX9-NEXT: s_movk_i32 s7, 0x7e004235; GFX9-NEXT: s_cselect_b32 s2, s7, 0x7c004236; GFX9-NEXT: s_cmpk_eq_i32 s6, 0x40f4237; GFX9-NEXT: s_cselect_b32 s2, s2, s54238; GFX9-NEXT: s_lshr_b32 s3, s3, 164239; GFX9-NEXT: s_and_b32 s3, s3, 0x80004240; GFX9-NEXT: s_or_b32 s5, s3, s24241; GFX9-NEXT: s_lshr_b32 s2, s1, 84242; GFX9-NEXT: s_and_b32 s6, s2, 0xffe4243; GFX9-NEXT: s_and_b32 s2, s1, 0x1ff4244; GFX9-NEXT: s_or_b32 s0, s2, s04245; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 04246; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]4247; GFX9-NEXT: v_readfirstlane_b32 s0, v04248; GFX9-NEXT: s_bfe_u32 s3, s1, 0xb00144249; GFX9-NEXT: s_or_b32 s0, s6, s04250; GFX9-NEXT: s_sub_i32 s6, 0x3f1, s34251; GFX9-NEXT: v_med3_i32 v0, s6, 0, 134252; GFX9-NEXT: s_or_b32 s2, s0, 0x10004253; GFX9-NEXT: v_readfirstlane_b32 s6, v04254; GFX9-NEXT: s_lshr_b32 s8, s2, s64255; GFX9-NEXT: s_lshl_b32 s6, s8, s64256; GFX9-NEXT: s_cmp_lg_u32 s6, s24257; GFX9-NEXT: s_cselect_b32 s2, 1, 04258; GFX9-NEXT: s_addk_i32 s3, 0xfc104259; GFX9-NEXT: s_lshl_b32 s6, s3, 124260; GFX9-NEXT: s_or_b32 s2, s8, s24261; GFX9-NEXT: s_or_b32 s6, s0, s64262; GFX9-NEXT: s_cmp_lt_i32 s3, 14263; GFX9-NEXT: s_cselect_b32 s2, s2, s64264; GFX9-NEXT: s_and_b32 s6, s2, 74265; GFX9-NEXT: s_cmp_gt_i32 s6, 54266; GFX9-NEXT: s_cselect_b32 s8, 1, 04267; GFX9-NEXT: s_cmp_eq_u32 s6, 34268; GFX9-NEXT: s_cselect_b32 s6, 1, 04269; GFX9-NEXT: s_or_b32 s6, s6, s84270; GFX9-NEXT: s_lshr_b32 s2, s2, 24271; GFX9-NEXT: s_add_i32 s2, s2, s64272; GFX9-NEXT: s_cmp_lt_i32 s3, 314273; GFX9-NEXT: s_cselect_b32 s2, s2, 0x7c004274; GFX9-NEXT: s_cmp_lg_u32 s0, 04275; GFX9-NEXT: s_cselect_b32 s0, s7, 0x7c004276; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x40f4277; GFX9-NEXT: s_cselect_b32 s0, s0, s24278; GFX9-NEXT: s_lshr_b32 s1, s1, 164279; GFX9-NEXT: s_and_b32 s1, s1, 0x80004280; GFX9-NEXT: s_or_b32 s0, s1, s04281; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s54282; GFX9-NEXT: s_mov_b32 s1, 0x7fff7fff4283; GFX9-NEXT: v_mov_b32_e32 v0, s04284; GFX9-NEXT: v_mov_b32_e32 v1, s44285; GFX9-NEXT: v_bfi_b32 v0, s1, v0, v14286; GFX9-NEXT: v_readfirstlane_b32 s0, v04287; GFX9-NEXT: ; return to shader part epilog4288;4289; GFX11-LABEL: s_copysign_out_v2f16_mag_v2f64_sign_v2f16:4290; GFX11: ; %bb.0:4291; GFX11-NEXT: s_lshr_b32 s5, s3, 84292; GFX11-NEXT: s_and_b32 s6, s3, 0x1ff4293; GFX11-NEXT: s_and_b32 s5, s5, 0xffe4294; GFX11-NEXT: s_or_b32 s2, s6, s24295; GFX11-NEXT: s_cselect_b32 s2, -1, 04296; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)4297; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s24298; GFX11-NEXT: s_bfe_u32 s2, s3, 0xb00144299; GFX11-NEXT: s_sub_i32 s6, 0x3f1, s24300; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)4301; GFX11-NEXT: v_med3_i32 v1, s6, 0, 134302; GFX11-NEXT: v_readfirstlane_b32 s6, v04303; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)4304; GFX11-NEXT: v_readfirstlane_b32 s7, v14305; GFX11-NEXT: s_or_b32 s5, s5, s64306; GFX11-NEXT: s_or_b32 s6, s5, 0x10004307; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4308; GFX11-NEXT: s_lshr_b32 s8, s6, s74309; GFX11-NEXT: s_lshl_b32 s7, s8, s74310; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)4311; GFX11-NEXT: s_cmp_lg_u32 s7, s64312; GFX11-NEXT: s_cselect_b32 s6, 1, 04313; GFX11-NEXT: s_addk_i32 s2, 0xfc104314; GFX11-NEXT: s_or_b32 s6, s8, s64315; GFX11-NEXT: s_lshl_b32 s7, s2, 124316; GFX11-NEXT: s_or_b32 s7, s5, s74317; GFX11-NEXT: s_cmp_lt_i32 s2, 14318; GFX11-NEXT: s_cselect_b32 s6, s6, s74319; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4320; GFX11-NEXT: s_and_b32 s7, s6, 74321; GFX11-NEXT: s_cmp_gt_i32 s7, 54322; GFX11-NEXT: s_cselect_b32 s8, 1, 04323; GFX11-NEXT: s_cmp_eq_u32 s7, 34324; GFX11-NEXT: s_cselect_b32 s7, 1, 04325; GFX11-NEXT: s_lshr_b32 s6, s6, 24326; GFX11-NEXT: s_or_b32 s7, s7, s84327; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4328; GFX11-NEXT: s_add_i32 s6, s6, s74329; GFX11-NEXT: s_cmp_lt_i32 s2, 314330; GFX11-NEXT: s_movk_i32 s7, 0x7e004331; GFX11-NEXT: s_cselect_b32 s6, s6, 0x7c004332; GFX11-NEXT: s_cmp_lg_u32 s5, 04333; GFX11-NEXT: s_cselect_b32 s5, s7, 0x7c004334; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x40f4335; GFX11-NEXT: s_cselect_b32 s2, s5, s64336; GFX11-NEXT: s_lshr_b32 s3, s3, 164337; GFX11-NEXT: s_lshr_b32 s5, s1, 84338; GFX11-NEXT: s_and_b32 s3, s3, 0x80004339; GFX11-NEXT: s_and_b32 s6, s1, 0x1ff4340; GFX11-NEXT: s_and_b32 s5, s5, 0xffe4341; GFX11-NEXT: s_or_b32 s2, s3, s24342; GFX11-NEXT: s_or_b32 s0, s6, s04343; GFX11-NEXT: s_cselect_b32 s0, -1, 04344; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)4345; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s04346; GFX11-NEXT: s_bfe_u32 s0, s1, 0xb00144347; GFX11-NEXT: s_sub_i32 s3, 0x3f1, s04348; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)4349; GFX11-NEXT: v_med3_i32 v1, s3, 0, 134350; GFX11-NEXT: v_readfirstlane_b32 s3, v04351; GFX11-NEXT: v_mov_b32_e32 v0, s44352; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)4353; GFX11-NEXT: v_readfirstlane_b32 s6, v14354; GFX11-NEXT: s_or_b32 s3, s5, s34355; GFX11-NEXT: s_or_b32 s5, s3, 0x10004356; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4357; GFX11-NEXT: s_lshr_b32 s8, s5, s64358; GFX11-NEXT: s_lshl_b32 s6, s8, s64359; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)4360; GFX11-NEXT: s_cmp_lg_u32 s6, s54361; GFX11-NEXT: s_cselect_b32 s5, 1, 04362; GFX11-NEXT: s_addk_i32 s0, 0xfc104363; GFX11-NEXT: s_or_b32 s5, s8, s54364; GFX11-NEXT: s_lshl_b32 s6, s0, 124365; GFX11-NEXT: s_or_b32 s6, s3, s64366; GFX11-NEXT: s_cmp_lt_i32 s0, 14367; GFX11-NEXT: s_cselect_b32 s5, s5, s64368; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4369; GFX11-NEXT: s_and_b32 s6, s5, 74370; GFX11-NEXT: s_cmp_gt_i32 s6, 54371; GFX11-NEXT: s_cselect_b32 s8, 1, 04372; GFX11-NEXT: s_cmp_eq_u32 s6, 34373; GFX11-NEXT: s_cselect_b32 s6, 1, 04374; GFX11-NEXT: s_lshr_b32 s5, s5, 24375; GFX11-NEXT: s_or_b32 s6, s6, s84376; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4377; GFX11-NEXT: s_add_i32 s5, s5, s64378; GFX11-NEXT: s_cmp_lt_i32 s0, 314379; GFX11-NEXT: s_cselect_b32 s5, s5, 0x7c004380; GFX11-NEXT: s_cmp_lg_u32 s3, 04381; GFX11-NEXT: s_cselect_b32 s3, s7, 0x7c004382; GFX11-NEXT: s_cmpk_eq_i32 s0, 0x40f4383; GFX11-NEXT: s_cselect_b32 s0, s3, s54384; GFX11-NEXT: s_lshr_b32 s1, s1, 164385; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4386; GFX11-NEXT: s_and_b32 s1, s1, 0x80004387; GFX11-NEXT: s_or_b32 s0, s1, s04388; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4389; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s24390; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v04391; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4392; GFX11-NEXT: v_readfirstlane_b32 s0, v04393; GFX11-NEXT: ; return to shader part epilog4394 %mag.trunc = fptrunc <2 x double> %mag to <2 x half>4395 %result = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag.trunc, <2 x half> %sign)4396 %cast = bitcast <2 x half> %result to i324397 ret i32 %cast4398}4399 4400define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f16_sign_v2f32(<2 x half> inreg %mag, <2 x float> inreg %sign) {4401; SI-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f32:4402; SI: ; %bb.0:4403; SI-NEXT: v_cvt_f16_f32_e32 v0, s14404; SI-NEXT: v_cvt_f16_f32_e32 v1, s34405; SI-NEXT: v_cvt_f16_f32_e32 v2, s04406; SI-NEXT: v_cvt_f16_f32_e32 v3, s24407; SI-NEXT: v_cvt_f32_f16_e32 v0, v04408; SI-NEXT: v_cvt_f32_f16_e32 v1, v14409; SI-NEXT: v_cvt_f32_f16_e32 v2, v24410; SI-NEXT: v_cvt_f32_f16_e32 v3, v34411; SI-NEXT: s_brev_b32 s0, -24412; SI-NEXT: v_bfi_b32 v0, s0, v0, v14413; SI-NEXT: v_cvt_f16_f32_e32 v0, v04414; SI-NEXT: v_bfi_b32 v1, s0, v2, v34415; SI-NEXT: v_cvt_f16_f32_e32 v1, v14416; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v04417; SI-NEXT: v_or_b32_e32 v0, v1, v04418; SI-NEXT: v_readfirstlane_b32 s0, v04419; SI-NEXT: ; return to shader part epilog4420;4421; VI-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f32:4422; VI: ; %bb.0:4423; VI-NEXT: v_mov_b32_e32 v0, s24424; VI-NEXT: v_cvt_f16_f32_e32 v1, s14425; VI-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD4426; VI-NEXT: s_mov_b32 s1, 0x7fff7fff4427; VI-NEXT: v_or_b32_e32 v0, v1, v04428; VI-NEXT: v_mov_b32_e32 v1, s04429; VI-NEXT: v_bfi_b32 v0, s1, v1, v04430; VI-NEXT: v_readfirstlane_b32 s0, v04431; VI-NEXT: ; return to shader part epilog4432;4433; GFX9-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f32:4434; GFX9: ; %bb.0:4435; GFX9-NEXT: v_cvt_f16_f32_e32 v0, s24436; GFX9-NEXT: v_cvt_f16_f32_e32 v1, s14437; GFX9-NEXT: s_mov_b32 s1, 0x7fff7fff4438; GFX9-NEXT: v_pack_b32_f16 v0, v1, v04439; GFX9-NEXT: v_mov_b32_e32 v1, s04440; GFX9-NEXT: v_bfi_b32 v0, s1, v1, v04441; GFX9-NEXT: v_readfirstlane_b32 s0, v04442; GFX9-NEXT: ; return to shader part epilog4443;4444; GFX11-TRUE16-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f32:4445; GFX11-TRUE16: ; %bb.0:4446; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s24447; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s14448; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4449; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l4450; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v04451; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4452; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v04453; GFX11-TRUE16-NEXT: ; return to shader part epilog4454;4455; GFX11-FAKE16-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f32:4456; GFX11-FAKE16: ; %bb.0:4457; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s24458; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, s14459; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4460; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v04461; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v04462; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4463; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v04464; GFX11-FAKE16-NEXT: ; return to shader part epilog4465 %sign.trunc = fptrunc <2 x float> %sign to <2 x half>4466 %out = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag, <2 x half> %sign.trunc)4467 %cast = bitcast <2 x half> %out to i324468 ret i32 %cast4469}4470 4471define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f16_sign_v2f64(<2 x half> inreg %mag, <2 x double> inreg %sign) {4472; SI-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f64:4473; SI: ; %bb.0:4474; SI-NEXT: v_cvt_f16_f32_e32 v0, s14475; SI-NEXT: v_cvt_f16_f32_e32 v1, s04476; SI-NEXT: s_brev_b32 s0, -24477; SI-NEXT: v_mov_b32_e32 v2, s54478; SI-NEXT: v_cvt_f32_f16_e32 v0, v04479; SI-NEXT: v_cvt_f32_f16_e32 v1, v14480; SI-NEXT: v_bfi_b32 v0, s0, v0, v24481; SI-NEXT: v_mov_b32_e32 v2, s34482; SI-NEXT: v_cvt_f16_f32_e32 v0, v04483; SI-NEXT: v_bfi_b32 v1, s0, v1, v24484; SI-NEXT: v_cvt_f16_f32_e32 v1, v14485; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v04486; SI-NEXT: v_or_b32_e32 v0, v1, v04487; SI-NEXT: v_readfirstlane_b32 s0, v04488; SI-NEXT: ; return to shader part epilog4489;4490; VI-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f64:4491; VI: ; %bb.0:4492; VI-NEXT: s_lshl_b32 s1, s4, 164493; VI-NEXT: s_and_b32 s2, s2, 0x80004494; VI-NEXT: s_or_b32 s1, s2, s14495; VI-NEXT: s_mov_b32 s2, 0x7fff7fff4496; VI-NEXT: v_mov_b32_e32 v0, s04497; VI-NEXT: v_mov_b32_e32 v1, s14498; VI-NEXT: v_bfi_b32 v0, s2, v0, v14499; VI-NEXT: v_readfirstlane_b32 s0, v04500; VI-NEXT: ; return to shader part epilog4501;4502; GFX9-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f64:4503; GFX9: ; %bb.0:4504; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s44505; GFX9-NEXT: s_mov_b32 s2, 0x7fff7fff4506; GFX9-NEXT: v_mov_b32_e32 v0, s04507; GFX9-NEXT: v_mov_b32_e32 v1, s14508; GFX9-NEXT: v_bfi_b32 v0, s2, v0, v14509; GFX9-NEXT: v_readfirstlane_b32 s0, v04510; GFX9-NEXT: ; return to shader part epilog4511;4512; GFX11-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f64:4513; GFX11: ; %bb.0:4514; GFX11-NEXT: s_pack_ll_b32_b16 s1, s2, s44515; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)4516; GFX11-NEXT: v_mov_b32_e32 v0, s14517; GFX11-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v04518; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4519; GFX11-NEXT: v_readfirstlane_b32 s0, v04520; GFX11-NEXT: ; return to shader part epilog4521 %sign.trunc = fptrunc <2 x double> %sign to <2 x half>4522 %out = call <2 x half> @llvm.copysign.v2f16(<2 x half> %mag, <2 x half> %sign.trunc)4523 %cast = bitcast <2 x half> %out to i324524 ret i32 %cast4525}4526 4527define <3 x float> @v_copysign_out_v3f32_mag_v3f16_sign_v3f32(<3 x half> %mag, <3 x float> %sign) {4528; SI-LABEL: v_copysign_out_v3f32_mag_v3f16_sign_v3f32:4529; SI: ; %bb.0:4530; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4531; SI-NEXT: v_cvt_f16_f32_e32 v0, v04532; SI-NEXT: v_cvt_f16_f32_e32 v1, v14533; SI-NEXT: v_cvt_f16_f32_e32 v2, v24534; SI-NEXT: s_brev_b32 s4, -24535; SI-NEXT: v_cvt_f32_f16_e32 v0, v04536; SI-NEXT: v_cvt_f32_f16_e32 v1, v14537; SI-NEXT: v_cvt_f32_f16_e32 v2, v24538; SI-NEXT: v_bfi_b32 v0, s4, v0, v34539; SI-NEXT: v_bfi_b32 v1, s4, v1, v44540; SI-NEXT: v_bfi_b32 v2, s4, v2, v54541; SI-NEXT: s_setpc_b64 s[30:31]4542;4543; VI-LABEL: v_copysign_out_v3f32_mag_v3f16_sign_v3f32:4544; VI: ; %bb.0:4545; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4546; VI-NEXT: v_cvt_f32_f16_e32 v5, v04547; VI-NEXT: v_cvt_f32_f16_e32 v1, v14548; VI-NEXT: v_cvt_f32_f16_sdwa v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_14549; VI-NEXT: s_brev_b32 s4, -24550; VI-NEXT: v_bfi_b32 v0, s4, v5, v24551; VI-NEXT: v_bfi_b32 v2, s4, v1, v44552; VI-NEXT: v_bfi_b32 v1, s4, v6, v34553; VI-NEXT: s_setpc_b64 s[30:31]4554;4555; GFX9-LABEL: v_copysign_out_v3f32_mag_v3f16_sign_v3f32:4556; GFX9: ; %bb.0:4557; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4558; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v04559; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v14560; GFX9-NEXT: v_cvt_f32_f16_sdwa v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_14561; GFX9-NEXT: s_brev_b32 s4, -24562; GFX9-NEXT: v_bfi_b32 v0, s4, v5, v24563; GFX9-NEXT: v_bfi_b32 v2, s4, v1, v44564; GFX9-NEXT: v_bfi_b32 v1, s4, v6, v34565; GFX9-NEXT: s_setpc_b64 s[30:31]4566;4567; GFX11-TRUE16-LABEL: v_copysign_out_v3f32_mag_v3f16_sign_v3f32:4568; GFX11-TRUE16: ; %bb.0:4569; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4570; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.l4571; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.h4572; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l4573; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4574; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v5, v24575; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v6, v34576; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)4577; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v7, v44578; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]4579;4580; GFX11-FAKE16-LABEL: v_copysign_out_v3f32_mag_v3f16_sign_v3f32:4581; GFX11-FAKE16: ; %bb.0:4582; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4583; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v04584; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v04585; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v14586; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4587; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v5, v54588; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v24589; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4590; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v6, v44591; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v34592; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]4593 %mag.ext = fpext <3 x half> %mag to <3 x float>4594 %out = call <3 x float> @llvm.copysign.v3f32(<3 x float> %mag.ext, <3 x float> %sign)4595 ret <3 x float> %out4596}4597 4598define <3 x float> @v_copysign_out_v3f32_mag_v3f32_sign_v3f16(<3 x float> %mag, <3 x half> %sign) {4599; SI-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3f16:4600; SI: ; %bb.0:4601; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4602; SI-NEXT: v_cvt_f16_f32_e32 v3, v34603; SI-NEXT: v_cvt_f16_f32_e32 v4, v44604; SI-NEXT: v_cvt_f16_f32_e32 v5, v54605; SI-NEXT: s_brev_b32 s4, -24606; SI-NEXT: v_cvt_f32_f16_e32 v3, v34607; SI-NEXT: v_cvt_f32_f16_e32 v4, v44608; SI-NEXT: v_cvt_f32_f16_e32 v5, v54609; SI-NEXT: v_bfi_b32 v0, s4, v0, v34610; SI-NEXT: v_bfi_b32 v1, s4, v1, v44611; SI-NEXT: v_bfi_b32 v2, s4, v2, v54612; SI-NEXT: s_setpc_b64 s[30:31]4613;4614; VI-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3f16:4615; VI: ; %bb.0:4616; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4617; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v34618; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v34619; VI-NEXT: s_brev_b32 s4, -24620; VI-NEXT: v_bfi_b32 v0, s4, v0, v34621; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v44622; VI-NEXT: v_bfi_b32 v2, s4, v2, v34623; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v54624; VI-NEXT: v_bfi_b32 v1, s4, v1, v34625; VI-NEXT: s_setpc_b64 s[30:31]4626;4627; GFX9-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3f16:4628; GFX9: ; %bb.0:4629; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4630; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v34631; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v34632; GFX9-NEXT: s_brev_b32 s4, -24633; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v34634; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v44635; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v34636; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v54637; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v34638; GFX9-NEXT: s_setpc_b64 s[30:31]4639;4640; GFX11-TRUE16-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3f16:4641; GFX11-TRUE16: ; %bb.0:4642; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4643; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v3.l4644; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l4645; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v34646; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4647; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v44648; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v54649; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]4650;4651; GFX11-FAKE16-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3f16:4652; GFX11-FAKE16: ; %bb.0:4653; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4654; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v34655; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v34656; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v44657; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4658; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v54659; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v34660; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4661; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v44662; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v54663; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]4664 %sign.ext = fpext <3 x half> %sign to <3 x float>4665 %out = call <3 x float> @llvm.copysign.v3f32(<3 x float> %mag, <3 x float> %sign.ext)4666 ret <3 x float> %out4667}4668 4669define <3 x double> @v_copysign_out_v3f64_mag_v3f64_sign_v3f16(<3 x double> %mag, <3 x half> %sign) {4670; SI-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3f16:4671; SI: ; %bb.0:4672; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4673; SI-NEXT: s_brev_b32 s4, -24674; SI-NEXT: v_bfi_b32 v1, s4, v1, v64675; SI-NEXT: v_bfi_b32 v3, s4, v3, v74676; SI-NEXT: v_bfi_b32 v5, s4, v5, v84677; SI-NEXT: s_setpc_b64 s[30:31]4678;4679; VI-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3f16:4680; VI: ; %bb.0:4681; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4682; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v64683; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v64684; VI-NEXT: s_brev_b32 s4, -24685; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v74686; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v64687; VI-NEXT: v_bfi_b32 v1, s4, v1, v84688; VI-NEXT: v_bfi_b32 v5, s4, v5, v74689; VI-NEXT: v_bfi_b32 v3, s4, v3, v64690; VI-NEXT: s_setpc_b64 s[30:31]4691;4692; GFX9-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3f16:4693; GFX9: ; %bb.0:4694; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4695; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v64696; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v64697; GFX9-NEXT: s_brev_b32 s4, -24698; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v74699; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v64700; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v84701; GFX9-NEXT: v_bfi_b32 v5, s4, v5, v74702; GFX9-NEXT: v_bfi_b32 v3, s4, v3, v64703; GFX9-NEXT: s_setpc_b64 s[30:31]4704;4705; GFX11-TRUE16-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3f16:4706; GFX11-TRUE16: ; %bb.0:4707; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4708; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l4709; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l4710; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v64711; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4712; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v74713; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v84714; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]4715;4716; GFX11-FAKE16-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3f16:4717; GFX11-FAKE16: ; %bb.0:4718; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4719; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v64720; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v64721; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v74722; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4723; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v84724; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v64725; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)4726; GFX11-FAKE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v74727; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v84728; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]4729 %sign.ext = fpext <3 x half> %sign to <3 x double>4730 %out = call <3 x double> @llvm.copysign.v3f64(<3 x double> %mag, <3 x double> %sign.ext)4731 ret <3 x double> %out4732}4733 4734define <3 x half> @v_copysign_out_v3f16_mag_v3f32_sign_v3f16(<3 x float> %mag, <3 x half> %sign) {4735; SI-LABEL: v_copysign_out_v3f16_mag_v3f32_sign_v3f16:4736; SI: ; %bb.0:4737; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4738; SI-NEXT: v_cvt_f16_f32_e32 v5, v54739; SI-NEXT: v_cvt_f16_f32_e32 v4, v44740; SI-NEXT: v_cvt_f16_f32_e32 v3, v34741; SI-NEXT: v_cvt_f16_f32_e32 v0, v04742; SI-NEXT: v_cvt_f16_f32_e32 v1, v14743; SI-NEXT: v_cvt_f16_f32_e32 v2, v24744; SI-NEXT: v_cvt_f32_f16_e32 v5, v54745; SI-NEXT: v_cvt_f32_f16_e32 v4, v44746; SI-NEXT: v_cvt_f32_f16_e32 v3, v34747; SI-NEXT: v_cvt_f32_f16_e32 v0, v04748; SI-NEXT: v_cvt_f32_f16_e32 v1, v14749; SI-NEXT: v_cvt_f32_f16_e32 v2, v24750; SI-NEXT: s_brev_b32 s4, -24751; SI-NEXT: v_bfi_b32 v0, s4, v0, v34752; SI-NEXT: v_bfi_b32 v1, s4, v1, v44753; SI-NEXT: v_bfi_b32 v2, s4, v2, v54754; SI-NEXT: s_setpc_b64 s[30:31]4755;4756; VI-LABEL: v_copysign_out_v3f16_mag_v3f32_sign_v3f16:4757; VI: ; %bb.0:4758; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4759; VI-NEXT: v_cvt_f16_f32_e32 v0, v04760; VI-NEXT: v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD4761; VI-NEXT: v_cvt_f16_f32_e32 v2, v24762; VI-NEXT: s_mov_b32 s4, 0x7fff7fff4763; VI-NEXT: v_or_b32_e32 v0, v0, v54764; VI-NEXT: v_bfi_b32 v1, s4, v2, v44765; VI-NEXT: v_bfi_b32 v0, s4, v0, v34766; VI-NEXT: s_setpc_b64 s[30:31]4767;4768; GFX9-LABEL: v_copysign_out_v3f16_mag_v3f32_sign_v3f16:4769; GFX9: ; %bb.0:4770; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4771; GFX9-NEXT: v_cvt_f16_f32_e32 v5, v14772; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v04773; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v24774; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff4775; GFX9-NEXT: v_pack_b32_f16 v0, v0, v54776; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v44777; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v34778; GFX9-NEXT: s_setpc_b64 s[30:31]4779;4780; GFX11-TRUE16-LABEL: v_copysign_out_v3f16_mag_v3f32_sign_v3f16:4781; GFX11-TRUE16: ; %bb.0:4782; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4783; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v14784; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v04785; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4786; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v1.l4787; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v24788; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v34789; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)4790; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v44791; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]4792;4793; GFX11-FAKE16-LABEL: v_copysign_out_v3f16_mag_v3f32_sign_v3f16:4794; GFX11-FAKE16: ; %bb.0:4795; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4796; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v14797; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v04798; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4799; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v14800; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v24801; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v34802; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)4803; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v44804; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]4805 %mag.trunc = fptrunc <3 x float> %mag to <3 x half>4806 %out = call <3 x half> @llvm.copysign.v3f16(<3 x half> %mag.trunc, <3 x half> %sign)4807 ret <3 x half> %out4808}4809 4810define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag, <3 x half> %sign) {4811; SI-LABEL: v_copysign_out_v3f16_mag_v3f64_sign_v3f16:4812; SI: ; %bb.0:4813; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4814; SI-NEXT: v_cvt_f16_f32_e32 v8, v84815; SI-NEXT: v_cvt_f16_f32_e32 v9, v64816; SI-NEXT: v_and_b32_e32 v10, 0x1ff, v54817; SI-NEXT: v_or_b32_e32 v4, v10, v44818; SI-NEXT: v_cvt_f32_f16_e32 v6, v84819; SI-NEXT: v_cvt_f32_f16_e32 v8, v94820; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v54821; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44822; SI-NEXT: v_and_b32_e32 v9, 0xffe, v94823; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc4824; SI-NEXT: v_bfe_u32 v10, v5, 20, 114825; SI-NEXT: s_movk_i32 s4, 0x3f14826; SI-NEXT: v_or_b32_e32 v4, v9, v44827; SI-NEXT: v_sub_i32_e32 v11, vcc, s4, v104828; SI-NEXT: v_or_b32_e32 v9, 0x1000, v44829; SI-NEXT: v_med3_i32 v11, v11, 0, 134830; SI-NEXT: v_lshrrev_b32_e32 v12, v11, v94831; SI-NEXT: v_lshlrev_b32_e32 v11, v11, v124832; SI-NEXT: v_cmp_ne_u32_e32 vcc, v11, v94833; SI-NEXT: s_movk_i32 s5, 0xfc104834; SI-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc4835; SI-NEXT: v_add_i32_e32 v10, vcc, s5, v104836; SI-NEXT: v_lshlrev_b32_e32 v11, 12, v104837; SI-NEXT: v_or_b32_e32 v9, v12, v94838; SI-NEXT: v_or_b32_e32 v11, v4, v114839; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v104840; SI-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4841; SI-NEXT: v_and_b32_e32 v11, 7, v94842; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v114843; SI-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc4844; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v114845; SI-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc4846; SI-NEXT: v_or_b32_e32 v11, v11, v124847; SI-NEXT: v_lshrrev_b32_e32 v9, 2, v94848; SI-NEXT: v_add_i32_e32 v9, vcc, v9, v114849; SI-NEXT: v_mov_b32_e32 v11, 0x7c004850; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v104851; SI-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4852; SI-NEXT: v_mov_b32_e32 v12, 0x7e004853; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44854; SI-NEXT: s_movk_i32 s6, 0x40f4855; SI-NEXT: v_cndmask_b32_e32 v4, v11, v12, vcc4856; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v104857; SI-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc4858; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v54859; SI-NEXT: v_and_b32_e32 v9, 0x1ff, v34860; SI-NEXT: v_and_b32_e32 v5, 0x8000, v54861; SI-NEXT: v_or_b32_e32 v2, v9, v24862; SI-NEXT: v_or_b32_e32 v4, v5, v44863; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v34864; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24865; SI-NEXT: v_and_b32_e32 v5, 0xffe, v54866; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc4867; SI-NEXT: v_bfe_u32 v9, v3, 20, 114868; SI-NEXT: v_or_b32_e32 v2, v5, v24869; SI-NEXT: v_sub_i32_e32 v10, vcc, s4, v94870; SI-NEXT: v_or_b32_e32 v5, 0x1000, v24871; SI-NEXT: v_med3_i32 v10, v10, 0, 134872; SI-NEXT: v_lshrrev_b32_e32 v13, v10, v54873; SI-NEXT: v_lshlrev_b32_e32 v10, v10, v134874; SI-NEXT: v_cmp_ne_u32_e32 vcc, v10, v54875; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc4876; SI-NEXT: v_add_i32_e32 v9, vcc, s5, v94877; SI-NEXT: v_lshlrev_b32_e32 v10, 12, v94878; SI-NEXT: v_or_b32_e32 v5, v13, v54879; SI-NEXT: v_or_b32_e32 v10, v2, v104880; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v94881; SI-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc4882; SI-NEXT: v_and_b32_e32 v10, 7, v54883; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v104884; SI-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc4885; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v104886; SI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc4887; SI-NEXT: v_or_b32_e32 v10, v10, v134888; SI-NEXT: v_lshrrev_b32_e32 v5, 2, v54889; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v104890; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v94891; SI-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc4892; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24893; SI-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc4894; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v94895; SI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc4896; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34897; SI-NEXT: v_and_b32_e32 v5, 0x1ff, v14898; SI-NEXT: v_and_b32_e32 v3, 0x8000, v34899; SI-NEXT: v_or_b32_e32 v0, v5, v04900; SI-NEXT: v_or_b32_e32 v2, v3, v24901; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v14902; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04903; SI-NEXT: v_and_b32_e32 v3, 0xffe, v34904; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc4905; SI-NEXT: v_bfe_u32 v5, v1, 20, 114906; SI-NEXT: v_or_b32_e32 v0, v3, v04907; SI-NEXT: v_sub_i32_e32 v9, vcc, s4, v54908; SI-NEXT: v_or_b32_e32 v3, 0x1000, v04909; SI-NEXT: v_med3_i32 v9, v9, 0, 134910; SI-NEXT: v_lshrrev_b32_e32 v10, v9, v34911; SI-NEXT: v_lshlrev_b32_e32 v9, v9, v104912; SI-NEXT: v_cmp_ne_u32_e32 vcc, v9, v34913; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc4914; SI-NEXT: v_add_i32_e32 v5, vcc, s5, v54915; SI-NEXT: v_lshlrev_b32_e32 v9, 12, v54916; SI-NEXT: v_or_b32_e32 v3, v10, v34917; SI-NEXT: v_or_b32_e32 v9, v0, v94918; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v54919; SI-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc4920; SI-NEXT: v_and_b32_e32 v9, 7, v34921; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v94922; SI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc4923; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v94924; SI-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc4925; SI-NEXT: v_or_b32_e32 v9, v9, v104926; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v34927; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v94928; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v54929; SI-NEXT: v_cvt_f16_f32_e32 v7, v74930; SI-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc4931; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04932; SI-NEXT: v_cndmask_b32_e32 v0, v11, v12, vcc4933; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v54934; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v14935; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc4936; SI-NEXT: v_and_b32_e32 v1, 0x8000, v14937; SI-NEXT: v_or_b32_e32 v0, v1, v04938; SI-NEXT: v_cvt_f32_f16_e32 v7, v74939; SI-NEXT: v_cvt_f32_f16_e32 v0, v04940; SI-NEXT: v_cvt_f32_f16_e32 v1, v24941; SI-NEXT: v_cvt_f32_f16_e32 v2, v44942; SI-NEXT: s_brev_b32 s4, -24943; SI-NEXT: v_bfi_b32 v0, s4, v0, v84944; SI-NEXT: v_bfi_b32 v1, s4, v1, v74945; SI-NEXT: v_bfi_b32 v2, s4, v2, v64946; SI-NEXT: s_setpc_b64 s[30:31]4947;4948; VI-LABEL: v_copysign_out_v3f16_mag_v3f64_sign_v3f16:4949; VI: ; %bb.0:4950; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4951; VI-NEXT: v_and_b32_e32 v9, 0x1ff, v54952; VI-NEXT: v_or_b32_e32 v4, v9, v44953; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v54954; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44955; VI-NEXT: v_and_b32_e32 v8, 0xffe, v84956; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc4957; VI-NEXT: v_bfe_u32 v5, v5, 20, 114958; VI-NEXT: s_movk_i32 s4, 0x3f14959; VI-NEXT: v_or_b32_e32 v4, v8, v44960; VI-NEXT: v_sub_u32_e32 v9, vcc, s4, v54961; VI-NEXT: v_or_b32_e32 v8, 0x1000, v44962; VI-NEXT: v_med3_i32 v9, v9, 0, 134963; VI-NEXT: v_lshrrev_b32_e32 v10, v9, v84964; VI-NEXT: v_lshlrev_b32_e32 v9, v9, v104965; VI-NEXT: v_cmp_ne_u32_e32 vcc, v9, v84966; VI-NEXT: s_movk_i32 s5, 0xfc104967; VI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc4968; VI-NEXT: v_add_u32_e32 v5, vcc, s5, v54969; VI-NEXT: v_lshlrev_b32_e32 v9, 12, v54970; VI-NEXT: v_or_b32_e32 v8, v10, v84971; VI-NEXT: v_or_b32_e32 v9, v4, v94972; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v54973; VI-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc4974; VI-NEXT: v_and_b32_e32 v9, 7, v84975; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v94976; VI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc4977; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v94978; VI-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc4979; VI-NEXT: v_or_b32_e32 v9, v9, v104980; VI-NEXT: v_lshrrev_b32_e32 v8, 2, v84981; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v94982; VI-NEXT: v_mov_b32_e32 v9, 0x7c004983; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v54984; VI-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc4985; VI-NEXT: v_mov_b32_e32 v10, 0x7e004986; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44987; VI-NEXT: s_movk_i32 s6, 0x40f4988; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc4989; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v54990; VI-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc4991; VI-NEXT: v_and_b32_e32 v8, 0x1ff, v14992; VI-NEXT: v_or_b32_e32 v0, v8, v04993; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v14994; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v04995; VI-NEXT: v_and_b32_e32 v5, 0xffe, v54996; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc4997; VI-NEXT: v_bfe_u32 v1, v1, 20, 114998; VI-NEXT: v_or_b32_e32 v0, v5, v04999; VI-NEXT: v_sub_u32_e32 v8, vcc, s4, v15000; VI-NEXT: v_or_b32_e32 v5, 0x1000, v05001; VI-NEXT: v_med3_i32 v8, v8, 0, 135002; VI-NEXT: v_lshrrev_b32_e32 v11, v8, v55003; VI-NEXT: v_lshlrev_b32_e32 v8, v8, v115004; VI-NEXT: v_cmp_ne_u32_e32 vcc, v8, v55005; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5006; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v15007; VI-NEXT: v_lshlrev_b32_e32 v8, 12, v15008; VI-NEXT: v_or_b32_e32 v5, v11, v55009; VI-NEXT: v_or_b32_e32 v8, v0, v85010; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v15011; VI-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc5012; VI-NEXT: v_and_b32_e32 v8, 7, v55013; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v85014; VI-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc5015; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v85016; VI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc5017; VI-NEXT: v_or_b32_e32 v8, v8, v115018; VI-NEXT: v_lshrrev_b32_e32 v5, 2, v55019; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v85020; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v15021; VI-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc5022; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05023; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc5024; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v15025; VI-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc5026; VI-NEXT: v_and_b32_e32 v5, 0x1ff, v35027; VI-NEXT: v_or_b32_e32 v2, v5, v25028; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v35029; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25030; VI-NEXT: v_and_b32_e32 v1, 0xffe, v15031; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc5032; VI-NEXT: v_bfe_u32 v3, v3, 20, 115033; VI-NEXT: v_or_b32_e32 v1, v1, v25034; VI-NEXT: v_sub_u32_e32 v5, vcc, s4, v35035; VI-NEXT: v_or_b32_e32 v2, 0x1000, v15036; VI-NEXT: v_med3_i32 v5, v5, 0, 135037; VI-NEXT: v_lshrrev_b32_e32 v8, v5, v25038; VI-NEXT: v_lshlrev_b32_e32 v5, v5, v85039; VI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v25040; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc5041; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v35042; VI-NEXT: v_lshlrev_b32_e32 v5, 12, v35043; VI-NEXT: v_or_b32_e32 v2, v8, v25044; VI-NEXT: v_or_b32_e32 v5, v1, v55045; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v35046; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc5047; VI-NEXT: v_and_b32_e32 v5, 7, v25048; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v55049; VI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc5050; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v55051; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5052; VI-NEXT: v_or_b32_e32 v5, v5, v85053; VI-NEXT: v_lshrrev_b32_e32 v2, 2, v25054; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v55055; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v35056; VI-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc5057; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15058; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc5059; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v35060; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5061; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v15062; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v05063; VI-NEXT: v_or_b32_e32 v0, v0, v15064; VI-NEXT: s_mov_b32 s4, 0x7fff7fff5065; VI-NEXT: v_bfi_b32 v0, s4, v0, v65066; VI-NEXT: v_bfi_b32 v1, s4, v4, v75067; VI-NEXT: s_setpc_b64 s[30:31]5068;5069; GFX9-LABEL: v_copysign_out_v3f16_mag_v3f64_sign_v3f16:5070; GFX9: ; %bb.0:5071; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5072; GFX9-NEXT: s_movk_i32 s4, 0x1ff5073; GFX9-NEXT: v_and_or_b32 v4, v5, s4, v45074; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v45075; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc5076; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v55077; GFX9-NEXT: s_movk_i32 s5, 0xffe5078; GFX9-NEXT: v_bfe_u32 v5, v5, 20, 115079; GFX9-NEXT: v_and_or_b32 v4, v8, s5, v45080; GFX9-NEXT: v_sub_u32_e32 v9, 0x3f1, v55081; GFX9-NEXT: v_or_b32_e32 v8, 0x1000, v45082; GFX9-NEXT: v_med3_i32 v9, v9, 0, 135083; GFX9-NEXT: v_lshrrev_b32_e32 v10, v9, v85084; GFX9-NEXT: v_lshlrev_b32_e32 v9, v9, v105085; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v9, v85086; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc5087; GFX9-NEXT: v_add_u32_e32 v5, 0xfffffc10, v55088; GFX9-NEXT: v_or_b32_e32 v8, v10, v85089; GFX9-NEXT: v_lshl_or_b32 v9, v5, 12, v45090; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v55091; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc5092; GFX9-NEXT: v_and_b32_e32 v9, 7, v85093; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v95094; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc5095; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v95096; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc5097; GFX9-NEXT: v_or_b32_e32 v9, v9, v105098; GFX9-NEXT: v_lshrrev_b32_e32 v8, 2, v85099; GFX9-NEXT: v_add_u32_e32 v8, v8, v95100; GFX9-NEXT: v_mov_b32_e32 v9, 0x7c005101; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v55102; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc5103; GFX9-NEXT: v_mov_b32_e32 v10, 0x7e005104; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v45105; GFX9-NEXT: s_movk_i32 s6, 0x40f5106; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc5107; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v55108; GFX9-NEXT: v_and_or_b32 v0, v1, s4, v05109; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc5110; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05111; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5112; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v15113; GFX9-NEXT: v_bfe_u32 v8, v1, 20, 115114; GFX9-NEXT: v_and_or_b32 v0, v5, s5, v05115; GFX9-NEXT: v_sub_u32_e32 v11, 0x3f1, v85116; GFX9-NEXT: v_or_b32_e32 v5, 0x1000, v05117; GFX9-NEXT: v_med3_i32 v11, v11, 0, 135118; GFX9-NEXT: v_lshrrev_b32_e32 v12, v11, v55119; GFX9-NEXT: v_lshlrev_b32_e32 v11, v11, v125120; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v11, v55121; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5122; GFX9-NEXT: v_add_u32_e32 v8, 0xfffffc10, v85123; GFX9-NEXT: v_or_b32_e32 v5, v12, v55124; GFX9-NEXT: v_lshl_or_b32 v11, v8, 12, v05125; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v85126; GFX9-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc5127; GFX9-NEXT: v_and_b32_e32 v11, 7, v55128; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v115129; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc5130; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v115131; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc5132; GFX9-NEXT: v_or_b32_e32 v11, v11, v125133; GFX9-NEXT: v_lshrrev_b32_e32 v5, 2, v55134; GFX9-NEXT: v_add_u32_e32 v5, v5, v115135; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v85136; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc5137; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05138; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc5139; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v85140; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc5141; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v15142; GFX9-NEXT: s_mov_b32 s7, 0x80005143; GFX9-NEXT: v_and_or_b32 v0, v1, s7, v05144; GFX9-NEXT: v_and_or_b32 v1, v3, s4, v25145; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15146; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5147; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v35148; GFX9-NEXT: v_bfe_u32 v5, v3, 20, 115149; GFX9-NEXT: v_and_or_b32 v1, v2, s5, v15150; GFX9-NEXT: v_sub_u32_e32 v8, 0x3f1, v55151; GFX9-NEXT: v_or_b32_e32 v2, 0x1000, v15152; GFX9-NEXT: v_med3_i32 v8, v8, 0, 135153; GFX9-NEXT: v_lshrrev_b32_e32 v11, v8, v25154; GFX9-NEXT: v_lshlrev_b32_e32 v8, v8, v115155; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v8, v25156; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc5157; GFX9-NEXT: v_add_u32_e32 v5, 0xfffffc10, v55158; GFX9-NEXT: v_or_b32_e32 v2, v11, v25159; GFX9-NEXT: v_lshl_or_b32 v8, v5, 12, v15160; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v55161; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc5162; GFX9-NEXT: v_and_b32_e32 v8, 7, v25163; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v85164; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc5165; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v85166; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc5167; GFX9-NEXT: v_or_b32_e32 v8, v8, v115168; GFX9-NEXT: v_lshrrev_b32_e32 v2, 2, v25169; GFX9-NEXT: v_add_u32_e32 v2, v2, v85170; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v55171; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc5172; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15173; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc5174; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v55175; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5176; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v35177; GFX9-NEXT: v_and_or_b32 v1, v2, s7, v15178; GFX9-NEXT: s_mov_b32 s4, 0x50401005179; GFX9-NEXT: v_perm_b32 v0, v1, v0, s45180; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff5181; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v65182; GFX9-NEXT: v_bfi_b32 v1, s4, v4, v75183; GFX9-NEXT: s_setpc_b64 s[30:31]5184;5185; GFX11-TRUE16-LABEL: v_copysign_out_v3f16_mag_v3f64_sign_v3f16:5186; GFX11-TRUE16: ; %bb.0:5187; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5188; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0x1ff, v5, v45189; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v25190; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v55191; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v35192; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v3, 20, 115193; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v45194; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v5, 20, 115195; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v05196; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v15197; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v1, 20, 115198; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo5199; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v25200; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v11, 0x3f1, v55201; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)5202; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0xffe, v8, v45203; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo5204; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v8, 0x3f1, v105205; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05206; GFX11-TRUE16-NEXT: v_med3_i32 v11, v11, 0, 135207; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v105208; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v9, v25209; GFX11-TRUE16-NEXT: v_med3_i32 v8, v8, 0, 135210; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x1000, v45211; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5212; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)5213; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x1000, v25214; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, v11, v95215; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)5216; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v13, v05217; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v13, 0x3f1, v145218; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, v8, v125219; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0xfffffc10, v145220; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, v11, v165221; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x1000, v05222; GFX11-TRUE16-NEXT: v_med3_i32 v13, v13, 0, 135223; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, v8, v155224; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)5225; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v8, v125226; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, v13, v175227; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo5228; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v95229; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v10, 12, v25230; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5231; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, v13, v125232; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v85233; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo5234; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v105235; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0xfffffc10, v55236; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)5237; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v16, v95238; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo5239; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v13, v175240; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v5, 12, v45241; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, 0x7e005242; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)5243; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 7, v85244; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo5245; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v55246; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 2, v85247; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo5248; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v155249; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v12, v135250; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 12, v05251; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo5252; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v155253; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo5254; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v145255; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)5256; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v135257; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v12, v11 :: v_dual_and_b32 v12, 7, v95258; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 2, v95259; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v135260; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)5261; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 7, v115262; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v125263; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v115264; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo5265; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)5266; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v155267; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo5268; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v155269; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo5270; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v125271; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v135272; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo5273; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v105274; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5275; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v135276; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v12, v165277; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, 0x7c00, v8, vcc_lo5278; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v25279; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)5280; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, 0x7c00, v17 :: v_dual_add_nc_u32 v9, v9, v125281; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v105282; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo5283; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v145284; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.h5285; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, 05286; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v11, vcc_lo5287; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05288; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)5289; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x8000, v8, v25290; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.h5291; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v17, vcc_lo5292; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v145293; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo5294; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v55295; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)5296; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x8000, v8, v05297; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, 0x7c00, v9, vcc_lo5298; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v45299; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l5300; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v17, vcc_lo5301; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v55302; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5303; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v65304; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo5305; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)5306; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v75307; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5308;5309; GFX11-FAKE16-LABEL: v_copysign_out_v3f16_mag_v3f64_sign_v3f16:5310; GFX11-FAKE16: ; %bb.0:5311; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5312; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0x1ff, v5, v45313; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v05314; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 20, 115315; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v55316; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v25317; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v45318; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v1, 20, 115319; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v9, 0x3f1, v85320; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 8, v35321; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v3, 20, 115322; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo5323; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05324; GFX11-FAKE16-NEXT: v_med3_i32 v9, v9, 0, 135325; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v35326; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)5327; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0xffe, v5, v45328; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5329; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v15330; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v25331; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v15332; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x1000, v45333; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)5334; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v5, v05335; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v5, 0x3f1, v105336; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo5337; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, v9, v115338; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5339; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x1000, v05340; GFX11-FAKE16-NEXT: v_med3_i32 v5, v5, 0, 135341; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)5342; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffe, v12, v25343; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v12, 0x3f1, v135344; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, v9, v155345; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0xfffffc10, v135346; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, v5, v145347; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x1000, v25348; GFX11-FAKE16-NEXT: v_med3_i32 v12, v12, 0, 135349; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v9, v115350; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)5351; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v5, v165352; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, v12, v175353; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo5354; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5355; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v5, v145356; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, v12, v115357; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)5358; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v15, v95359; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0xfffffc10, v85360; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo5361; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v12, v175362; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5363; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v8, 12, v45364; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v16, v55365; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v105366; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo5367; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v85368; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5369; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v10, 12, v05370; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v125371; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc_lo5372; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v105373; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 12, v25374; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo5375; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v135376; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 7, v95377; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 2, v95378; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo5379; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)5380; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v145381; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo5382; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v145383; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo5384; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v125385; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)5386; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, 0x7e00 :: v_dual_add_nc_u32 v9, v9, v125387; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 7, v55388; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 7, v115389; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 2, v55390; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 2, v115391; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v155392; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo5393; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v155394; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo5395; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v165396; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)5397; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v175398; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo5399; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v165400; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v145401; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo5402; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v105403; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)5404; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v185405; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v5, vcc_lo5406; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05407; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)5408; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, 0x7c00, v12 :: v_dual_add_nc_u32 v11, v11, v155409; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v135410; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, 0x7c00, v11, vcc_lo5411; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v25412; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v12, vcc_lo5413; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v105414; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo5415; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v135416; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)5417; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x8000, v1, v05418; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo5419; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v85420; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0x8000, v3, v25421; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v9, vcc_lo5422; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v45423; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)5424; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401005425; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v12, vcc_lo5426; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v85427; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v65428; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)5429; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo5430; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v75431; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5432 %mag.trunc = fptrunc <3 x double> %mag to <3 x half>5433 %result = call <3 x half> @llvm.copysign.v3f16(<3 x half> %mag.trunc, <3 x half> %sign)5434 ret <3 x half> %result5435}5436 5437define <3 x half> @v_copysign_out_v3f16_mag_v3f16_sign_v3f32(<3 x half> %mag, <3 x float> %sign) {5438; SI-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f32:5439; SI: ; %bb.0:5440; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5441; SI-NEXT: v_cvt_f16_f32_e32 v2, v25442; SI-NEXT: v_cvt_f16_f32_e32 v1, v15443; SI-NEXT: v_cvt_f16_f32_e32 v0, v05444; SI-NEXT: v_cvt_f16_f32_e32 v3, v35445; SI-NEXT: v_cvt_f16_f32_e32 v4, v45446; SI-NEXT: v_cvt_f16_f32_e32 v5, v55447; SI-NEXT: v_cvt_f32_f16_e32 v2, v25448; SI-NEXT: v_cvt_f32_f16_e32 v1, v15449; SI-NEXT: v_cvt_f32_f16_e32 v0, v05450; SI-NEXT: v_cvt_f32_f16_e32 v3, v35451; SI-NEXT: v_cvt_f32_f16_e32 v4, v45452; SI-NEXT: v_cvt_f32_f16_e32 v5, v55453; SI-NEXT: s_brev_b32 s4, -25454; SI-NEXT: v_bfi_b32 v0, s4, v0, v35455; SI-NEXT: v_bfi_b32 v1, s4, v1, v45456; SI-NEXT: v_bfi_b32 v2, s4, v2, v55457; SI-NEXT: s_setpc_b64 s[30:31]5458;5459; VI-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f32:5460; VI: ; %bb.0:5461; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5462; VI-NEXT: v_cvt_f16_f32_e32 v2, v25463; VI-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD5464; VI-NEXT: v_cvt_f16_f32_e32 v4, v45465; VI-NEXT: s_mov_b32 s4, 0x7fff7fff5466; VI-NEXT: v_or_b32_e32 v2, v2, v35467; VI-NEXT: v_bfi_b32 v1, s4, v1, v45468; VI-NEXT: v_bfi_b32 v0, s4, v0, v25469; VI-NEXT: s_setpc_b64 s[30:31]5470;5471; GFX9-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f32:5472; GFX9: ; %bb.0:5473; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5474; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v35475; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v25476; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v45477; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff5478; GFX9-NEXT: v_pack_b32_f16 v2, v2, v35479; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v45480; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v25481; GFX9-NEXT: s_setpc_b64 s[30:31]5482;5483; GFX11-TRUE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f32:5484; GFX11-TRUE16: ; %bb.0:5485; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5486; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v35487; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v25488; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5489; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v2.l, v3.l5490; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v45491; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v25492; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)5493; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v35494; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5495;5496; GFX11-FAKE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f32:5497; GFX11-FAKE16: ; %bb.0:5498; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5499; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v35500; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v25501; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5502; GFX11-FAKE16-NEXT: v_pack_b32_f16 v2, v2, v35503; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v45504; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v25505; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)5506; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v35507; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5508 %sign.trunc = fptrunc <3 x float> %sign to <3 x half>5509 %out = call <3 x half> @llvm.copysign.v3f16(<3 x half> %mag, <3 x half> %sign.trunc)5510 ret <3 x half> %out5511}5512 5513define <3 x half> @v_copysign_out_v3f16_mag_v3f16_sign_v3f64(<3 x half> %mag, <3 x double> %sign) {5514; SI-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f64:5515; SI: ; %bb.0:5516; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5517; SI-NEXT: v_cvt_f16_f32_e32 v0, v05518; SI-NEXT: v_cvt_f16_f32_e32 v1, v15519; SI-NEXT: v_cvt_f16_f32_e32 v2, v25520; SI-NEXT: s_brev_b32 s4, -25521; SI-NEXT: v_cvt_f32_f16_e32 v0, v05522; SI-NEXT: v_cvt_f32_f16_e32 v1, v15523; SI-NEXT: v_cvt_f32_f16_e32 v2, v25524; SI-NEXT: v_bfi_b32 v0, s4, v0, v45525; SI-NEXT: v_bfi_b32 v1, s4, v1, v65526; SI-NEXT: v_bfi_b32 v2, s4, v2, v85527; SI-NEXT: s_setpc_b64 s[30:31]5528;5529; VI-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f64:5530; VI: ; %bb.0:5531; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5532; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v75533; VI-NEXT: s_movk_i32 s4, 0x7fff5534; VI-NEXT: v_bfi_b32 v1, s4, v1, v25535; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v35536; VI-NEXT: v_bfi_b32 v2, s4, v0, v25537; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v05538; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v55539; VI-NEXT: v_bfi_b32 v0, s4, v0, v35540; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v05541; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD5542; VI-NEXT: s_setpc_b64 s[30:31]5543;5544; GFX9-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f64:5545; GFX9: ; %bb.0:5546; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5547; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v75548; GFX9-NEXT: s_movk_i32 s4, 0x7fff5549; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v25550; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v35551; GFX9-NEXT: v_bfi_b32 v2, s4, v0, v25552; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v05553; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v55554; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v35555; GFX9-NEXT: s_mov_b32 s4, 0x50401005556; GFX9-NEXT: v_perm_b32 v0, v0, v2, s45557; GFX9-NEXT: s_setpc_b64 s[30:31]5558;5559; GFX11-TRUE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f64:5560; GFX11-TRUE16: ; %bb.0:5561; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5562; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h5563; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v55564; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v35565; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5566; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v45567; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v75568; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v35569; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5570; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l5571; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v45572; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5573;5574; GFX11-FAKE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f64:5575; GFX11-FAKE16: ; %bb.0:5576; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5577; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v35578; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v05579; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v55580; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)5581; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v25582; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v3, v45583; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v75584; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5585; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x50401005586; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v35587; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5588 %sign.trunc = fptrunc <3 x double> %sign to <3 x half>5589 %out = call <3 x half> @llvm.copysign.v3f16(<3 x half> %mag, <3 x half> %sign.trunc)5590 ret <3 x half> %out5591}5592 5593define <4 x float> @v_copysign_out_v4f32_mag_v4f16_sign_v4f32(<4 x half> %mag, <4 x float> %sign) {5594; SI-LABEL: v_copysign_out_v4f32_mag_v4f16_sign_v4f32:5595; SI: ; %bb.0:5596; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5597; SI-NEXT: v_cvt_f16_f32_e32 v3, v35598; SI-NEXT: v_cvt_f16_f32_e32 v0, v05599; SI-NEXT: v_cvt_f16_f32_e32 v1, v15600; SI-NEXT: v_cvt_f16_f32_e32 v2, v25601; SI-NEXT: v_cvt_f32_f16_e32 v3, v35602; SI-NEXT: v_cvt_f32_f16_e32 v0, v05603; SI-NEXT: v_cvt_f32_f16_e32 v1, v15604; SI-NEXT: v_cvt_f32_f16_e32 v2, v25605; SI-NEXT: s_brev_b32 s4, -25606; SI-NEXT: v_bfi_b32 v0, s4, v0, v45607; SI-NEXT: v_bfi_b32 v1, s4, v1, v55608; SI-NEXT: v_bfi_b32 v2, s4, v2, v65609; SI-NEXT: v_bfi_b32 v3, s4, v3, v75610; SI-NEXT: s_setpc_b64 s[30:31]5611;5612; VI-LABEL: v_copysign_out_v4f32_mag_v4f16_sign_v4f32:5613; VI: ; %bb.0:5614; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5615; VI-NEXT: v_cvt_f32_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15616; VI-NEXT: v_cvt_f32_f16_e32 v7, v05617; VI-NEXT: v_cvt_f32_f16_e32 v1, v15618; VI-NEXT: v_cvt_f32_f16_sdwa v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15619; VI-NEXT: s_brev_b32 s4, -25620; VI-NEXT: v_bfi_b32 v0, s4, v7, v25621; VI-NEXT: v_bfi_b32 v2, s4, v1, v45622; VI-NEXT: v_bfi_b32 v1, s4, v8, v35623; VI-NEXT: v_bfi_b32 v3, s4, v6, v55624; VI-NEXT: s_setpc_b64 s[30:31]5625;5626; GFX9-LABEL: v_copysign_out_v4f32_mag_v4f16_sign_v4f32:5627; GFX9: ; %bb.0:5628; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5629; GFX9-NEXT: v_cvt_f32_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15630; GFX9-NEXT: v_cvt_f32_f16_e32 v7, v05631; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v15632; GFX9-NEXT: v_cvt_f32_f16_sdwa v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15633; GFX9-NEXT: s_brev_b32 s4, -25634; GFX9-NEXT: v_bfi_b32 v0, s4, v7, v25635; GFX9-NEXT: v_bfi_b32 v2, s4, v1, v45636; GFX9-NEXT: v_bfi_b32 v1, s4, v8, v35637; GFX9-NEXT: v_bfi_b32 v3, s4, v6, v55638; GFX9-NEXT: s_setpc_b64 s[30:31]5639;5640; GFX11-TRUE16-LABEL: v_copysign_out_v4f32_mag_v4f16_sign_v4f32:5641; GFX11-TRUE16: ; %bb.0:5642; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5643; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.l5644; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v0.h5645; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v1.l5646; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v1.h5647; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5648; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v6, v25649; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v7, v35650; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5651; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v8, v45652; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v9, v55653; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5654;5655; GFX11-FAKE16-LABEL: v_copysign_out_v4f32_mag_v4f16_sign_v4f32:5656; GFX11-FAKE16: ; %bb.0:5657; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5658; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v05659; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15660; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v05661; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v15662; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5663; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v6, v65664; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v7, v75665; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5666; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v25667; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v1, v45668; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5669; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v6, v35670; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v7, v55671; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5672 %mag.ext = fpext <4 x half> %mag to <4 x float>5673 %out = call <4 x float> @llvm.copysign.v4f32(<4 x float> %mag.ext, <4 x float> %sign)5674 ret <4 x float> %out5675}5676 5677define <4 x float> @v_copysign_out_v4f32_mag_v4f32_sign_v4f16(<4 x float> %mag, <4 x half> %sign) {5678; SI-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4f16:5679; SI: ; %bb.0:5680; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5681; SI-NEXT: v_cvt_f16_f32_e32 v7, v75682; SI-NEXT: v_cvt_f16_f32_e32 v4, v45683; SI-NEXT: v_cvt_f16_f32_e32 v5, v55684; SI-NEXT: v_cvt_f16_f32_e32 v6, v65685; SI-NEXT: v_cvt_f32_f16_e32 v7, v75686; SI-NEXT: v_cvt_f32_f16_e32 v4, v45687; SI-NEXT: v_cvt_f32_f16_e32 v5, v55688; SI-NEXT: v_cvt_f32_f16_e32 v6, v65689; SI-NEXT: s_brev_b32 s4, -25690; SI-NEXT: v_bfi_b32 v0, s4, v0, v45691; SI-NEXT: v_bfi_b32 v1, s4, v1, v55692; SI-NEXT: v_bfi_b32 v2, s4, v2, v65693; SI-NEXT: v_bfi_b32 v3, s4, v3, v75694; SI-NEXT: s_setpc_b64 s[30:31]5695;5696; VI-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4f16:5697; VI: ; %bb.0:5698; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5699; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v45700; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v45701; VI-NEXT: s_brev_b32 s4, -25702; VI-NEXT: v_bfi_b32 v0, s4, v0, v45703; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v55704; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v55705; VI-NEXT: v_bfi_b32 v2, s4, v2, v45706; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v75707; VI-NEXT: v_bfi_b32 v1, s4, v1, v45708; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v65709; VI-NEXT: v_bfi_b32 v3, s4, v3, v45710; VI-NEXT: s_setpc_b64 s[30:31]5711;5712; GFX9-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4f16:5713; GFX9: ; %bb.0:5714; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5715; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v45716; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v45717; GFX9-NEXT: s_brev_b32 s4, -25718; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v45719; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v55720; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v55721; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v45722; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v75723; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v45724; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v65725; GFX9-NEXT: v_bfi_b32 v3, s4, v3, v45726; GFX9-NEXT: s_setpc_b64 s[30:31]5727;5728; GFX11-TRUE16-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4f16:5729; GFX11-TRUE16: ; %bb.0:5730; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5731; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l5732; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l5733; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v45734; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v55735; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5736; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v65737; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v75738; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5739;5740; GFX11-FAKE16-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4f16:5741; GFX11-FAKE16: ; %bb.0:5742; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5743; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v45744; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v55745; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v45746; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v55747; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5748; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v65749; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v75750; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5751; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v45752; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v55753; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5754; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v65755; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v75756; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5757 %sign.ext = fpext <4 x half> %sign to <4 x float>5758 %out = call <4 x float> @llvm.copysign.v4f32(<4 x float> %mag, <4 x float> %sign.ext)5759 ret <4 x float> %out5760}5761 5762define <4 x double> @v_copysign_out_v4f64_mag_v4f64_sign_v4f16(<4 x double> %mag, <4 x half> %sign) {5763; SI-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4f16:5764; SI: ; %bb.0:5765; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5766; SI-NEXT: s_brev_b32 s4, -25767; SI-NEXT: v_bfi_b32 v1, s4, v1, v85768; SI-NEXT: v_bfi_b32 v3, s4, v3, v95769; SI-NEXT: v_bfi_b32 v5, s4, v5, v105770; SI-NEXT: v_bfi_b32 v7, s4, v7, v115771; SI-NEXT: s_setpc_b64 s[30:31]5772;5773; VI-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4f16:5774; VI: ; %bb.0:5775; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5776; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v85777; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v85778; VI-NEXT: s_brev_b32 s4, -25779; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v85780; VI-NEXT: v_bfi_b32 v3, s4, v3, v85781; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v95782; VI-NEXT: v_bfi_b32 v1, s4, v1, v105783; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v95784; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v85785; VI-NEXT: v_bfi_b32 v5, s4, v5, v105786; VI-NEXT: v_bfi_b32 v7, s4, v7, v85787; VI-NEXT: s_setpc_b64 s[30:31]5788;5789; GFX9-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4f16:5790; GFX9: ; %bb.0:5791; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5792; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v85793; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v85794; GFX9-NEXT: s_brev_b32 s4, -25795; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v85796; GFX9-NEXT: v_bfi_b32 v3, s4, v3, v85797; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v95798; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v105799; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v95800; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v85801; GFX9-NEXT: v_bfi_b32 v5, s4, v5, v105802; GFX9-NEXT: v_bfi_b32 v7, s4, v7, v85803; GFX9-NEXT: s_setpc_b64 s[30:31]5804;5805; GFX11-TRUE16-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4f16:5806; GFX11-TRUE16: ; %bb.0:5807; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5808; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v8.l5809; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v9.l5810; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v85811; GFX11-TRUE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v95812; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5813; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v105814; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v115815; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5816;5817; GFX11-FAKE16-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4f16:5818; GFX11-FAKE16: ; %bb.0:5819; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5820; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v85821; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v95822; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v85823; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v95824; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5825; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v105826; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v115827; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5828; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v85829; GFX11-FAKE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v95830; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5831; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v105832; GFX11-FAKE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v115833; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5834 %sign.ext = fpext <4 x half> %sign to <4 x double>5835 %out = call <4 x double> @llvm.copysign.v4f64(<4 x double> %mag, <4 x double> %sign.ext)5836 ret <4 x double> %out5837}5838 5839define <4 x half> @v_copysign_out_v4f16_mag_v4f32_sign_v4f16(<4 x float> %mag, <4 x half> %sign) {5840; SI-LABEL: v_copysign_out_v4f16_mag_v4f32_sign_v4f16:5841; SI: ; %bb.0:5842; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5843; SI-NEXT: v_cvt_f16_f32_e32 v7, v75844; SI-NEXT: v_cvt_f16_f32_e32 v6, v65845; SI-NEXT: v_cvt_f16_f32_e32 v5, v55846; SI-NEXT: v_cvt_f16_f32_e32 v4, v45847; SI-NEXT: v_cvt_f16_f32_e32 v3, v35848; SI-NEXT: v_cvt_f16_f32_e32 v0, v05849; SI-NEXT: v_cvt_f16_f32_e32 v1, v15850; SI-NEXT: v_cvt_f16_f32_e32 v2, v25851; SI-NEXT: v_cvt_f32_f16_e32 v7, v75852; SI-NEXT: v_cvt_f32_f16_e32 v6, v65853; SI-NEXT: v_cvt_f32_f16_e32 v5, v55854; SI-NEXT: v_cvt_f32_f16_e32 v4, v45855; SI-NEXT: v_cvt_f32_f16_e32 v3, v35856; SI-NEXT: v_cvt_f32_f16_e32 v0, v05857; SI-NEXT: v_cvt_f32_f16_e32 v1, v15858; SI-NEXT: v_cvt_f32_f16_e32 v2, v25859; SI-NEXT: s_brev_b32 s4, -25860; SI-NEXT: v_bfi_b32 v0, s4, v0, v45861; SI-NEXT: v_bfi_b32 v1, s4, v1, v55862; SI-NEXT: v_bfi_b32 v2, s4, v2, v65863; SI-NEXT: v_bfi_b32 v3, s4, v3, v75864; SI-NEXT: s_setpc_b64 s[30:31]5865;5866; VI-LABEL: v_copysign_out_v4f16_mag_v4f32_sign_v4f16:5867; VI: ; %bb.0:5868; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5869; VI-NEXT: v_cvt_f16_f32_e32 v0, v05870; VI-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD5871; VI-NEXT: v_cvt_f16_f32_e32 v2, v25872; VI-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD5873; VI-NEXT: s_mov_b32 s4, 0x7fff7fff5874; VI-NEXT: v_or_b32_e32 v0, v0, v15875; VI-NEXT: v_bfi_b32 v0, s4, v0, v45876; VI-NEXT: v_or_b32_e32 v1, v2, v35877; VI-NEXT: v_bfi_b32 v1, s4, v1, v55878; VI-NEXT: s_setpc_b64 s[30:31]5879;5880; GFX9-LABEL: v_copysign_out_v4f16_mag_v4f32_sign_v4f16:5881; GFX9: ; %bb.0:5882; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5883; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v15884; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v05885; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v35886; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v25887; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff5888; GFX9-NEXT: v_pack_b32_f16 v0, v0, v15889; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v45890; GFX9-NEXT: v_pack_b32_f16 v1, v2, v35891; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v55892; GFX9-NEXT: s_setpc_b64 s[30:31]5893;5894; GFX11-TRUE16-LABEL: v_copysign_out_v4f16_mag_v4f32_sign_v4f16:5895; GFX11-TRUE16: ; %bb.0:5896; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5897; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v35898; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v15899; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v05900; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v25901; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5902; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v0.l, v1.l5903; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v0.h, v3.l5904; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5905; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v45906; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v2, v55907; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5908;5909; GFX11-FAKE16-LABEL: v_copysign_out_v4f16_mag_v4f32_sign_v4f16:5910; GFX11-FAKE16: ; %bb.0:5911; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5912; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v35913; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v15914; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v05915; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v25916; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5917; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v15918; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v2, v35919; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5920; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v45921; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v55922; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5923 %mag.trunc = fptrunc <4 x float> %mag to <4 x half>5924 %out = call <4 x half> @llvm.copysign.v4f16(<4 x half> %mag.trunc, <4 x half> %sign)5925 ret <4 x half> %out5926}5927 5928define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag, <4 x half> %sign) {5929; SI-LABEL: v_copysign_out_v4f16_mag_v4f64_sign_v4f16:5930; SI: ; %bb.0:5931; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5932; SI-NEXT: v_cvt_f16_f32_e32 v11, v115933; SI-NEXT: v_cvt_f16_f32_e32 v13, v85934; SI-NEXT: v_cvt_f16_f32_e32 v10, v105935; SI-NEXT: v_cvt_f16_f32_e32 v12, v95936; SI-NEXT: v_cvt_f32_f16_e32 v8, v115937; SI-NEXT: v_cvt_f32_f16_e32 v11, v135938; SI-NEXT: v_and_b32_e32 v13, 0x1ff, v75939; SI-NEXT: v_or_b32_e32 v6, v13, v65940; SI-NEXT: v_cvt_f32_f16_e32 v9, v105941; SI-NEXT: v_cvt_f32_f16_e32 v10, v125942; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v75943; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65944; SI-NEXT: v_and_b32_e32 v12, 0xffe, v125945; SI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc5946; SI-NEXT: v_bfe_u32 v13, v7, 20, 115947; SI-NEXT: s_movk_i32 s4, 0x3f15948; SI-NEXT: v_or_b32_e32 v6, v12, v65949; SI-NEXT: v_sub_i32_e32 v14, vcc, s4, v135950; SI-NEXT: v_or_b32_e32 v12, 0x1000, v65951; SI-NEXT: v_med3_i32 v14, v14, 0, 135952; SI-NEXT: v_lshrrev_b32_e32 v15, v14, v125953; SI-NEXT: v_lshlrev_b32_e32 v14, v14, v155954; SI-NEXT: v_cmp_ne_u32_e32 vcc, v14, v125955; SI-NEXT: s_movk_i32 s5, 0xfc105956; SI-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc5957; SI-NEXT: v_add_i32_e32 v13, vcc, s5, v135958; SI-NEXT: v_lshlrev_b32_e32 v14, 12, v135959; SI-NEXT: v_or_b32_e32 v12, v15, v125960; SI-NEXT: v_or_b32_e32 v14, v6, v145961; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v135962; SI-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc5963; SI-NEXT: v_and_b32_e32 v14, 7, v125964; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v145965; SI-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc5966; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v145967; SI-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc5968; SI-NEXT: v_or_b32_e32 v14, v14, v155969; SI-NEXT: v_lshrrev_b32_e32 v12, 2, v125970; SI-NEXT: v_add_i32_e32 v12, vcc, v12, v145971; SI-NEXT: v_mov_b32_e32 v14, 0x7c005972; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v135973; SI-NEXT: v_cndmask_b32_e32 v12, v14, v12, vcc5974; SI-NEXT: v_mov_b32_e32 v15, 0x7e005975; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65976; SI-NEXT: s_movk_i32 s6, 0x40f5977; SI-NEXT: v_cndmask_b32_e32 v6, v14, v15, vcc5978; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v135979; SI-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc5980; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v75981; SI-NEXT: v_and_b32_e32 v12, 0x1ff, v55982; SI-NEXT: v_and_b32_e32 v7, 0x8000, v75983; SI-NEXT: v_or_b32_e32 v4, v12, v45984; SI-NEXT: v_or_b32_e32 v6, v7, v65985; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v55986; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v45987; SI-NEXT: v_and_b32_e32 v7, 0xffe, v75988; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc5989; SI-NEXT: v_bfe_u32 v12, v5, 20, 115990; SI-NEXT: v_or_b32_e32 v4, v7, v45991; SI-NEXT: v_sub_i32_e32 v13, vcc, s4, v125992; SI-NEXT: v_or_b32_e32 v7, 0x1000, v45993; SI-NEXT: v_med3_i32 v13, v13, 0, 135994; SI-NEXT: v_lshrrev_b32_e32 v16, v13, v75995; SI-NEXT: v_lshlrev_b32_e32 v13, v13, v165996; SI-NEXT: v_cmp_ne_u32_e32 vcc, v13, v75997; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc5998; SI-NEXT: v_add_i32_e32 v12, vcc, s5, v125999; SI-NEXT: v_lshlrev_b32_e32 v13, 12, v126000; SI-NEXT: v_or_b32_e32 v7, v16, v76001; SI-NEXT: v_or_b32_e32 v13, v4, v136002; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v126003; SI-NEXT: v_cndmask_b32_e32 v7, v13, v7, vcc6004; SI-NEXT: v_and_b32_e32 v13, 7, v76005; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v136006; SI-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc6007; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v136008; SI-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc6009; SI-NEXT: v_or_b32_e32 v13, v13, v166010; SI-NEXT: v_lshrrev_b32_e32 v7, 2, v76011; SI-NEXT: v_add_i32_e32 v7, vcc, v7, v136012; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v126013; SI-NEXT: v_cndmask_b32_e32 v7, v14, v7, vcc6014; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46015; SI-NEXT: v_cndmask_b32_e32 v4, v14, v15, vcc6016; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v126017; SI-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc6018; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v56019; SI-NEXT: v_and_b32_e32 v7, 0x1ff, v36020; SI-NEXT: v_and_b32_e32 v5, 0x8000, v56021; SI-NEXT: v_or_b32_e32 v2, v7, v26022; SI-NEXT: v_or_b32_e32 v4, v5, v46023; SI-NEXT: v_lshrrev_b32_e32 v5, 8, v36024; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26025; SI-NEXT: v_and_b32_e32 v5, 0xffe, v56026; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc6027; SI-NEXT: v_bfe_u32 v7, v3, 20, 116028; SI-NEXT: v_or_b32_e32 v2, v5, v26029; SI-NEXT: v_sub_i32_e32 v12, vcc, s4, v76030; SI-NEXT: v_or_b32_e32 v5, 0x1000, v26031; SI-NEXT: v_med3_i32 v12, v12, 0, 136032; SI-NEXT: v_lshrrev_b32_e32 v13, v12, v56033; SI-NEXT: v_lshlrev_b32_e32 v12, v12, v136034; SI-NEXT: v_cmp_ne_u32_e32 vcc, v12, v56035; SI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc6036; SI-NEXT: v_add_i32_e32 v7, vcc, s5, v76037; SI-NEXT: v_lshlrev_b32_e32 v12, 12, v76038; SI-NEXT: v_or_b32_e32 v5, v13, v56039; SI-NEXT: v_or_b32_e32 v12, v2, v126040; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v76041; SI-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc6042; SI-NEXT: v_and_b32_e32 v12, 7, v56043; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v126044; SI-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc6045; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v126046; SI-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc6047; SI-NEXT: v_or_b32_e32 v12, v12, v136048; SI-NEXT: v_lshrrev_b32_e32 v5, 2, v56049; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v126050; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v76051; SI-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc6052; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26053; SI-NEXT: v_cndmask_b32_e32 v2, v14, v15, vcc6054; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v76055; SI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc6056; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v36057; SI-NEXT: v_and_b32_e32 v5, 0x1ff, v16058; SI-NEXT: v_and_b32_e32 v3, 0x8000, v36059; SI-NEXT: v_or_b32_e32 v0, v5, v06060; SI-NEXT: v_or_b32_e32 v2, v3, v26061; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v16062; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06063; SI-NEXT: v_and_b32_e32 v3, 0xffe, v36064; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc6065; SI-NEXT: v_bfe_u32 v5, v1, 20, 116066; SI-NEXT: v_or_b32_e32 v0, v3, v06067; SI-NEXT: v_sub_i32_e32 v7, vcc, s4, v56068; SI-NEXT: v_or_b32_e32 v3, 0x1000, v06069; SI-NEXT: v_med3_i32 v7, v7, 0, 136070; SI-NEXT: v_lshrrev_b32_e32 v12, v7, v36071; SI-NEXT: v_lshlrev_b32_e32 v7, v7, v126072; SI-NEXT: v_cmp_ne_u32_e32 vcc, v7, v36073; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc6074; SI-NEXT: v_add_i32_e32 v5, vcc, s5, v56075; SI-NEXT: v_lshlrev_b32_e32 v7, 12, v56076; SI-NEXT: v_or_b32_e32 v3, v12, v36077; SI-NEXT: v_or_b32_e32 v7, v0, v76078; SI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v56079; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc6080; SI-NEXT: v_and_b32_e32 v7, 7, v36081; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v76082; SI-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc6083; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v76084; SI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc6085; SI-NEXT: v_or_b32_e32 v7, v7, v126086; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v36087; SI-NEXT: v_add_i32_e32 v3, vcc, v3, v76088; SI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v56089; SI-NEXT: v_cndmask_b32_e32 v3, v14, v3, vcc6090; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06091; SI-NEXT: v_cndmask_b32_e32 v0, v14, v15, vcc6092; SI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v56093; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v16094; SI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc6095; SI-NEXT: v_and_b32_e32 v1, 0x8000, v16096; SI-NEXT: v_or_b32_e32 v0, v1, v06097; SI-NEXT: v_cvt_f32_f16_e32 v6, v66098; SI-NEXT: v_cvt_f32_f16_e32 v0, v06099; SI-NEXT: v_cvt_f32_f16_e32 v1, v26100; SI-NEXT: v_cvt_f32_f16_e32 v2, v46101; SI-NEXT: s_brev_b32 s4, -26102; SI-NEXT: v_bfi_b32 v0, s4, v0, v116103; SI-NEXT: v_bfi_b32 v1, s4, v1, v106104; SI-NEXT: v_bfi_b32 v2, s4, v2, v96105; SI-NEXT: v_bfi_b32 v3, s4, v6, v86106; SI-NEXT: s_setpc_b64 s[30:31]6107;6108; VI-LABEL: v_copysign_out_v4f16_mag_v4f64_sign_v4f16:6109; VI: ; %bb.0:6110; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6111; VI-NEXT: v_and_b32_e32 v11, 0x1ff, v56112; VI-NEXT: v_or_b32_e32 v4, v11, v46113; VI-NEXT: v_lshrrev_b32_e32 v10, 8, v56114; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46115; VI-NEXT: v_and_b32_e32 v10, 0xffe, v106116; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc6117; VI-NEXT: v_bfe_u32 v5, v5, 20, 116118; VI-NEXT: s_movk_i32 s4, 0x3f16119; VI-NEXT: v_or_b32_e32 v4, v10, v46120; VI-NEXT: v_sub_u32_e32 v11, vcc, s4, v56121; VI-NEXT: v_or_b32_e32 v10, 0x1000, v46122; VI-NEXT: v_med3_i32 v11, v11, 0, 136123; VI-NEXT: v_lshrrev_b32_e32 v12, v11, v106124; VI-NEXT: v_lshlrev_b32_e32 v11, v11, v126125; VI-NEXT: v_cmp_ne_u32_e32 vcc, v11, v106126; VI-NEXT: s_movk_i32 s5, 0xfc106127; VI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc6128; VI-NEXT: v_add_u32_e32 v5, vcc, s5, v56129; VI-NEXT: v_lshlrev_b32_e32 v11, 12, v56130; VI-NEXT: v_or_b32_e32 v10, v12, v106131; VI-NEXT: v_or_b32_e32 v11, v4, v116132; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v56133; VI-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc6134; VI-NEXT: v_and_b32_e32 v11, 7, v106135; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v116136; VI-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc6137; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v116138; VI-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc6139; VI-NEXT: v_or_b32_e32 v11, v11, v126140; VI-NEXT: v_lshrrev_b32_e32 v10, 2, v106141; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v116142; VI-NEXT: v_mov_b32_e32 v11, 0x7c006143; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v56144; VI-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc6145; VI-NEXT: v_mov_b32_e32 v12, 0x7e006146; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46147; VI-NEXT: s_movk_i32 s6, 0x40f6148; VI-NEXT: v_cndmask_b32_e32 v4, v11, v12, vcc6149; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v56150; VI-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc6151; VI-NEXT: v_and_b32_e32 v10, 0x1ff, v76152; VI-NEXT: v_or_b32_e32 v6, v10, v66153; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v76154; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66155; VI-NEXT: v_and_b32_e32 v5, 0xffe, v56156; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc6157; VI-NEXT: v_bfe_u32 v7, v7, 20, 116158; VI-NEXT: v_or_b32_e32 v5, v5, v66159; VI-NEXT: v_sub_u32_e32 v10, vcc, s4, v76160; VI-NEXT: v_or_b32_e32 v6, 0x1000, v56161; VI-NEXT: v_med3_i32 v10, v10, 0, 136162; VI-NEXT: v_lshrrev_b32_e32 v13, v10, v66163; VI-NEXT: v_lshlrev_b32_e32 v10, v10, v136164; VI-NEXT: v_cmp_ne_u32_e32 vcc, v10, v66165; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc6166; VI-NEXT: v_add_u32_e32 v7, vcc, s5, v76167; VI-NEXT: v_lshlrev_b32_e32 v10, 12, v76168; VI-NEXT: v_or_b32_e32 v6, v13, v66169; VI-NEXT: v_or_b32_e32 v10, v5, v106170; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v76171; VI-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc6172; VI-NEXT: v_and_b32_e32 v10, 7, v66173; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v106174; VI-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc6175; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v106176; VI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc6177; VI-NEXT: v_or_b32_e32 v10, v10, v136178; VI-NEXT: v_lshrrev_b32_e32 v6, 2, v66179; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v106180; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v76181; VI-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc6182; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v56183; VI-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc6184; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v76185; VI-NEXT: v_and_b32_e32 v7, 0x1ff, v16186; VI-NEXT: v_or_b32_e32 v0, v7, v06187; VI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc6188; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v16189; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06190; VI-NEXT: v_and_b32_e32 v6, 0xffe, v66191; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc6192; VI-NEXT: v_bfe_u32 v1, v1, 20, 116193; VI-NEXT: v_or_b32_e32 v0, v6, v06194; VI-NEXT: v_sub_u32_e32 v7, vcc, s4, v16195; VI-NEXT: v_or_b32_e32 v6, 0x1000, v06196; VI-NEXT: v_med3_i32 v7, v7, 0, 136197; VI-NEXT: v_lshrrev_b32_e32 v10, v7, v66198; VI-NEXT: v_lshlrev_b32_e32 v7, v7, v106199; VI-NEXT: v_cmp_ne_u32_e32 vcc, v7, v66200; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc6201; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v16202; VI-NEXT: v_lshlrev_b32_e32 v7, 12, v16203; VI-NEXT: v_or_b32_e32 v6, v10, v66204; VI-NEXT: v_or_b32_e32 v7, v0, v76205; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v16206; VI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc6207; VI-NEXT: v_and_b32_e32 v7, 7, v66208; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v76209; VI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc6210; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v76211; VI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc6212; VI-NEXT: v_or_b32_e32 v7, v7, v106213; VI-NEXT: v_lshrrev_b32_e32 v6, 2, v66214; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v76215; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v16216; VI-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc6217; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06218; VI-NEXT: v_cndmask_b32_e32 v0, v11, v12, vcc6219; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v16220; VI-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc6221; VI-NEXT: v_and_b32_e32 v6, 0x1ff, v36222; VI-NEXT: v_or_b32_e32 v2, v6, v26223; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v36224; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26225; VI-NEXT: v_and_b32_e32 v1, 0xffe, v16226; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc6227; VI-NEXT: v_bfe_u32 v3, v3, 20, 116228; VI-NEXT: v_or_b32_e32 v1, v1, v26229; VI-NEXT: v_sub_u32_e32 v6, vcc, s4, v36230; VI-NEXT: v_or_b32_e32 v2, 0x1000, v16231; VI-NEXT: v_med3_i32 v6, v6, 0, 136232; VI-NEXT: v_lshrrev_b32_e32 v7, v6, v26233; VI-NEXT: v_lshlrev_b32_e32 v6, v6, v76234; VI-NEXT: v_cmp_ne_u32_e32 vcc, v6, v26235; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc6236; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v36237; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v36238; VI-NEXT: v_or_b32_e32 v2, v7, v26239; VI-NEXT: v_or_b32_e32 v6, v1, v66240; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v36241; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc6242; VI-NEXT: v_and_b32_e32 v6, 7, v26243; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v66244; VI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc6245; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v66246; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc6247; VI-NEXT: v_or_b32_e32 v6, v6, v76248; VI-NEXT: v_lshrrev_b32_e32 v2, 2, v26249; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v66250; VI-NEXT: v_cmp_gt_i32_e32 vcc, 31, v36251; VI-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc6252; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16253; VI-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc6254; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v36255; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc6256; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16257; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v06258; VI-NEXT: v_or_b32_e32 v0, v0, v16259; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v56260; VI-NEXT: v_and_b32_e32 v2, 0x7fff, v46261; VI-NEXT: s_mov_b32 s4, 0x7fff7fff6262; VI-NEXT: v_or_b32_e32 v1, v2, v16263; VI-NEXT: v_bfi_b32 v0, s4, v0, v86264; VI-NEXT: v_bfi_b32 v1, s4, v1, v96265; VI-NEXT: s_setpc_b64 s[30:31]6266;6267; GFX9-LABEL: v_copysign_out_v4f16_mag_v4f64_sign_v4f16:6268; GFX9: ; %bb.0:6269; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6270; GFX9-NEXT: s_movk_i32 s4, 0x1ff6271; GFX9-NEXT: v_and_or_b32 v4, v5, s4, v46272; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46273; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc6274; GFX9-NEXT: v_lshrrev_b32_e32 v10, 8, v56275; GFX9-NEXT: s_movk_i32 s5, 0xffe6276; GFX9-NEXT: v_bfe_u32 v11, v5, 20, 116277; GFX9-NEXT: v_and_or_b32 v4, v10, s5, v46278; GFX9-NEXT: v_sub_u32_e32 v12, 0x3f1, v116279; GFX9-NEXT: v_or_b32_e32 v10, 0x1000, v46280; GFX9-NEXT: v_med3_i32 v12, v12, 0, 136281; GFX9-NEXT: v_lshrrev_b32_e32 v13, v12, v106282; GFX9-NEXT: v_lshlrev_b32_e32 v12, v12, v136283; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v12, v106284; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc6285; GFX9-NEXT: v_add_u32_e32 v11, 0xfffffc10, v116286; GFX9-NEXT: v_or_b32_e32 v10, v13, v106287; GFX9-NEXT: v_lshl_or_b32 v12, v11, 12, v46288; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v116289; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc6290; GFX9-NEXT: v_and_b32_e32 v12, 7, v106291; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v126292; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc6293; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v126294; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc6295; GFX9-NEXT: v_or_b32_e32 v12, v12, v136296; GFX9-NEXT: v_lshrrev_b32_e32 v10, 2, v106297; GFX9-NEXT: v_add_u32_e32 v10, v10, v126298; GFX9-NEXT: v_mov_b32_e32 v12, 0x7c006299; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v116300; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc6301; GFX9-NEXT: v_mov_b32_e32 v13, 0x7e006302; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v46303; GFX9-NEXT: s_movk_i32 s6, 0x40f6304; GFX9-NEXT: v_cndmask_b32_e32 v4, v12, v13, vcc6305; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v116306; GFX9-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc6307; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v56308; GFX9-NEXT: s_mov_b32 s7, 0x80006309; GFX9-NEXT: v_and_or_b32 v4, v5, s7, v46310; GFX9-NEXT: v_and_or_b32 v5, v7, s4, v66311; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v56312; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc6313; GFX9-NEXT: v_lshrrev_b32_e32 v6, 8, v76314; GFX9-NEXT: v_bfe_u32 v10, v7, 20, 116315; GFX9-NEXT: v_and_or_b32 v5, v6, s5, v56316; GFX9-NEXT: v_sub_u32_e32 v11, 0x3f1, v106317; GFX9-NEXT: v_or_b32_e32 v6, 0x1000, v56318; GFX9-NEXT: v_med3_i32 v11, v11, 0, 136319; GFX9-NEXT: v_lshrrev_b32_e32 v14, v11, v66320; GFX9-NEXT: v_lshlrev_b32_e32 v11, v11, v146321; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v11, v66322; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc6323; GFX9-NEXT: v_add_u32_e32 v10, 0xfffffc10, v106324; GFX9-NEXT: v_or_b32_e32 v6, v14, v66325; GFX9-NEXT: v_lshl_or_b32 v11, v10, 12, v56326; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v106327; GFX9-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc6328; GFX9-NEXT: v_and_b32_e32 v11, 7, v66329; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v116330; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc6331; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v116332; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc6333; GFX9-NEXT: v_or_b32_e32 v11, v11, v146334; GFX9-NEXT: v_lshrrev_b32_e32 v6, 2, v66335; GFX9-NEXT: v_add_u32_e32 v6, v6, v116336; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v106337; GFX9-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc6338; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v56339; GFX9-NEXT: v_cndmask_b32_e32 v5, v12, v13, vcc6340; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v106341; GFX9-NEXT: v_and_or_b32 v0, v1, s4, v06342; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc6343; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v76344; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06345; GFX9-NEXT: v_and_or_b32 v5, v6, s7, v56346; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc6347; GFX9-NEXT: v_lshrrev_b32_e32 v6, 8, v16348; GFX9-NEXT: v_bfe_u32 v7, v1, 20, 116349; GFX9-NEXT: v_and_or_b32 v0, v6, s5, v06350; GFX9-NEXT: v_sub_u32_e32 v10, 0x3f1, v76351; GFX9-NEXT: v_or_b32_e32 v6, 0x1000, v06352; GFX9-NEXT: v_med3_i32 v10, v10, 0, 136353; GFX9-NEXT: v_lshrrev_b32_e32 v11, v10, v66354; GFX9-NEXT: v_lshlrev_b32_e32 v10, v10, v116355; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v10, v66356; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc6357; GFX9-NEXT: v_add_u32_e32 v7, 0xfffffc10, v76358; GFX9-NEXT: v_or_b32_e32 v6, v11, v66359; GFX9-NEXT: v_lshl_or_b32 v10, v7, 12, v06360; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v76361; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc6362; GFX9-NEXT: v_and_b32_e32 v10, 7, v66363; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v106364; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc6365; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v106366; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc6367; GFX9-NEXT: v_or_b32_e32 v10, v10, v116368; GFX9-NEXT: v_lshrrev_b32_e32 v6, 2, v66369; GFX9-NEXT: v_add_u32_e32 v6, v6, v106370; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v76371; GFX9-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc6372; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06373; GFX9-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc6374; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v76375; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc6376; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v16377; GFX9-NEXT: v_and_or_b32 v0, v1, s7, v06378; GFX9-NEXT: v_and_or_b32 v1, v3, s4, v26379; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16380; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc6381; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v36382; GFX9-NEXT: v_bfe_u32 v6, v3, 20, 116383; GFX9-NEXT: v_and_or_b32 v1, v2, s5, v16384; GFX9-NEXT: v_sub_u32_e32 v7, 0x3f1, v66385; GFX9-NEXT: v_or_b32_e32 v2, 0x1000, v16386; GFX9-NEXT: v_med3_i32 v7, v7, 0, 136387; GFX9-NEXT: v_lshrrev_b32_e32 v10, v7, v26388; GFX9-NEXT: v_lshlrev_b32_e32 v7, v7, v106389; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v7, v26390; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc6391; GFX9-NEXT: v_add_u32_e32 v6, 0xfffffc10, v66392; GFX9-NEXT: v_or_b32_e32 v2, v10, v26393; GFX9-NEXT: v_lshl_or_b32 v7, v6, 12, v16394; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 1, v66395; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc6396; GFX9-NEXT: v_and_b32_e32 v7, 7, v26397; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v76398; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc6399; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v76400; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc6401; GFX9-NEXT: v_or_b32_e32 v7, v7, v106402; GFX9-NEXT: v_lshrrev_b32_e32 v2, 2, v26403; GFX9-NEXT: v_add_u32_e32 v2, v2, v76404; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 31, v66405; GFX9-NEXT: v_cndmask_b32_e32 v2, v12, v2, vcc6406; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16407; GFX9-NEXT: v_cndmask_b32_e32 v1, v12, v13, vcc6408; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s6, v66409; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc6410; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v36411; GFX9-NEXT: v_and_or_b32 v1, v2, s7, v16412; GFX9-NEXT: s_mov_b32 s4, 0x50401006413; GFX9-NEXT: v_perm_b32 v0, v1, v0, s46414; GFX9-NEXT: s_mov_b32 s5, 0x7fff7fff6415; GFX9-NEXT: v_perm_b32 v1, v5, v4, s46416; GFX9-NEXT: v_bfi_b32 v0, s5, v0, v86417; GFX9-NEXT: v_bfi_b32 v1, s5, v1, v96418; GFX9-NEXT: s_setpc_b64 s[30:31]6419;6420; GFX11-TRUE16-LABEL: v_copysign_out_v4f16_mag_v4f64_sign_v4f16:6421; GFX11-TRUE16: ; %bb.0:6422; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6423; GFX11-TRUE16-NEXT: v_and_or_b32 v6, 0x1ff, v7, v66424; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 20, 116425; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 8, v76426; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0x1ff, v5, v46427; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v26428; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v66429; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v12, 0x3f1, v106430; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v56431; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v06432; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 20, 116433; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo6434; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v36435; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v3, 20, 116436; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v1, 20, 116437; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v7.h6438; GFX11-TRUE16-NEXT: v_and_or_b32 v6, 0xffe, v11, v66439; GFX11-TRUE16-NEXT: v_med3_i32 v11, v12, 0, 136440; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, 06441; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)6442; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x1000, v66443; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, v11, v126444; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)6445; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, v11, v146446; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v126447; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 8, v16448; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo6449; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v46450; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)6451; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v14, v116452; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v106453; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo6454; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v14, 0x3f1, v176455; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v10, 12, v66456; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v106457; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)6458; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0xffe, v16, v46459; GFX11-TRUE16-NEXT: v_med3_i32 v14, v14, 0, 136460; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)6461; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v21, v11, vcc_lo6462; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26463; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, 0x7e006464; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x1000, v46465; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v21, 0x3f1, v196466; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 7, v116467; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo6468; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v06469; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v116470; GFX11-TRUE16-NEXT: v_med3_i32 v21, v21, 0, 136471; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)6472; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0xffe, v18, v26473; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo6474; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v166475; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, v14, v226476; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v12, v06477; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo6478; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v166479; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo6480; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v66481; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)6482; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v236483; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, 0x7c00, v13 :: v_dual_add_nc_u32 v11, v11, v166484; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, v14, v186485; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x1000, v26486; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6487; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v12, v226488; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, v21, v146489; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo6490; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v106491; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)6492; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v18, v126493; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, 0x7c00, v11, vcc_lo6494; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v106495; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0xfffffc10, v176496; GFX11-TRUE16-NEXT: v_sub_nc_u32_e32 v10, 0x3f1, v206497; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo6498; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)6499; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v17, 12, v46500; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v176501; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, v21, v226502; GFX11-TRUE16-NEXT: v_med3_i32 v10, v10, 0, 136503; GFX11-TRUE16-NEXT: v_and_or_b32 v6, 0x8000, v15, v66504; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v5.h6505; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc_lo6506; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v146507; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0xfffffc10, v196508; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x1000, v06509; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo6510; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)6511; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v14, 12, v26512; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, v10, v166513; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)6514; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v22, v116515; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 7, v126516; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, v10, v76517; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 2, v126518; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)6519; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v186520; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo6521; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v146522; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v19, v11, vcc_lo6523; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v186524; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 7, v116525; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo6526; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v10, v166527; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 2, v116528; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)6529; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v18, v216530; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo6531; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v196532; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v106533; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0xfffffc10, v206534; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo6535; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v196536; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)6537; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v16, 12, v06538; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo6539; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v166540; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v7 :: v_dual_add_nc_u32 v10, v12, v186541; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v176542; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)6543; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v19, v206544; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 7, v76545; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 2, v76546; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, 0x7c00, v10, vcc_lo6547; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v46548; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, 0x7c00, v13 :: v_dual_add_nc_u32 v11, v11, v126549; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v186550; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo6551; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v186552; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo6553; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v176554; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v4, vcc_lo6555; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v146556; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)6557; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v18, v126558; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, 0x7c00, v11, vcc_lo6559; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26560; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v106561; GFX11-TRUE16-NEXT: v_and_or_b32 v4, 0x8000, v15, v46562; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.h6563; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l6564; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v13, vcc_lo6565; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v146566; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)6567; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo6568; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v166569; GFX11-TRUE16-NEXT: v_and_or_b32 v2, 0x8000, v15, v26570; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, 0x7c00, v7, vcc_lo6571; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v06572; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v1.h6573; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v4, v96574; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v13, vcc_lo6575; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v166576; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)6577; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo6578; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0x8000, v15, v06579; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l6580; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)6581; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v86582; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]6583;6584; GFX11-FAKE16-LABEL: v_copysign_out_v4f16_mag_v4f64_sign_v4f16:6585; GFX11-FAKE16: ; %bb.0:6586; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6587; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0x1ff, v5, v46588; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 20, 116589; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 8, v56590; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0x1ff, v7, v66591; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v76592; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v46593; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v12, 0x3f1, v106594; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v7, 20, 116595; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v06596; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0x1ff, v3, v26597; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo6598; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v66599; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v17, 0x3f1, v156600; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 8, v16601; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v56602; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0xffe, v11, v46603; GFX11-FAKE16-NEXT: v_med3_i32 v11, v12, 0, 136604; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo6605; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v76606; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)6607; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x1000, v46608; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0xffe, v13, v66609; GFX11-FAKE16-NEXT: v_med3_i32 v13, v17, 0, 136610; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)6611; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, v11, v126612; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x1000, v66613; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)6614; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, v11, v146615; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v11, v126616; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v1, 20, 116617; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v16618; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo6619; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)6620; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v116621; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0xfffffc10, v106622; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0xfffffc10, v156623; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, v13, v176624; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 12, v46625; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v106626; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)6627; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, v13, v156628; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v18, v11, vcc_lo6629; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v06630; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v18, 0x3f1, v126631; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)6632; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 7, v116633; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo6634; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26635; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 2, v116636; GFX11-FAKE16-NEXT: v_med3_i32 v18, v18, 0, 136637; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v16, v06638; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo6639; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v13, v176640; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v14, 12, v66641; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo6642; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v196643; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)6644; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v136645; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo6646; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v196647; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo6648; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v146649; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v176650; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc_lo6651; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x1000, v06652; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 8, v36653; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v3, 20, 116654; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v156655; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v106656; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, v18, v166657; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffe, v17, v26658; GFX11-FAKE16-NEXT: v_sub_nc_u32_e32 v17, 0x3f1, v196659; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0xfffffc10, v196660; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)6661; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, 0x7c00, v11 :: v_dual_lshlrev_b32 v18, v18, v206662; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 7, v136663; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x1000, v26664; GFX11-FAKE16-NEXT: v_med3_i32 v17, v17, 0, 136665; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 2, v136666; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v36667; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v156668; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)6669; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, v17, v216670; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo6671; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v156672; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo6673; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v18, v166674; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, 0x7e00 :: v_dual_lshlrev_b32 v17, v17, v236675; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)6676; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v226677; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo6678; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v17, v216679; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)6680; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v156681; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v20, v166682; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo6683; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)6684; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v23, v176685; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0xfffffc10, v126686; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v12, 12, v06687; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v126688; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)6689; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v20, v16, vcc_lo6690; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v46691; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v19, 12, v26692; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, 0x7c00, v18 :: v_dual_and_b32 v15, 7, v166693; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v196694; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)6695; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v20, v17, vcc_lo6696; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v106697; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc_lo6698; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v146699; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)6700; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 7, v176701; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0x8000, v5, v46702; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, 0x7c00, v13, vcc_lo6703; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v156704; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo6705; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v156706; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo6707; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v116708; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)6709; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v136710; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo6711; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v116712; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 2, v166713; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 2, v176714; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo6715; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v66716; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)6717; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v15, v136718; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v206719; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, 0x7c00, v18, vcc_lo6720; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v146721; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)6722; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo6723; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v126724; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, 0x7c00, v13 :: v_dual_add_nc_u32 v10, v16, v116725; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v06726; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v18, vcc_lo6727; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v196728; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)6729; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, 0x7c00, v10, vcc_lo6730; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26731; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v18, vcc_lo6732; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v126733; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo6734; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v196735; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)6736; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0x8000, v1, v06737; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo6738; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0x8000, v3, v26739; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0x8000, v7, v66740; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6741; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401006742; GFX11-FAKE16-NEXT: v_perm_b32 v1, v2, v4, 0x50401006743; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6744; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v86745; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v96746; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]6747 %mag.trunc = fptrunc <4 x double> %mag to <4 x half>6748 %result = call <4 x half> @llvm.copysign.v4f16(<4 x half> %mag.trunc, <4 x half> %sign)6749 ret <4 x half> %result6750}6751 6752define <4 x half> @v_copysign_out_v4f16_mag_v4f16_sign_v4f32(<4 x half> %mag, <4 x float> %sign) {6753; SI-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f32:6754; SI: ; %bb.0:6755; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6756; SI-NEXT: v_cvt_f16_f32_e32 v3, v36757; SI-NEXT: v_cvt_f16_f32_e32 v2, v26758; SI-NEXT: v_cvt_f16_f32_e32 v1, v16759; SI-NEXT: v_cvt_f16_f32_e32 v0, v06760; SI-NEXT: v_cvt_f16_f32_e32 v7, v76761; SI-NEXT: v_cvt_f16_f32_e32 v4, v46762; SI-NEXT: v_cvt_f16_f32_e32 v5, v56763; SI-NEXT: v_cvt_f16_f32_e32 v6, v66764; SI-NEXT: v_cvt_f32_f16_e32 v3, v36765; SI-NEXT: v_cvt_f32_f16_e32 v2, v26766; SI-NEXT: v_cvt_f32_f16_e32 v1, v16767; SI-NEXT: v_cvt_f32_f16_e32 v0, v06768; SI-NEXT: v_cvt_f32_f16_e32 v7, v76769; SI-NEXT: v_cvt_f32_f16_e32 v4, v46770; SI-NEXT: v_cvt_f32_f16_e32 v5, v56771; SI-NEXT: v_cvt_f32_f16_e32 v6, v66772; SI-NEXT: s_brev_b32 s4, -26773; SI-NEXT: v_bfi_b32 v0, s4, v0, v46774; SI-NEXT: v_bfi_b32 v1, s4, v1, v56775; SI-NEXT: v_bfi_b32 v2, s4, v2, v66776; SI-NEXT: v_bfi_b32 v3, s4, v3, v76777; SI-NEXT: s_setpc_b64 s[30:31]6778;6779; VI-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f32:6780; VI: ; %bb.0:6781; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6782; VI-NEXT: v_cvt_f16_f32_e32 v2, v26783; VI-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6784; VI-NEXT: v_cvt_f16_f32_e32 v4, v46785; VI-NEXT: v_cvt_f16_f32_sdwa v5, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD6786; VI-NEXT: s_mov_b32 s4, 0x7fff7fff6787; VI-NEXT: v_or_b32_e32 v2, v2, v36788; VI-NEXT: v_bfi_b32 v0, s4, v0, v26789; VI-NEXT: v_or_b32_e32 v2, v4, v56790; VI-NEXT: v_bfi_b32 v1, s4, v1, v26791; VI-NEXT: s_setpc_b64 s[30:31]6792;6793; GFX9-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f32:6794; GFX9: ; %bb.0:6795; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6796; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v36797; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v26798; GFX9-NEXT: v_cvt_f16_f32_e32 v5, v56799; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v46800; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff6801; GFX9-NEXT: v_pack_b32_f16 v2, v2, v36802; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v26803; GFX9-NEXT: v_pack_b32_f16 v2, v4, v56804; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v26805; GFX9-NEXT: s_setpc_b64 s[30:31]6806;6807; GFX11-TRUE16-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f32:6808; GFX11-TRUE16: ; %bb.0:6809; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6810; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v5.l, v56811; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v36812; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v26813; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.h, v46814; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6815; GFX11-TRUE16-NEXT: v_pack_b32_f16 v3, v2.l, v3.l6816; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v2.h, v5.l6817; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6818; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v36819; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v26820; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]6821;6822; GFX11-FAKE16-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f32:6823; GFX11-FAKE16: ; %bb.0:6824; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6825; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v5, v56826; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v36827; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v26828; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v4, v46829; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6830; GFX11-FAKE16-NEXT: v_pack_b32_f16 v2, v2, v36831; GFX11-FAKE16-NEXT: v_pack_b32_f16 v3, v4, v56832; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6833; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v26834; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v36835; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]6836 %sign.trunc = fptrunc <4 x float> %sign to <4 x half>6837 %out = call <4 x half> @llvm.copysign.v4f16(<4 x half> %mag, <4 x half> %sign.trunc)6838 ret <4 x half> %out6839}6840 6841define <4 x half> @v_copysign_out_v4f16_mag_v4f16_sign_v4f64(<4 x half> %mag, <4 x double> %sign) {6842; SI-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:6843; SI: ; %bb.0:6844; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6845; SI-NEXT: v_cvt_f16_f32_e32 v3, v36846; SI-NEXT: v_cvt_f16_f32_e32 v0, v06847; SI-NEXT: v_cvt_f16_f32_e32 v1, v16848; SI-NEXT: v_cvt_f16_f32_e32 v2, v26849; SI-NEXT: v_cvt_f32_f16_e32 v3, v36850; SI-NEXT: v_cvt_f32_f16_e32 v0, v06851; SI-NEXT: v_cvt_f32_f16_e32 v1, v16852; SI-NEXT: v_cvt_f32_f16_e32 v2, v26853; SI-NEXT: s_brev_b32 s4, -26854; SI-NEXT: v_bfi_b32 v0, s4, v0, v56855; SI-NEXT: v_bfi_b32 v1, s4, v1, v76856; SI-NEXT: v_bfi_b32 v2, s4, v2, v96857; SI-NEXT: v_bfi_b32 v3, s4, v3, v116858; SI-NEXT: s_setpc_b64 s[30:31]6859;6860; VI-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:6861; VI: ; %bb.0:6862; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6863; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v56864; VI-NEXT: v_and_b32_e32 v3, 0x8000, v36865; VI-NEXT: v_or_b32_e32 v2, v3, v26866; VI-NEXT: s_mov_b32 s4, 0x7fff7fff6867; VI-NEXT: v_bfi_b32 v0, s4, v0, v26868; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v96869; VI-NEXT: v_and_b32_e32 v3, 0x8000, v76870; VI-NEXT: v_or_b32_e32 v2, v3, v26871; VI-NEXT: v_bfi_b32 v1, s4, v1, v26872; VI-NEXT: s_setpc_b64 s[30:31]6873;6874; GFX9-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:6875; GFX9: ; %bb.0:6876; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6877; GFX9-NEXT: s_mov_b32 s4, 0x50401006878; GFX9-NEXT: v_perm_b32 v2, v5, v3, s46879; GFX9-NEXT: s_mov_b32 s5, 0x7fff7fff6880; GFX9-NEXT: v_bfi_b32 v0, s5, v0, v26881; GFX9-NEXT: v_perm_b32 v2, v9, v7, s46882; GFX9-NEXT: v_bfi_b32 v1, s5, v1, v26883; GFX9-NEXT: s_setpc_b64 s[30:31]6884;6885; GFX11-TRUE16-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:6886; GFX11-TRUE16: ; %bb.0:6887; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6888; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l6889; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l6890; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6891; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v36892; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v76893; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]6894;6895; GFX11-FAKE16-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:6896; GFX11-FAKE16: ; %bb.0:6897; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6898; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v3, 0x50401006899; GFX11-FAKE16-NEXT: v_perm_b32 v3, v9, v7, 0x50401006900; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6901; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v26902; GFX11-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v36903; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]6904 %sign.trunc = fptrunc <4 x double> %sign to <4 x half>6905 %out = call <4 x half> @llvm.copysign.v4f16(<4 x half> %mag, <4 x half> %sign.trunc)6906 ret <4 x half> %out6907}6908 6909attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }6910