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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SIVI,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=SIVI,VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s5 6define amdgpu_kernel void @s_test_copysign_f32(ptr addrspace(1) %out, float %mag, float %sign) {7; SI-LABEL: s_test_copysign_f32:8; SI: ; %bb.0:9; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x910; SI-NEXT: s_brev_b32 s8, -211; SI-NEXT: s_mov_b32 s7, 0xf00012; SI-NEXT: s_mov_b32 s6, -113; SI-NEXT: s_waitcnt lgkmcnt(0)14; SI-NEXT: v_mov_b32_e32 v0, s215; SI-NEXT: v_mov_b32_e32 v1, s316; SI-NEXT: s_mov_b32 s4, s017; SI-NEXT: s_mov_b32 s5, s118; SI-NEXT: v_bfi_b32 v0, s8, v0, v119; SI-NEXT: buffer_store_dword v0, off, s[4:7], 020; SI-NEXT: s_endpgm21;22; VI-LABEL: s_test_copysign_f32:23; VI: ; %bb.0:24; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2425; VI-NEXT: s_brev_b32 s4, -226; VI-NEXT: s_waitcnt lgkmcnt(0)27; VI-NEXT: v_mov_b32_e32 v0, s228; VI-NEXT: v_mov_b32_e32 v1, s329; VI-NEXT: v_bfi_b32 v2, s4, v0, v130; VI-NEXT: v_mov_b32_e32 v0, s031; VI-NEXT: v_mov_b32_e32 v1, s132; VI-NEXT: flat_store_dword v[0:1], v233; VI-NEXT: s_endpgm34;35; GFX11-LABEL: s_test_copysign_f32:36; GFX11: ; %bb.0:37; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2438; GFX11-NEXT: s_waitcnt lgkmcnt(0)39; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s340; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)41; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s2, v042; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]43; GFX11-NEXT: s_endpgm44 %result = call float @llvm.copysign.f32(float %mag, float %sign)45 store float %result, ptr addrspace(1) %out, align 446 ret void47}48 49define amdgpu_kernel void @s_test_copysign_f32_0(ptr addrspace(1) %out, float %mag) {50; SI-LABEL: s_test_copysign_f32_0:51; SI: ; %bb.0:52; SI-NEXT: s_load_dword s6, s[4:5], 0xb53; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x954; SI-NEXT: s_mov_b32 s3, 0xf00055; SI-NEXT: s_mov_b32 s2, -156; SI-NEXT: s_waitcnt lgkmcnt(0)57; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff58; SI-NEXT: v_mov_b32_e32 v0, s459; SI-NEXT: buffer_store_dword v0, off, s[0:3], 060; SI-NEXT: s_endpgm61;62; VI-LABEL: s_test_copysign_f32_0:63; VI: ; %bb.0:64; VI-NEXT: s_load_dword s2, s[4:5], 0x2c65; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2466; VI-NEXT: s_waitcnt lgkmcnt(0)67; VI-NEXT: s_bitset0_b32 s2, 3168; VI-NEXT: v_mov_b32_e32 v0, s069; VI-NEXT: v_mov_b32_e32 v1, s170; VI-NEXT: v_mov_b32_e32 v2, s271; VI-NEXT: flat_store_dword v[0:1], v272; VI-NEXT: s_endpgm73;74; GFX11-LABEL: s_test_copysign_f32_0:75; GFX11: ; %bb.0:76; GFX11-NEXT: s_clause 0x177; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c78; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2479; GFX11-NEXT: s_waitcnt lgkmcnt(0)80; GFX11-NEXT: s_bitset0_b32 s2, 3181; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)82; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s283; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]84; GFX11-NEXT: s_endpgm85 %result = call float @llvm.copysign.f32(float %mag, float 0.0)86 store float %result, ptr addrspace(1) %out, align 487 ret void88}89 90define amdgpu_kernel void @s_test_copysign_f32_1(ptr addrspace(1) %out, float %mag) {91; SI-LABEL: s_test_copysign_f32_1:92; SI: ; %bb.0:93; SI-NEXT: s_load_dword s6, s[4:5], 0xb94; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x995; SI-NEXT: s_mov_b32 s3, 0xf00096; SI-NEXT: s_mov_b32 s2, -197; SI-NEXT: s_waitcnt lgkmcnt(0)98; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff99; SI-NEXT: v_mov_b32_e32 v0, s4100; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0101; SI-NEXT: s_endpgm102;103; VI-LABEL: s_test_copysign_f32_1:104; VI: ; %bb.0:105; VI-NEXT: s_load_dword s2, s[4:5], 0x2c106; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24107; VI-NEXT: s_waitcnt lgkmcnt(0)108; VI-NEXT: s_bitset0_b32 s2, 31109; VI-NEXT: v_mov_b32_e32 v0, s0110; VI-NEXT: v_mov_b32_e32 v1, s1111; VI-NEXT: v_mov_b32_e32 v2, s2112; VI-NEXT: flat_store_dword v[0:1], v2113; VI-NEXT: s_endpgm114;115; GFX11-LABEL: s_test_copysign_f32_1:116; GFX11: ; %bb.0:117; GFX11-NEXT: s_clause 0x1118; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c119; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24120; GFX11-NEXT: s_waitcnt lgkmcnt(0)121; GFX11-NEXT: s_bitset0_b32 s2, 31122; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)123; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2124; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]125; GFX11-NEXT: s_endpgm126 %result = call float @llvm.copysign.f32(float %mag, float 1.0)127 store float %result, ptr addrspace(1) %out, align 4128 ret void129}130 131define amdgpu_kernel void @s_test_copysign_f32_10.0(ptr addrspace(1) %out, float %mag) {132; SI-LABEL: s_test_copysign_f32_10.0:133; SI: ; %bb.0:134; SI-NEXT: s_load_dword s6, s[4:5], 0xb135; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9136; SI-NEXT: s_mov_b32 s3, 0xf000137; SI-NEXT: s_mov_b32 s2, -1138; SI-NEXT: s_waitcnt lgkmcnt(0)139; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff140; SI-NEXT: v_mov_b32_e32 v0, s4141; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0142; SI-NEXT: s_endpgm143;144; VI-LABEL: s_test_copysign_f32_10.0:145; VI: ; %bb.0:146; VI-NEXT: s_load_dword s2, s[4:5], 0x2c147; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24148; VI-NEXT: s_waitcnt lgkmcnt(0)149; VI-NEXT: s_bitset0_b32 s2, 31150; VI-NEXT: v_mov_b32_e32 v0, s0151; VI-NEXT: v_mov_b32_e32 v1, s1152; VI-NEXT: v_mov_b32_e32 v2, s2153; VI-NEXT: flat_store_dword v[0:1], v2154; VI-NEXT: s_endpgm155;156; GFX11-LABEL: s_test_copysign_f32_10.0:157; GFX11: ; %bb.0:158; GFX11-NEXT: s_clause 0x1159; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c160; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24161; GFX11-NEXT: s_waitcnt lgkmcnt(0)162; GFX11-NEXT: s_bitset0_b32 s2, 31163; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)164; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2165; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]166; GFX11-NEXT: s_endpgm167 %result = call float @llvm.copysign.f32(float %mag, float 10.0)168 store float %result, ptr addrspace(1) %out, align 4169 ret void170}171 172define amdgpu_kernel void @s_test_copysign_f32_neg1(ptr addrspace(1) %out, float %mag) {173; SI-LABEL: s_test_copysign_f32_neg1:174; SI: ; %bb.0:175; SI-NEXT: s_load_dword s6, s[4:5], 0xb176; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9177; SI-NEXT: s_mov_b32 s3, 0xf000178; SI-NEXT: s_mov_b32 s2, -1179; SI-NEXT: s_waitcnt lgkmcnt(0)180; SI-NEXT: s_or_b32 s4, s6, 0x80000000181; SI-NEXT: v_mov_b32_e32 v0, s4182; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0183; SI-NEXT: s_endpgm184;185; VI-LABEL: s_test_copysign_f32_neg1:186; VI: ; %bb.0:187; VI-NEXT: s_load_dword s2, s[4:5], 0x2c188; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24189; VI-NEXT: s_waitcnt lgkmcnt(0)190; VI-NEXT: s_bitset1_b32 s2, 31191; VI-NEXT: v_mov_b32_e32 v0, s0192; VI-NEXT: v_mov_b32_e32 v1, s1193; VI-NEXT: v_mov_b32_e32 v2, s2194; VI-NEXT: flat_store_dword v[0:1], v2195; VI-NEXT: s_endpgm196;197; GFX11-LABEL: s_test_copysign_f32_neg1:198; GFX11: ; %bb.0:199; GFX11-NEXT: s_clause 0x1200; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c201; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24202; GFX11-NEXT: s_waitcnt lgkmcnt(0)203; GFX11-NEXT: s_bitset1_b32 s2, 31204; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)205; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2206; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]207; GFX11-NEXT: s_endpgm208 %result = call float @llvm.copysign.f32(float %mag, float -1.0)209 store float %result, ptr addrspace(1) %out, align 4210 ret void211}212 213define amdgpu_kernel void @s_test_copysign_f32_neg10(ptr addrspace(1) %out, float %mag) {214; SI-LABEL: s_test_copysign_f32_neg10:215; SI: ; %bb.0:216; SI-NEXT: s_load_dword s6, s[4:5], 0xb217; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9218; SI-NEXT: s_mov_b32 s3, 0xf000219; SI-NEXT: s_mov_b32 s2, -1220; SI-NEXT: s_waitcnt lgkmcnt(0)221; SI-NEXT: s_or_b32 s4, s6, 0x80000000222; SI-NEXT: v_mov_b32_e32 v0, s4223; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0224; SI-NEXT: s_endpgm225;226; VI-LABEL: s_test_copysign_f32_neg10:227; VI: ; %bb.0:228; VI-NEXT: s_load_dword s2, s[4:5], 0x2c229; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24230; VI-NEXT: s_waitcnt lgkmcnt(0)231; VI-NEXT: s_bitset1_b32 s2, 31232; VI-NEXT: v_mov_b32_e32 v0, s0233; VI-NEXT: v_mov_b32_e32 v1, s1234; VI-NEXT: v_mov_b32_e32 v2, s2235; VI-NEXT: flat_store_dword v[0:1], v2236; VI-NEXT: s_endpgm237;238; GFX11-LABEL: s_test_copysign_f32_neg10:239; GFX11: ; %bb.0:240; GFX11-NEXT: s_clause 0x1241; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c242; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24243; GFX11-NEXT: s_waitcnt lgkmcnt(0)244; GFX11-NEXT: s_bitset1_b32 s2, 31245; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)246; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2247; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]248; GFX11-NEXT: s_endpgm249 %result = call float @llvm.copysign.f32(float %mag, float -10.0)250 store float %result, ptr addrspace(1) %out, align 4251 ret void252}253 254define amdgpu_kernel void @s_test_copysign_f32_0_mag(ptr addrspace(1) %out, float %sign) {255; SI-LABEL: s_test_copysign_f32_0_mag:256; SI: ; %bb.0:257; SI-NEXT: s_load_dword s6, s[4:5], 0xb258; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9259; SI-NEXT: s_mov_b32 s3, 0xf000260; SI-NEXT: s_mov_b32 s2, -1261; SI-NEXT: s_waitcnt lgkmcnt(0)262; SI-NEXT: s_and_b32 s4, s6, 0x80000000263; SI-NEXT: v_mov_b32_e32 v0, s4264; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0265; SI-NEXT: s_endpgm266;267; VI-LABEL: s_test_copysign_f32_0_mag:268; VI: ; %bb.0:269; VI-NEXT: s_load_dword s2, s[4:5], 0x2c270; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24271; VI-NEXT: s_waitcnt lgkmcnt(0)272; VI-NEXT: s_and_b32 s2, s2, 0x80000000273; VI-NEXT: v_mov_b32_e32 v0, s0274; VI-NEXT: v_mov_b32_e32 v1, s1275; VI-NEXT: v_mov_b32_e32 v2, s2276; VI-NEXT: flat_store_dword v[0:1], v2277; VI-NEXT: s_endpgm278;279; GFX11-LABEL: s_test_copysign_f32_0_mag:280; GFX11: ; %bb.0:281; GFX11-NEXT: s_clause 0x1282; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c283; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24284; GFX11-NEXT: s_waitcnt lgkmcnt(0)285; GFX11-NEXT: s_and_b32 s2, s2, 0x80000000286; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)287; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2288; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]289; GFX11-NEXT: s_endpgm290 %result = call float @llvm.copysign.f32(float 0.0, float %sign)291 store float %result, ptr addrspace(1) %out, align 4292 ret void293}294 295 296define amdgpu_kernel void @s_test_copysign_f32_1_mag(ptr addrspace(1) %out, float %sign) {297; SI-LABEL: s_test_copysign_f32_1_mag:298; SI: ; %bb.0:299; SI-NEXT: s_load_dword s6, s[4:5], 0xb300; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9301; SI-NEXT: s_mov_b32 s3, 0xf000302; SI-NEXT: s_mov_b32 s2, -1303; SI-NEXT: s_waitcnt lgkmcnt(0)304; SI-NEXT: s_and_b32 s4, s6, 0x80000000305; SI-NEXT: s_or_b32 s4, s4, 1.0306; SI-NEXT: v_mov_b32_e32 v0, s4307; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0308; SI-NEXT: s_endpgm309;310; VI-LABEL: s_test_copysign_f32_1_mag:311; VI: ; %bb.0:312; VI-NEXT: s_load_dword s2, s[4:5], 0x2c313; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24314; VI-NEXT: s_waitcnt lgkmcnt(0)315; VI-NEXT: s_and_b32 s2, s2, 0x80000000316; VI-NEXT: s_or_b32 s2, s2, 1.0317; VI-NEXT: v_mov_b32_e32 v0, s0318; VI-NEXT: v_mov_b32_e32 v1, s1319; VI-NEXT: v_mov_b32_e32 v2, s2320; VI-NEXT: flat_store_dword v[0:1], v2321; VI-NEXT: s_endpgm322;323; GFX11-LABEL: s_test_copysign_f32_1_mag:324; GFX11: ; %bb.0:325; GFX11-NEXT: s_clause 0x1326; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c327; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24328; GFX11-NEXT: s_waitcnt lgkmcnt(0)329; GFX11-NEXT: s_and_b32 s2, s2, 0x80000000330; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)331; GFX11-NEXT: s_or_b32 s2, s2, 1.0332; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2333; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]334; GFX11-NEXT: s_endpgm335 %result = call float @llvm.copysign.f32(float 1.0, float %sign)336 store float %result, ptr addrspace(1) %out, align 4337 ret void338}339 340define amdgpu_kernel void @s_test_copysign_f32_10_mag(ptr addrspace(1) %out, float %sign) {341; SI-LABEL: s_test_copysign_f32_10_mag:342; SI: ; %bb.0:343; SI-NEXT: s_load_dword s6, s[4:5], 0xb344; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9345; SI-NEXT: s_mov_b32 s3, 0xf000346; SI-NEXT: s_mov_b32 s2, -1347; SI-NEXT: s_waitcnt lgkmcnt(0)348; SI-NEXT: s_and_b32 s4, s6, 0x80000000349; SI-NEXT: s_or_b32 s4, s4, 0x41200000350; SI-NEXT: v_mov_b32_e32 v0, s4351; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0352; SI-NEXT: s_endpgm353;354; VI-LABEL: s_test_copysign_f32_10_mag:355; VI: ; %bb.0:356; VI-NEXT: s_load_dword s2, s[4:5], 0x2c357; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24358; VI-NEXT: s_waitcnt lgkmcnt(0)359; VI-NEXT: s_and_b32 s2, s2, 0x80000000360; VI-NEXT: s_or_b32 s2, s2, 0x41200000361; VI-NEXT: v_mov_b32_e32 v0, s0362; VI-NEXT: v_mov_b32_e32 v1, s1363; VI-NEXT: v_mov_b32_e32 v2, s2364; VI-NEXT: flat_store_dword v[0:1], v2365; VI-NEXT: s_endpgm366;367; GFX11-LABEL: s_test_copysign_f32_10_mag:368; GFX11: ; %bb.0:369; GFX11-NEXT: s_clause 0x1370; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c371; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24372; GFX11-NEXT: s_waitcnt lgkmcnt(0)373; GFX11-NEXT: s_and_b32 s2, s2, 0x80000000374; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)375; GFX11-NEXT: s_or_b32 s2, s2, 0x41200000376; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2377; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]378; GFX11-NEXT: s_endpgm379 %result = call float @llvm.copysign.f32(float 10.0, float %sign)380 store float %result, ptr addrspace(1) %out, align 4381 ret void382}383 384define amdgpu_kernel void @s_test_copysign_f32_neg1_mag(ptr addrspace(1) %out, float %sign) {385; SI-LABEL: s_test_copysign_f32_neg1_mag:386; SI: ; %bb.0:387; SI-NEXT: s_load_dword s6, s[4:5], 0xb388; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9389; SI-NEXT: s_mov_b32 s3, 0xf000390; SI-NEXT: s_mov_b32 s2, -1391; SI-NEXT: s_waitcnt lgkmcnt(0)392; SI-NEXT: s_and_b32 s4, s6, 0x80000000393; SI-NEXT: s_or_b32 s4, s4, 1.0394; SI-NEXT: v_mov_b32_e32 v0, s4395; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0396; SI-NEXT: s_endpgm397;398; VI-LABEL: s_test_copysign_f32_neg1_mag:399; VI: ; %bb.0:400; VI-NEXT: s_load_dword s2, s[4:5], 0x2c401; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24402; VI-NEXT: s_waitcnt lgkmcnt(0)403; VI-NEXT: s_and_b32 s2, s2, 0x80000000404; VI-NEXT: s_or_b32 s2, s2, 1.0405; VI-NEXT: v_mov_b32_e32 v0, s0406; VI-NEXT: v_mov_b32_e32 v1, s1407; VI-NEXT: v_mov_b32_e32 v2, s2408; VI-NEXT: flat_store_dword v[0:1], v2409; VI-NEXT: s_endpgm410;411; GFX11-LABEL: s_test_copysign_f32_neg1_mag:412; GFX11: ; %bb.0:413; GFX11-NEXT: s_clause 0x1414; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c415; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24416; GFX11-NEXT: s_waitcnt lgkmcnt(0)417; GFX11-NEXT: s_and_b32 s2, s2, 0x80000000418; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)419; GFX11-NEXT: s_or_b32 s2, s2, 1.0420; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2421; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]422; GFX11-NEXT: s_endpgm423 %result = call float @llvm.copysign.f32(float -1.0, float %sign)424 store float %result, ptr addrspace(1) %out, align 4425 ret void426}427 428define amdgpu_kernel void @s_test_copysign_f32_neg10_mag(ptr addrspace(1) %out, float %sign) {429; SI-LABEL: s_test_copysign_f32_neg10_mag:430; SI: ; %bb.0:431; SI-NEXT: s_load_dword s6, s[4:5], 0xb432; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9433; SI-NEXT: s_mov_b32 s3, 0xf000434; SI-NEXT: s_mov_b32 s2, -1435; SI-NEXT: s_waitcnt lgkmcnt(0)436; SI-NEXT: s_and_b32 s4, s6, 0x80000000437; SI-NEXT: s_or_b32 s4, s4, 0x41200000438; SI-NEXT: v_mov_b32_e32 v0, s4439; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0440; SI-NEXT: s_endpgm441;442; VI-LABEL: s_test_copysign_f32_neg10_mag:443; VI: ; %bb.0:444; VI-NEXT: s_load_dword s2, s[4:5], 0x2c445; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24446; VI-NEXT: s_waitcnt lgkmcnt(0)447; VI-NEXT: s_and_b32 s2, s2, 0x80000000448; VI-NEXT: s_or_b32 s2, s2, 0x41200000449; VI-NEXT: v_mov_b32_e32 v0, s0450; VI-NEXT: v_mov_b32_e32 v1, s1451; VI-NEXT: v_mov_b32_e32 v2, s2452; VI-NEXT: flat_store_dword v[0:1], v2453; VI-NEXT: s_endpgm454;455; GFX11-LABEL: s_test_copysign_f32_neg10_mag:456; GFX11: ; %bb.0:457; GFX11-NEXT: s_clause 0x1458; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c459; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24460; GFX11-NEXT: s_waitcnt lgkmcnt(0)461; GFX11-NEXT: s_and_b32 s2, s2, 0x80000000462; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)463; GFX11-NEXT: s_or_b32 s2, s2, 0x41200000464; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2465; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]466; GFX11-NEXT: s_endpgm467 %result = call float @llvm.copysign.f32(float -10.0, float %sign)468 store float %result, ptr addrspace(1) %out, align 4469 ret void470}471 472define amdgpu_kernel void @s_test_copysign_v2f32(ptr addrspace(1) %out, <2 x float> %mag, <2 x float> %sign) {473; SI-LABEL: s_test_copysign_v2f32:474; SI: ; %bb.0:475; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb476; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9477; SI-NEXT: s_brev_b32 s8, -2478; SI-NEXT: s_mov_b32 s7, 0xf000479; SI-NEXT: s_mov_b32 s6, -1480; SI-NEXT: s_waitcnt lgkmcnt(0)481; SI-NEXT: v_mov_b32_e32 v0, s1482; SI-NEXT: v_mov_b32_e32 v1, s3483; SI-NEXT: v_bfi_b32 v1, s8, v0, v1484; SI-NEXT: v_mov_b32_e32 v0, s0485; SI-NEXT: v_mov_b32_e32 v2, s2486; SI-NEXT: v_bfi_b32 v0, s8, v0, v2487; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0488; SI-NEXT: s_endpgm489;490; VI-LABEL: s_test_copysign_v2f32:491; VI: ; %bb.0:492; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c493; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24494; VI-NEXT: s_brev_b32 s6, -2495; VI-NEXT: s_waitcnt lgkmcnt(0)496; VI-NEXT: v_mov_b32_e32 v0, s1497; VI-NEXT: v_mov_b32_e32 v1, s3498; VI-NEXT: v_mov_b32_e32 v2, s0499; VI-NEXT: v_bfi_b32 v1, s6, v0, v1500; VI-NEXT: v_mov_b32_e32 v0, s2501; VI-NEXT: v_bfi_b32 v0, s6, v2, v0502; VI-NEXT: v_mov_b32_e32 v2, s4503; VI-NEXT: v_mov_b32_e32 v3, s5504; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]505; VI-NEXT: s_endpgm506;507; GFX11-LABEL: s_test_copysign_v2f32:508; GFX11: ; %bb.0:509; GFX11-NEXT: s_clause 0x1510; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c511; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24512; GFX11-NEXT: s_waitcnt lgkmcnt(0)513; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s3514; GFX11-NEXT: v_mov_b32_e32 v2, s2515; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)516; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v0517; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v2518; GFX11-NEXT: global_store_b64 v3, v[0:1], s[4:5]519; GFX11-NEXT: s_endpgm520 %result = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag, <2 x float> %sign)521 store <2 x float> %result, ptr addrspace(1) %out, align 8522 ret void523}524 525define amdgpu_kernel void @s_test_copysign_v3f32(ptr addrspace(1) %out, <3 x float> %mag, <3 x float> %sign) {526; SI-LABEL: s_test_copysign_v3f32:527; SI: ; %bb.0:528; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd529; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9530; SI-NEXT: s_brev_b32 s6, -2531; SI-NEXT: s_mov_b32 s3, 0xf000532; SI-NEXT: s_mov_b32 s2, -1533; SI-NEXT: s_waitcnt lgkmcnt(0)534; SI-NEXT: v_mov_b32_e32 v0, s9535; SI-NEXT: v_mov_b32_e32 v1, s13536; SI-NEXT: v_bfi_b32 v1, s6, v0, v1537; SI-NEXT: v_mov_b32_e32 v0, s8538; SI-NEXT: v_mov_b32_e32 v2, s12539; SI-NEXT: v_bfi_b32 v0, s6, v0, v2540; SI-NEXT: v_mov_b32_e32 v2, s10541; SI-NEXT: v_mov_b32_e32 v3, s14542; SI-NEXT: v_bfi_b32 v2, s6, v2, v3543; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8544; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0545; SI-NEXT: s_endpgm546;547; VI-LABEL: s_test_copysign_v3f32:548; VI: ; %bb.0:549; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34550; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24551; VI-NEXT: s_brev_b32 s2, -2552; VI-NEXT: s_waitcnt lgkmcnt(0)553; VI-NEXT: v_mov_b32_e32 v0, s10554; VI-NEXT: v_mov_b32_e32 v1, s14555; VI-NEXT: v_mov_b32_e32 v3, s9556; VI-NEXT: v_bfi_b32 v2, s2, v0, v1557; VI-NEXT: v_mov_b32_e32 v0, s13558; VI-NEXT: v_bfi_b32 v1, s2, v3, v0559; VI-NEXT: v_mov_b32_e32 v0, s8560; VI-NEXT: v_mov_b32_e32 v3, s12561; VI-NEXT: v_bfi_b32 v0, s2, v0, v3562; VI-NEXT: v_mov_b32_e32 v4, s1563; VI-NEXT: v_mov_b32_e32 v3, s0564; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]565; VI-NEXT: s_endpgm566;567; GFX11-LABEL: s_test_copysign_v3f32:568; GFX11: ; %bb.0:569; GFX11-NEXT: s_clause 0x1570; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34571; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24572; GFX11-NEXT: s_waitcnt lgkmcnt(0)573; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s12574; GFX11-NEXT: v_dual_mov_b32 v0, s14 :: v_dual_mov_b32 v1, s13575; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)576; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, s10, v0577; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, s9, v1578; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)579; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s8, v3580; GFX11-NEXT: global_store_b96 v4, v[0:2], s[0:1]581; GFX11-NEXT: s_endpgm582 %result = call <3 x float> @llvm.copysign.v3f32(<3 x float> %mag, <3 x float> %sign)583 store <3 x float> %result, ptr addrspace(1) %out, align 16584 ret void585}586 587define amdgpu_kernel void @s_test_copysign_v4f32(ptr addrspace(1) %out, <4 x float> %mag, <4 x float> %sign) {588; SI-LABEL: s_test_copysign_v4f32:589; SI: ; %bb.0:590; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd591; SI-NEXT: s_brev_b32 s6, -2592; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9593; SI-NEXT: s_mov_b32 s3, 0xf000594; SI-NEXT: s_mov_b32 s2, -1595; SI-NEXT: s_waitcnt lgkmcnt(0)596; SI-NEXT: v_mov_b32_e32 v0, s11597; SI-NEXT: v_mov_b32_e32 v1, s15598; SI-NEXT: v_bfi_b32 v3, s6, v0, v1599; SI-NEXT: v_mov_b32_e32 v0, s10600; SI-NEXT: v_mov_b32_e32 v1, s14601; SI-NEXT: v_bfi_b32 v2, s6, v0, v1602; SI-NEXT: v_mov_b32_e32 v0, s9603; SI-NEXT: v_mov_b32_e32 v1, s13604; SI-NEXT: v_bfi_b32 v1, s6, v0, v1605; SI-NEXT: v_mov_b32_e32 v0, s8606; SI-NEXT: v_mov_b32_e32 v4, s12607; SI-NEXT: v_bfi_b32 v0, s6, v0, v4608; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0609; SI-NEXT: s_endpgm610;611; VI-LABEL: s_test_copysign_v4f32:612; VI: ; %bb.0:613; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34614; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24615; VI-NEXT: s_brev_b32 s2, -2616; VI-NEXT: s_waitcnt lgkmcnt(0)617; VI-NEXT: v_mov_b32_e32 v0, s11618; VI-NEXT: v_mov_b32_e32 v1, s15619; VI-NEXT: v_mov_b32_e32 v2, s10620; VI-NEXT: v_bfi_b32 v3, s2, v0, v1621; VI-NEXT: v_mov_b32_e32 v0, s14622; VI-NEXT: v_bfi_b32 v2, s2, v2, v0623; VI-NEXT: v_mov_b32_e32 v0, s9624; VI-NEXT: v_mov_b32_e32 v1, s13625; VI-NEXT: v_bfi_b32 v1, s2, v0, v1626; VI-NEXT: v_mov_b32_e32 v0, s8627; VI-NEXT: v_mov_b32_e32 v4, s12628; VI-NEXT: v_bfi_b32 v0, s2, v0, v4629; VI-NEXT: v_mov_b32_e32 v5, s1630; VI-NEXT: v_mov_b32_e32 v4, s0631; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]632; VI-NEXT: s_endpgm633;634; GFX11-LABEL: s_test_copysign_v4f32:635; GFX11: ; %bb.0:636; GFX11-NEXT: s_clause 0x1637; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34638; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24639; GFX11-NEXT: v_mov_b32_e32 v6, 0640; GFX11-NEXT: s_waitcnt lgkmcnt(0)641; GFX11-NEXT: v_dual_mov_b32 v0, s15 :: v_dual_mov_b32 v1, s14642; GFX11-NEXT: v_dual_mov_b32 v4, s13 :: v_dual_mov_b32 v5, s12643; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)644; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, s11, v0645; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, s10, v1646; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)647; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, s9, v4648; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s8, v5649; GFX11-NEXT: global_store_b128 v6, v[0:3], s[0:1]650; GFX11-NEXT: s_endpgm651 %result = call <4 x float> @llvm.copysign.v4f32(<4 x float> %mag, <4 x float> %sign)652 store <4 x float> %result, ptr addrspace(1) %out, align 16653 ret void654}655 656define float @v_test_copysign_f32(float %mag, float %sign) {657; SIVI-LABEL: v_test_copysign_f32:658; SIVI: ; %bb.0:659; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)660; SIVI-NEXT: s_brev_b32 s4, -2661; SIVI-NEXT: v_bfi_b32 v0, s4, v0, v1662; SIVI-NEXT: s_setpc_b64 s[30:31]663;664; GFX11-LABEL: v_test_copysign_f32:665; GFX11: ; %bb.0:666; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)667; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1668; GFX11-NEXT: s_setpc_b64 s[30:31]669 %result = call float @llvm.copysign.f32(float %mag, float %sign)670 ret float %result671}672 673define float @v_test_copysign_f32_0(float %mag) {674; SIVI-LABEL: v_test_copysign_f32_0:675; SIVI: ; %bb.0:676; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)677; SIVI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0678; SIVI-NEXT: s_setpc_b64 s[30:31]679;680; GFX11-LABEL: v_test_copysign_f32_0:681; GFX11: ; %bb.0:682; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)683; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0684; GFX11-NEXT: s_setpc_b64 s[30:31]685 %result = call float @llvm.copysign.f32(float %mag, float 0.0)686 ret float %result687}688 689define float @v_test_copysign_f32_1(float %mag) {690; SIVI-LABEL: v_test_copysign_f32_1:691; SIVI: ; %bb.0:692; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)693; SIVI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0694; SIVI-NEXT: s_setpc_b64 s[30:31]695;696; GFX11-LABEL: v_test_copysign_f32_1:697; GFX11: ; %bb.0:698; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)699; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0700; GFX11-NEXT: s_setpc_b64 s[30:31]701 %result = call float @llvm.copysign.f32(float %mag, float 1.0)702 ret float %result703}704 705define float @v_test_copysign_f32_10(float %mag) {706; SIVI-LABEL: v_test_copysign_f32_10:707; SIVI: ; %bb.0:708; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)709; SIVI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0710; SIVI-NEXT: s_setpc_b64 s[30:31]711;712; GFX11-LABEL: v_test_copysign_f32_10:713; GFX11: ; %bb.0:714; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)715; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0716; GFX11-NEXT: s_setpc_b64 s[30:31]717 %result = call float @llvm.copysign.f32(float %mag, float 10.0)718 ret float %result719}720 721define float @v_test_copysign_f32_neg1(float %mag) {722; SIVI-LABEL: v_test_copysign_f32_neg1:723; SIVI: ; %bb.0:724; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)725; SIVI-NEXT: v_or_b32_e32 v0, 0x80000000, v0726; SIVI-NEXT: s_setpc_b64 s[30:31]727;728; GFX11-LABEL: v_test_copysign_f32_neg1:729; GFX11: ; %bb.0:730; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)731; GFX11-NEXT: v_or_b32_e32 v0, 0x80000000, v0732; GFX11-NEXT: s_setpc_b64 s[30:31]733 %result = call float @llvm.copysign.f32(float %mag, float -1.0)734 ret float %result735}736 737define float @v_test_copysign_f32_neg10(float %mag) {738; SIVI-LABEL: v_test_copysign_f32_neg10:739; SIVI: ; %bb.0:740; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)741; SIVI-NEXT: v_or_b32_e32 v0, 0x80000000, v0742; SIVI-NEXT: s_setpc_b64 s[30:31]743;744; GFX11-LABEL: v_test_copysign_f32_neg10:745; GFX11: ; %bb.0:746; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)747; GFX11-NEXT: v_or_b32_e32 v0, 0x80000000, v0748; GFX11-NEXT: s_setpc_b64 s[30:31]749 %result = call float @llvm.copysign.f32(float %mag, float -10.0)750 ret float %result751}752 753define <2 x float> @v_test_copysign_v2f32(<2 x float> %mag, <2 x float> %sign) {754; SIVI-LABEL: v_test_copysign_v2f32:755; SIVI: ; %bb.0:756; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)757; SIVI-NEXT: s_brev_b32 s4, -2758; SIVI-NEXT: v_bfi_b32 v0, s4, v0, v2759; SIVI-NEXT: v_bfi_b32 v1, s4, v1, v3760; SIVI-NEXT: s_setpc_b64 s[30:31]761;762; GFX11-LABEL: v_test_copysign_v2f32:763; GFX11: ; %bb.0:764; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)765; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v2766; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v3767; GFX11-NEXT: s_setpc_b64 s[30:31]768 %result = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag, <2 x float> %sign)769 ret <2 x float> %result770}771 772define <2 x float> @v_test_copysign_v2f32_0(<2 x float> %mag) {773; SIVI-LABEL: v_test_copysign_v2f32_0:774; SIVI: ; %bb.0:775; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)776; SIVI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0777; SIVI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1778; SIVI-NEXT: s_setpc_b64 s[30:31]779;780; GFX11-LABEL: v_test_copysign_v2f32_0:781; GFX11: ; %bb.0:782; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)783; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0784; GFX11-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1785; GFX11-NEXT: s_setpc_b64 s[30:31]786 %result = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag, <2 x float> zeroinitializer)787 ret <2 x float> %result788}789 790define <2 x float> @v_test_copysign_v2f32_neg1(<2 x float> %mag) {791; SIVI-LABEL: v_test_copysign_v2f32_neg1:792; SIVI: ; %bb.0:793; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)794; SIVI-NEXT: v_or_b32_e32 v0, 0x80000000, v0795; SIVI-NEXT: v_or_b32_e32 v1, 0x80000000, v1796; SIVI-NEXT: s_setpc_b64 s[30:31]797;798; GFX11-LABEL: v_test_copysign_v2f32_neg1:799; GFX11: ; %bb.0:800; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)801; GFX11-NEXT: v_or_b32_e32 v0, 0x80000000, v0802; GFX11-NEXT: v_or_b32_e32 v1, 0x80000000, v1803; GFX11-NEXT: s_setpc_b64 s[30:31]804 %result = call <2 x float> @llvm.copysign.v2f32(<2 x float> %mag, <2 x float> <float -1.0, float -1.0>)805 ret <2 x float> %result806}807 808define <3 x float> @v_test_copysign_v3f32(<3 x float> %mag, <3 x float> %sign) {809; SIVI-LABEL: v_test_copysign_v3f32:810; SIVI: ; %bb.0:811; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)812; SIVI-NEXT: s_brev_b32 s4, -2813; SIVI-NEXT: v_bfi_b32 v0, s4, v0, v3814; SIVI-NEXT: v_bfi_b32 v1, s4, v1, v4815; SIVI-NEXT: v_bfi_b32 v2, s4, v2, v5816; SIVI-NEXT: s_setpc_b64 s[30:31]817;818; GFX11-LABEL: v_test_copysign_v3f32:819; GFX11: ; %bb.0:820; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)821; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v3822; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4823; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v5824; GFX11-NEXT: s_setpc_b64 s[30:31]825 %result = call <3 x float> @llvm.copysign.v3f32(<3 x float> %mag, <3 x float> %sign)826 ret <3 x float> %result827}828 829define <4 x float> @v_test_copysign_v4f32(<4 x float> %mag, <4 x float> %sign) {830; SIVI-LABEL: v_test_copysign_v4f32:831; SIVI: ; %bb.0:832; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)833; SIVI-NEXT: s_brev_b32 s4, -2834; SIVI-NEXT: v_bfi_b32 v0, s4, v0, v4835; SIVI-NEXT: v_bfi_b32 v1, s4, v1, v5836; SIVI-NEXT: v_bfi_b32 v2, s4, v2, v6837; SIVI-NEXT: v_bfi_b32 v3, s4, v3, v7838; SIVI-NEXT: s_setpc_b64 s[30:31]839;840; GFX11-LABEL: v_test_copysign_v4f32:841; GFX11: ; %bb.0:842; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)843; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v4844; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v5845; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v6846; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v7847; GFX11-NEXT: s_setpc_b64 s[30:31]848 %result = call <4 x float> @llvm.copysign.v4f32(<4 x float> %mag, <4 x float> %sign)849 ret <4 x float> %result850}851 852define <5 x float> @v_test_copysign_v5f32(<5 x float> %mag, <5 x float> %sign) {853; SIVI-LABEL: v_test_copysign_v5f32:854; SIVI: ; %bb.0:855; SIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)856; SIVI-NEXT: s_brev_b32 s4, -2857; SIVI-NEXT: v_bfi_b32 v0, s4, v0, v5858; SIVI-NEXT: v_bfi_b32 v1, s4, v1, v6859; SIVI-NEXT: v_bfi_b32 v2, s4, v2, v7860; SIVI-NEXT: v_bfi_b32 v3, s4, v3, v8861; SIVI-NEXT: v_bfi_b32 v4, s4, v4, v9862; SIVI-NEXT: s_setpc_b64 s[30:31]863;864; GFX11-LABEL: v_test_copysign_v5f32:865; GFX11: ; %bb.0:866; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)867; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v5868; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v6869; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v7870; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v8871; GFX11-NEXT: v_bfi_b32 v4, 0x7fffffff, v4, v9872; GFX11-NEXT: s_setpc_b64 s[30:31]873 %result = call <5 x float> @llvm.copysign.v5f32(<5 x float> %mag, <5 x float> %sign)874 ret <5 x float> %result875}876 877define amdgpu_kernel void @s_test_copysign_f32_fptrunc_f64(ptr addrspace(1) %out, float %mag, double %sign) {878; SI-LABEL: s_test_copysign_f32_fptrunc_f64:879; SI: ; %bb.0:880; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9881; SI-NEXT: s_load_dword s6, s[4:5], 0xb882; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd883; SI-NEXT: s_waitcnt lgkmcnt(0)884; SI-NEXT: s_brev_b32 s4, -2885; SI-NEXT: s_mov_b32 s3, 0xf000886; SI-NEXT: s_mov_b32 s2, -1887; SI-NEXT: v_mov_b32_e32 v0, s6888; SI-NEXT: v_mov_b32_e32 v1, s5889; SI-NEXT: v_bfi_b32 v0, s4, v0, v1890; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0891; SI-NEXT: s_endpgm892;893; VI-LABEL: s_test_copysign_f32_fptrunc_f64:894; VI: ; %bb.0:895; VI-NEXT: s_load_dword s6, s[4:5], 0x2c896; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34897; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24898; VI-NEXT: s_waitcnt lgkmcnt(0)899; VI-NEXT: s_brev_b32 s0, -2900; VI-NEXT: v_mov_b32_e32 v0, s6901; VI-NEXT: v_mov_b32_e32 v1, s1902; VI-NEXT: v_bfi_b32 v2, s0, v0, v1903; VI-NEXT: v_mov_b32_e32 v0, s2904; VI-NEXT: v_mov_b32_e32 v1, s3905; VI-NEXT: flat_store_dword v[0:1], v2906; VI-NEXT: s_endpgm907;908; GFX11-LABEL: s_test_copysign_f32_fptrunc_f64:909; GFX11: ; %bb.0:910; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x34911; GFX11-NEXT: s_waitcnt lgkmcnt(0)912; GFX11-NEXT: s_clause 0x1913; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c914; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24915; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s1916; GFX11-NEXT: s_waitcnt lgkmcnt(0)917; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)918; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0919; GFX11-NEXT: global_store_b32 v1, v0, s[2:3]920; GFX11-NEXT: s_endpgm921 %sign.trunc = fptrunc double %sign to float922 %result = call float @llvm.copysign.f32(float %mag, float %sign.trunc)923 store float %result, ptr addrspace(1) %out, align 4924 ret void925}926 927define amdgpu_kernel void @s_test_copysign_f32_1_fptrunc_f64(ptr addrspace(1) %out, double %sign) {928; SI-LABEL: s_test_copysign_f32_1_fptrunc_f64:929; SI: ; %bb.0:930; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9931; SI-NEXT: s_mov_b32 s7, 0xf000932; SI-NEXT: s_mov_b32 s6, -1933; SI-NEXT: s_waitcnt lgkmcnt(0)934; SI-NEXT: s_mov_b32 s4, s0935; SI-NEXT: s_and_b32 s0, s3, 0x80000000936; SI-NEXT: s_or_b32 s0, s0, 1.0937; SI-NEXT: s_mov_b32 s5, s1938; SI-NEXT: v_mov_b32_e32 v0, s0939; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0940; SI-NEXT: s_endpgm941;942; VI-LABEL: s_test_copysign_f32_1_fptrunc_f64:943; VI: ; %bb.0:944; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24945; VI-NEXT: s_waitcnt lgkmcnt(0)946; VI-NEXT: v_mov_b32_e32 v0, s0947; VI-NEXT: s_and_b32 s0, s3, 0x80000000948; VI-NEXT: s_or_b32 s0, s0, 1.0949; VI-NEXT: v_mov_b32_e32 v1, s1950; VI-NEXT: v_mov_b32_e32 v2, s0951; VI-NEXT: flat_store_dword v[0:1], v2952; VI-NEXT: s_endpgm953;954; GFX11-LABEL: s_test_copysign_f32_1_fptrunc_f64:955; GFX11: ; %bb.0:956; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24957; GFX11-NEXT: s_waitcnt lgkmcnt(0)958; GFX11-NEXT: s_and_b32 s2, s3, 0x80000000959; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)960; GFX11-NEXT: s_or_b32 s2, s2, 1.0961; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2962; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]963; GFX11-NEXT: s_endpgm964 %sign.trunc = fptrunc double %sign to float965 %result = call float @llvm.copysign.f32(float 1.0, float %sign.trunc)966 store float %result, ptr addrspace(1) %out, align 4967 ret void968}969 970define amdgpu_kernel void @s_test_copysign_f32_fpext_f16(ptr addrspace(1) %out, float %mag, half %sign) {971; SI-LABEL: s_test_copysign_f32_fpext_f16:972; SI: ; %bb.0:973; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9974; SI-NEXT: s_mov_b32 s7, 0xf000975; SI-NEXT: s_mov_b32 s6, -1976; SI-NEXT: s_waitcnt lgkmcnt(0)977; SI-NEXT: v_cvt_f32_f16_e32 v0, s3978; SI-NEXT: s_mov_b32 s4, s0979; SI-NEXT: s_brev_b32 s0, -2980; SI-NEXT: v_mov_b32_e32 v1, s2981; SI-NEXT: s_mov_b32 s5, s1982; SI-NEXT: v_bfi_b32 v0, s0, v1, v0983; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0984; SI-NEXT: s_endpgm985;986; VI-LABEL: s_test_copysign_f32_fpext_f16:987; VI: ; %bb.0:988; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24989; VI-NEXT: s_brev_b32 s4, -2990; VI-NEXT: s_waitcnt lgkmcnt(0)991; VI-NEXT: v_lshlrev_b32_e64 v0, 16, s3992; VI-NEXT: v_mov_b32_e32 v1, s2993; VI-NEXT: v_bfi_b32 v2, s4, v1, v0994; VI-NEXT: v_mov_b32_e32 v0, s0995; VI-NEXT: v_mov_b32_e32 v1, s1996; VI-NEXT: flat_store_dword v[0:1], v2997; VI-NEXT: s_endpgm998;999; GFX11-LABEL: s_test_copysign_f32_fpext_f16:1000; GFX11: ; %bb.0:1001; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241002; GFX11-NEXT: v_mov_b32_e32 v1, 01003; GFX11-NEXT: s_waitcnt lgkmcnt(0)1004; GFX11-NEXT: v_mov_b16_e32 v0.h, s31005; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1006; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s2, v01007; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]1008; GFX11-NEXT: s_endpgm1009 %sign.ext = fpext half %sign to float1010 %result = call float @llvm.copysign.f32(float %mag, float %sign.ext)1011 store float %result, ptr addrspace(1) %out, align 41012 ret void1013}1014 1015define amdgpu_kernel void @s_test_copysign_f32_1_fpext_f16(ptr addrspace(1) %out, half %sign) {1016; SI-LABEL: s_test_copysign_f32_1_fpext_f16:1017; SI: ; %bb.0:1018; SI-NEXT: s_load_dword s0, s[4:5], 0xb1019; SI-NEXT: s_mov_b32 s3, 0xf0001020; SI-NEXT: s_mov_b32 s2, -11021; SI-NEXT: s_waitcnt lgkmcnt(0)1022; SI-NEXT: v_cvt_f32_f16_e32 v0, s01023; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91024; SI-NEXT: v_and_b32_e32 v0, 0x80000000, v01025; SI-NEXT: v_or_b32_e32 v0, 1.0, v01026; SI-NEXT: s_waitcnt lgkmcnt(0)1027; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01028; SI-NEXT: s_endpgm1029;1030; VI-LABEL: s_test_copysign_f32_1_fpext_f16:1031; VI: ; %bb.0:1032; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1033; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241034; VI-NEXT: s_waitcnt lgkmcnt(0)1035; VI-NEXT: s_lshl_b32 s2, s2, 161036; VI-NEXT: s_and_b32 s2, s2, 0x800000001037; VI-NEXT: s_or_b32 s2, s2, 1.01038; VI-NEXT: v_mov_b32_e32 v0, s01039; VI-NEXT: v_mov_b32_e32 v1, s11040; VI-NEXT: v_mov_b32_e32 v2, s21041; VI-NEXT: flat_store_dword v[0:1], v21042; VI-NEXT: s_endpgm1043;1044; GFX11-LABEL: s_test_copysign_f32_1_fpext_f16:1045; GFX11: ; %bb.0:1046; GFX11-NEXT: s_clause 0x11047; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c1048; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x241049; GFX11-NEXT: s_waitcnt lgkmcnt(0)1050; GFX11-NEXT: s_lshl_b32 s2, s2, 161051; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1052; GFX11-NEXT: s_and_b32 s2, s2, 0x800000001053; GFX11-NEXT: s_or_b32 s2, s2, 1.01054; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1055; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s21056; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1057; GFX11-NEXT: s_endpgm1058 %sign.ext = fpext half %sign to float1059 %result = call float @llvm.copysign.f32(float 1.0, float %sign.ext)1060 store float %result, ptr addrspace(1) %out, align 41061 ret void1062}1063 1064define amdgpu_kernel void @s_test_copysign_f32_fpext_bf16(ptr addrspace(1) %out, float %mag, bfloat %sign) {1065; SI-LABEL: s_test_copysign_f32_fpext_bf16:1066; SI: ; %bb.0:1067; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91068; SI-NEXT: s_mov_b32 s7, 0xf0001069; SI-NEXT: s_mov_b32 s6, -11070; SI-NEXT: s_waitcnt lgkmcnt(0)1071; SI-NEXT: s_mov_b32 s4, s01072; SI-NEXT: s_lshl_b32 s0, s3, 161073; SI-NEXT: s_mov_b32 s5, s11074; SI-NEXT: s_brev_b32 s1, -21075; SI-NEXT: v_mov_b32_e32 v0, s21076; SI-NEXT: v_mov_b32_e32 v1, s01077; SI-NEXT: v_bfi_b32 v0, s1, v0, v11078; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01079; SI-NEXT: s_endpgm1080;1081; VI-LABEL: s_test_copysign_f32_fpext_bf16:1082; VI: ; %bb.0:1083; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241084; VI-NEXT: s_brev_b32 s4, -21085; VI-NEXT: s_waitcnt lgkmcnt(0)1086; VI-NEXT: v_lshlrev_b32_e64 v0, 16, s31087; VI-NEXT: v_mov_b32_e32 v1, s21088; VI-NEXT: v_bfi_b32 v2, s4, v1, v01089; VI-NEXT: v_mov_b32_e32 v0, s01090; VI-NEXT: v_mov_b32_e32 v1, s11091; VI-NEXT: flat_store_dword v[0:1], v21092; VI-NEXT: s_endpgm1093;1094; GFX11-LABEL: s_test_copysign_f32_fpext_bf16:1095; GFX11: ; %bb.0:1096; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241097; GFX11-NEXT: v_mov_b32_e32 v1, 01098; GFX11-NEXT: s_waitcnt lgkmcnt(0)1099; GFX11-NEXT: v_mov_b16_e32 v0.h, s31100; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1101; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, s2, v01102; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]1103; GFX11-NEXT: s_endpgm1104 %sign.ext = fpext bfloat %sign to float1105 %result = call float @llvm.copysign.f32(float %mag, float %sign.ext)1106 store float %result, ptr addrspace(1) %out, align 41107 ret void1108}1109 1110declare float @llvm.copysign.f32(float, float) #01111declare <2 x float> @llvm.copysign.v2f32(<2 x float>, <2 x float>) #01112declare <3 x float> @llvm.copysign.v3f32(<3 x float>, <3 x float>) #01113declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) #01114declare <5 x float> @llvm.copysign.v5f32(<5 x float>, <5 x float>) #01115 1116attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }1117