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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=fiji -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX8 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX9 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX10 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s8 9; Make sure fdiv is promoted to f32.10 11define amdgpu_kernel void @v_fdiv_f16(12; SI-LABEL: v_fdiv_f16:13; SI:       ; %bb.0: ; %entry14; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x915; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd16; SI-NEXT:    s_mov_b32 s7, 0xf00017; SI-NEXT:    s_mov_b32 s6, 018; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v019; SI-NEXT:    s_waitcnt lgkmcnt(0)20; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]21; SI-NEXT:    v_mov_b32_e32 v1, 022; SI-NEXT:    s_mov_b64 s[10:11], s[6:7]23; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc24; SI-NEXT:    s_waitcnt vmcnt(0)25; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc26; SI-NEXT:    s_waitcnt vmcnt(0)27; SI-NEXT:    v_cvt_f32_f16_e32 v2, v228; SI-NEXT:    v_cvt_f32_f16_e32 v3, v329; SI-NEXT:    v_div_scale_f32 v4, s[2:3], v3, v3, v230; SI-NEXT:    v_rcp_f32_e32 v5, v431; SI-NEXT:    v_div_scale_f32 v6, vcc, v2, v3, v232; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 333; SI-NEXT:    v_fma_f32 v7, -v4, v5, 1.034; SI-NEXT:    v_fma_f32 v5, v7, v5, v535; SI-NEXT:    v_mul_f32_e32 v7, v6, v536; SI-NEXT:    v_fma_f32 v8, -v4, v7, v637; SI-NEXT:    v_fma_f32 v7, v8, v5, v738; SI-NEXT:    v_fma_f32 v4, -v4, v7, v639; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 040; SI-NEXT:    v_div_fmas_f32 v4, v4, v5, v741; SI-NEXT:    v_div_fixup_f32 v2, v4, v3, v242; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 043; SI-NEXT:    v_cvt_f16_f32_e32 v2, v244; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]45; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr6446; SI-NEXT:    s_endpgm47;48; GFX8-LABEL: v_fdiv_f16:49; GFX8:       ; %bb.0: ; %entry50; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2451; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x3452; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 1, v053; GFX8-NEXT:    s_waitcnt lgkmcnt(0)54; GFX8-NEXT:    v_mov_b32_e32 v1, s355; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v456; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc57; GFX8-NEXT:    v_mov_b32_e32 v3, s558; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s4, v459; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc60; GFX8-NEXT:    flat_load_ushort v5, v[0:1] glc61; GFX8-NEXT:    s_waitcnt vmcnt(0)62; GFX8-NEXT:    flat_load_ushort v2, v[2:3] glc63; GFX8-NEXT:    s_waitcnt vmcnt(0)64; GFX8-NEXT:    v_mov_b32_e32 v6, s165; GFX8-NEXT:    v_cvt_f32_f16_e32 v1, v566; GFX8-NEXT:    v_cvt_f32_f16_e32 v0, v267; GFX8-NEXT:    v_rcp_f32_e32 v3, v068; GFX8-NEXT:    v_mul_f32_e32 v7, v1, v369; GFX8-NEXT:    v_mad_f32 v8, -v0, v7, v170; GFX8-NEXT:    v_mac_f32_e32 v7, v8, v371; GFX8-NEXT:    v_mad_f32 v0, -v0, v7, v172; GFX8-NEXT:    v_mul_f32_e32 v0, v0, v373; GFX8-NEXT:    v_and_b32_e32 v0, 0xff800000, v074; GFX8-NEXT:    v_add_f32_e32 v0, v0, v775; GFX8-NEXT:    v_cvt_f16_f32_e32 v3, v076; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v477; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v6, vcc78; GFX8-NEXT:    v_div_fixup_f16 v2, v3, v2, v579; GFX8-NEXT:    flat_store_short v[0:1], v280; GFX8-NEXT:    s_endpgm81;82; GFX9-LABEL: v_fdiv_f16:83; GFX9:       ; %bb.0: ; %entry84; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2485; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x3486; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v087; GFX9-NEXT:    s_waitcnt lgkmcnt(0)88; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc89; GFX9-NEXT:    s_waitcnt vmcnt(0)90; GFX9-NEXT:    global_load_ushort v2, v0, s[6:7] glc91; GFX9-NEXT:    s_waitcnt vmcnt(0)92; GFX9-NEXT:    v_cvt_f32_f16_e32 v4, v193; GFX9-NEXT:    v_cvt_f32_f16_e32 v3, v294; GFX9-NEXT:    v_rcp_f32_e32 v3, v395; GFX9-NEXT:    v_mul_f32_e32 v4, v4, v396; GFX9-NEXT:    v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1]97; GFX9-NEXT:    v_mac_f32_e32 v4, v5, v398; GFX9-NEXT:    v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1]99; GFX9-NEXT:    v_mul_f32_e32 v3, v5, v3100; GFX9-NEXT:    v_and_b32_e32 v3, 0xff800000, v3101; GFX9-NEXT:    v_add_f32_e32 v3, v3, v4102; GFX9-NEXT:    v_cvt_f16_f32_e32 v3, v3103; GFX9-NEXT:    v_div_fixup_f16 v1, v3, v2, v1104; GFX9-NEXT:    global_store_short v0, v1, s[0:1]105; GFX9-NEXT:    s_endpgm106;107; GFX10-LABEL: v_fdiv_f16:108; GFX10:       ; %bb.0: ; %entry109; GFX10-NEXT:    s_clause 0x1110; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24111; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34112; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0113; GFX10-NEXT:    s_waitcnt lgkmcnt(0)114; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc115; GFX10-NEXT:    s_waitcnt vmcnt(0)116; GFX10-NEXT:    global_load_ushort v2, v0, s[6:7] glc dlc117; GFX10-NEXT:    s_waitcnt vmcnt(0)118; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v1119; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v2120; GFX10-NEXT:    v_rcp_f32_e32 v4, v3121; GFX10-NEXT:    v_mul_f32_e32 v6, v5, v4122; GFX10-NEXT:    v_mad_f32 v7, -v3, v6, v5123; GFX10-NEXT:    v_mac_f32_e32 v6, v7, v4124; GFX10-NEXT:    v_mad_f32 v3, -v3, v6, v5125; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v4126; GFX10-NEXT:    v_and_b32_e32 v3, 0xff800000, v3127; GFX10-NEXT:    v_add_f32_e32 v3, v3, v6128; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3129; GFX10-NEXT:    v_div_fixup_f16 v1, v3, v2, v1130; GFX10-NEXT:    global_store_short v0, v1, s[0:1]131; GFX10-NEXT:    s_endpgm132;133; GFX11-TRUE16-LABEL: v_fdiv_f16:134; GFX11-TRUE16:       ; %bb.0: ; %entry135; GFX11-TRUE16-NEXT:    s_clause 0x1136; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24137; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34138; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0139; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)140; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0141; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)142; GFX11-TRUE16-NEXT:    global_load_d16_b16 v2, v1, s[2:3] glc dlc143; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)144; GFX11-TRUE16-NEXT:    global_load_d16_b16 v3, v1, s[4:5] glc dlc145; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)146; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v2.l147; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.l148; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)149; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v0, v0150; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)151; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v4, v0152; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]153; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)154; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v4, v5, v0155; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]156; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)157; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v5, v0158; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0159; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)160; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v0, v4161; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0162; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)163; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l164; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]165; GFX11-TRUE16-NEXT:    s_endpgm166;167; GFX11-FAKE16-LABEL: v_fdiv_f16:168; GFX11-FAKE16:       ; %bb.0: ; %entry169; GFX11-FAKE16-NEXT:    s_clause 0x1170; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24171; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34172; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0173; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)174; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0175; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)176; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc177; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)178; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] glc dlc179; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)180; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v1181; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v2182; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)183; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v3, v3184; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)185; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v4, v3186; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1]187; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)188; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v4, v5, v3189; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1]190; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)191; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v5, v3192; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff800000, v3193; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)194; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v3, v4195; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3196; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)197; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v1, v3, v2, v1198; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]199; GFX11-FAKE16-NEXT:    s_endpgm200    ptr addrspace(1) %r,201    ptr addrspace(1) %a,202    ptr addrspace(1) %b) #0 {203entry:204  %tid = call i32 @llvm.amdgcn.workitem.id.x()205  %tid.ext = sext i32 %tid to i64206  %gep.a = getelementptr inbounds half, ptr addrspace(1) %a, i64 %tid.ext207  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext208  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext209  %a.val = load volatile half, ptr addrspace(1) %gep.a210  %b.val = load volatile half, ptr addrspace(1) %gep.b211  %r.val = fdiv half %a.val, %b.val212  store half %r.val, ptr addrspace(1) %gep.r213  ret void214}215 216define amdgpu_kernel void @v_rcp_f16(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {217; SI-LABEL: v_rcp_f16:218; SI:       ; %bb.0: ; %entry219; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9220; SI-NEXT:    s_mov_b32 s7, 0xf000221; SI-NEXT:    s_mov_b32 s6, 0222; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0223; SI-NEXT:    v_mov_b32_e32 v1, 0224; SI-NEXT:    s_waitcnt lgkmcnt(0)225; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]226; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc227; SI-NEXT:    s_waitcnt vmcnt(0)228; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2229; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, 1.0230; SI-NEXT:    v_rcp_f32_e32 v4, v3231; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v2, 1.0232; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3233; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.0234; SI-NEXT:    v_fma_f32 v4, v6, v4, v4235; SI-NEXT:    v_mul_f32_e32 v6, v5, v4236; SI-NEXT:    v_fma_f32 v7, -v3, v6, v5237; SI-NEXT:    v_fma_f32 v6, v7, v4, v6238; SI-NEXT:    v_fma_f32 v3, -v3, v6, v5239; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0240; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v6241; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, 1.0242; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0243; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2244; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]245; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64246; SI-NEXT:    s_endpgm247;248; GFX8-LABEL: v_rcp_f16:249; GFX8:       ; %bb.0: ; %entry250; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24251; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v0252; GFX8-NEXT:    s_waitcnt lgkmcnt(0)253; GFX8-NEXT:    v_mov_b32_e32 v1, s3254; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v2255; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc256; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc257; GFX8-NEXT:    s_waitcnt vmcnt(0)258; GFX8-NEXT:    v_mov_b32_e32 v1, s1259; GFX8-NEXT:    v_rcp_f16_e32 v3, v0260; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v2261; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc262; GFX8-NEXT:    flat_store_short v[0:1], v3263; GFX8-NEXT:    s_endpgm264;265; GFX9-LABEL: v_rcp_f16:266; GFX9:       ; %bb.0: ; %entry267; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24268; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0269; GFX9-NEXT:    s_waitcnt lgkmcnt(0)270; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc271; GFX9-NEXT:    s_waitcnt vmcnt(0)272; GFX9-NEXT:    v_rcp_f16_e32 v1, v1273; GFX9-NEXT:    global_store_short v0, v1, s[0:1]274; GFX9-NEXT:    s_endpgm275;276; GFX10-LABEL: v_rcp_f16:277; GFX10:       ; %bb.0: ; %entry278; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24279; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0280; GFX10-NEXT:    s_waitcnt lgkmcnt(0)281; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc282; GFX10-NEXT:    s_waitcnt vmcnt(0)283; GFX10-NEXT:    v_rcp_f16_e32 v1, v1284; GFX10-NEXT:    global_store_short v0, v1, s[0:1]285; GFX10-NEXT:    s_endpgm286;287; GFX11-TRUE16-LABEL: v_rcp_f16:288; GFX11-TRUE16:       ; %bb.0: ; %entry289; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24290; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0291; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)292; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0293; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)294; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc295; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)296; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l297; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]298; GFX11-TRUE16-NEXT:    s_endpgm299;300; GFX11-FAKE16-LABEL: v_rcp_f16:301; GFX11-FAKE16:       ; %bb.0: ; %entry302; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24303; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0304; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)305; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0306; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)307; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc308; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)309; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v1, v1310; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]311; GFX11-FAKE16-NEXT:    s_endpgm312entry:313  %tid = call i32 @llvm.amdgcn.workitem.id.x()314  %tid.ext = sext i32 %tid to i64315  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext316  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext317  %b.val = load volatile half, ptr addrspace(1) %gep.b318  %r.val = fdiv half 1.0, %b.val319  store half %r.val, ptr addrspace(1) %gep.r320  ret void321}322 323define amdgpu_kernel void @v_rcp_f16_abs(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {324; SI-LABEL: v_rcp_f16_abs:325; SI:       ; %bb.0: ; %entry326; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9327; SI-NEXT:    s_mov_b32 s7, 0xf000328; SI-NEXT:    s_mov_b32 s6, 0329; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0330; SI-NEXT:    v_mov_b32_e32 v1, 0331; SI-NEXT:    s_waitcnt lgkmcnt(0)332; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]333; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc334; SI-NEXT:    s_waitcnt vmcnt(0)335; SI-NEXT:    v_cvt_f32_f16_e64 v2, |v2|336; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, 1.0337; SI-NEXT:    v_rcp_f32_e32 v4, v3338; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v2, 1.0339; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3340; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.0341; SI-NEXT:    v_fma_f32 v4, v6, v4, v4342; SI-NEXT:    v_mul_f32_e32 v6, v5, v4343; SI-NEXT:    v_fma_f32 v7, -v3, v6, v5344; SI-NEXT:    v_fma_f32 v6, v7, v4, v6345; SI-NEXT:    v_fma_f32 v3, -v3, v6, v5346; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0347; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v6348; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, 1.0349; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0350; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2351; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]352; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64353; SI-NEXT:    s_endpgm354;355; GFX8-LABEL: v_rcp_f16_abs:356; GFX8:       ; %bb.0: ; %entry357; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24358; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v0359; GFX8-NEXT:    s_waitcnt lgkmcnt(0)360; GFX8-NEXT:    v_mov_b32_e32 v1, s3361; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v2362; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc363; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc364; GFX8-NEXT:    s_waitcnt vmcnt(0)365; GFX8-NEXT:    v_mov_b32_e32 v1, s1366; GFX8-NEXT:    v_rcp_f16_e64 v3, |v0|367; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v2368; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc369; GFX8-NEXT:    flat_store_short v[0:1], v3370; GFX8-NEXT:    s_endpgm371;372; GFX9-LABEL: v_rcp_f16_abs:373; GFX9:       ; %bb.0: ; %entry374; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24375; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0376; GFX9-NEXT:    s_waitcnt lgkmcnt(0)377; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc378; GFX9-NEXT:    s_waitcnt vmcnt(0)379; GFX9-NEXT:    v_rcp_f16_e64 v1, |v1|380; GFX9-NEXT:    global_store_short v0, v1, s[0:1]381; GFX9-NEXT:    s_endpgm382;383; GFX10-LABEL: v_rcp_f16_abs:384; GFX10:       ; %bb.0: ; %entry385; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24386; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0387; GFX10-NEXT:    s_waitcnt lgkmcnt(0)388; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc389; GFX10-NEXT:    s_waitcnt vmcnt(0)390; GFX10-NEXT:    v_rcp_f16_e64 v1, |v1|391; GFX10-NEXT:    global_store_short v0, v1, s[0:1]392; GFX10-NEXT:    s_endpgm393;394; GFX11-TRUE16-LABEL: v_rcp_f16_abs:395; GFX11-TRUE16:       ; %bb.0: ; %entry396; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24397; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0398; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)399; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0400; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)401; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc402; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)403; GFX11-TRUE16-NEXT:    v_rcp_f16_e64 v0.l, |v0.l|404; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]405; GFX11-TRUE16-NEXT:    s_endpgm406;407; GFX11-FAKE16-LABEL: v_rcp_f16_abs:408; GFX11-FAKE16:       ; %bb.0: ; %entry409; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24410; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0411; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)412; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0413; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)414; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc415; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)416; GFX11-FAKE16-NEXT:    v_rcp_f16_e64 v1, |v1|417; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]418; GFX11-FAKE16-NEXT:    s_endpgm419entry:420  %tid = call i32 @llvm.amdgcn.workitem.id.x()421  %tid.ext = sext i32 %tid to i64422  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext423  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext424  %b.val = load volatile half, ptr addrspace(1) %gep.b425  %b.abs = call half @llvm.fabs.f16(half %b.val)426  %r.val = fdiv half 1.0, %b.abs427  store half %r.val, ptr addrspace(1) %gep.r428  ret void429}430 431; We could not do 1/b -> rcp_f32(b) under !fpmath < 1ulp.432 433define amdgpu_kernel void @reciprocal_f16_rounded(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {434; SI-LABEL: reciprocal_f16_rounded:435; SI:       ; %bb.0: ; %entry436; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9437; SI-NEXT:    s_mov_b32 s7, 0xf000438; SI-NEXT:    s_mov_b32 s6, 0439; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0440; SI-NEXT:    v_mov_b32_e32 v1, 0441; SI-NEXT:    s_waitcnt lgkmcnt(0)442; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]443; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc444; SI-NEXT:    s_waitcnt vmcnt(0)445; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2446; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, 1.0447; SI-NEXT:    v_rcp_f32_e32 v4, v3448; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v2, 1.0449; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3450; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.0451; SI-NEXT:    v_fma_f32 v4, v6, v4, v4452; SI-NEXT:    v_mul_f32_e32 v6, v5, v4453; SI-NEXT:    v_fma_f32 v7, -v3, v6, v5454; SI-NEXT:    v_fma_f32 v6, v7, v4, v6455; SI-NEXT:    v_fma_f32 v3, -v3, v6, v5456; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0457; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v6458; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, 1.0459; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0460; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2461; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]462; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64463; SI-NEXT:    s_endpgm464;465; GFX8-LABEL: reciprocal_f16_rounded:466; GFX8:       ; %bb.0: ; %entry467; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24468; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v0469; GFX8-NEXT:    s_waitcnt lgkmcnt(0)470; GFX8-NEXT:    v_mov_b32_e32 v1, s3471; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v2472; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc473; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc474; GFX8-NEXT:    s_waitcnt vmcnt(0)475; GFX8-NEXT:    v_mov_b32_e32 v1, s1476; GFX8-NEXT:    v_rcp_f16_e32 v3, v0477; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v2478; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc479; GFX8-NEXT:    flat_store_short v[0:1], v3480; GFX8-NEXT:    s_endpgm481;482; GFX9-LABEL: reciprocal_f16_rounded:483; GFX9:       ; %bb.0: ; %entry484; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24485; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0486; GFX9-NEXT:    s_waitcnt lgkmcnt(0)487; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc488; GFX9-NEXT:    s_waitcnt vmcnt(0)489; GFX9-NEXT:    v_rcp_f16_e32 v1, v1490; GFX9-NEXT:    global_store_short v0, v1, s[0:1]491; GFX9-NEXT:    s_endpgm492;493; GFX10-LABEL: reciprocal_f16_rounded:494; GFX10:       ; %bb.0: ; %entry495; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24496; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0497; GFX10-NEXT:    s_waitcnt lgkmcnt(0)498; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc499; GFX10-NEXT:    s_waitcnt vmcnt(0)500; GFX10-NEXT:    v_rcp_f16_e32 v1, v1501; GFX10-NEXT:    global_store_short v0, v1, s[0:1]502; GFX10-NEXT:    s_endpgm503;504; GFX11-TRUE16-LABEL: reciprocal_f16_rounded:505; GFX11-TRUE16:       ; %bb.0: ; %entry506; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24507; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0508; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)509; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0510; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)511; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc512; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)513; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l514; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]515; GFX11-TRUE16-NEXT:    s_endpgm516;517; GFX11-FAKE16-LABEL: reciprocal_f16_rounded:518; GFX11-FAKE16:       ; %bb.0: ; %entry519; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24520; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0521; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)522; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0523; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)524; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc525; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)526; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v1, v1527; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]528; GFX11-FAKE16-NEXT:    s_endpgm529entry:530  %tid = call i32 @llvm.amdgcn.workitem.id.x()531  %tid.ext = sext i32 %tid to i64532  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext533  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext534  %b.val = load volatile half, ptr addrspace(1) %gep.b535  %r.val = fdiv half 1.0, %b.val536  store half %r.val, ptr addrspace(1) %gep.r537  ret void538}539 540define amdgpu_kernel void @v_rcp_f16_afn(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {541; SI-LABEL: v_rcp_f16_afn:542; SI:       ; %bb.0: ; %entry543; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9544; SI-NEXT:    s_mov_b32 s7, 0xf000545; SI-NEXT:    s_mov_b32 s6, 0546; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0547; SI-NEXT:    v_mov_b32_e32 v1, 0548; SI-NEXT:    s_waitcnt lgkmcnt(0)549; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]550; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc551; SI-NEXT:    s_waitcnt vmcnt(0)552; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]553; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2554; SI-NEXT:    v_rcp_f32_e32 v2, v2555; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2556; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64557; SI-NEXT:    s_endpgm558;559; GFX8-LABEL: v_rcp_f16_afn:560; GFX8:       ; %bb.0: ; %entry561; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24562; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v0563; GFX8-NEXT:    s_waitcnt lgkmcnt(0)564; GFX8-NEXT:    v_mov_b32_e32 v1, s3565; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v2566; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc567; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc568; GFX8-NEXT:    s_waitcnt vmcnt(0)569; GFX8-NEXT:    v_mov_b32_e32 v1, s1570; GFX8-NEXT:    v_rcp_f16_e32 v3, v0571; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v2572; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc573; GFX8-NEXT:    flat_store_short v[0:1], v3574; GFX8-NEXT:    s_endpgm575;576; GFX9-LABEL: v_rcp_f16_afn:577; GFX9:       ; %bb.0: ; %entry578; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24579; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0580; GFX9-NEXT:    s_waitcnt lgkmcnt(0)581; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc582; GFX9-NEXT:    s_waitcnt vmcnt(0)583; GFX9-NEXT:    v_rcp_f16_e32 v1, v1584; GFX9-NEXT:    global_store_short v0, v1, s[0:1]585; GFX9-NEXT:    s_endpgm586;587; GFX10-LABEL: v_rcp_f16_afn:588; GFX10:       ; %bb.0: ; %entry589; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24590; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0591; GFX10-NEXT:    s_waitcnt lgkmcnt(0)592; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc593; GFX10-NEXT:    s_waitcnt vmcnt(0)594; GFX10-NEXT:    v_rcp_f16_e32 v1, v1595; GFX10-NEXT:    global_store_short v0, v1, s[0:1]596; GFX10-NEXT:    s_endpgm597;598; GFX11-TRUE16-LABEL: v_rcp_f16_afn:599; GFX11-TRUE16:       ; %bb.0: ; %entry600; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24601; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0602; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)603; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0604; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)605; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc606; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)607; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l608; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]609; GFX11-TRUE16-NEXT:    s_endpgm610;611; GFX11-FAKE16-LABEL: v_rcp_f16_afn:612; GFX11-FAKE16:       ; %bb.0: ; %entry613; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24614; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0615; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)616; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0617; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)618; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc619; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)620; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v1, v1621; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]622; GFX11-FAKE16-NEXT:    s_endpgm623entry:624  %tid = call i32 @llvm.amdgcn.workitem.id.x()625  %tid.ext = sext i32 %tid to i64626  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext627  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext628  %b.val = load volatile half, ptr addrspace(1) %gep.b629  %r.val = fdiv afn half 1.0, %b.val630  store half %r.val, ptr addrspace(1) %gep.r631  ret void632}633 634define amdgpu_kernel void @v_rcp_f16_neg(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {635; SI-LABEL: v_rcp_f16_neg:636; SI:       ; %bb.0: ; %entry637; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9638; SI-NEXT:    s_mov_b32 s7, 0xf000639; SI-NEXT:    s_mov_b32 s6, 0640; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0641; SI-NEXT:    v_mov_b32_e32 v1, 0642; SI-NEXT:    s_waitcnt lgkmcnt(0)643; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]644; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc645; SI-NEXT:    s_waitcnt vmcnt(0)646; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2647; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, -1.0648; SI-NEXT:    v_rcp_f32_e32 v4, v3649; SI-NEXT:    v_div_scale_f32 v5, vcc, -1.0, v2, -1.0650; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3651; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.0652; SI-NEXT:    v_fma_f32 v4, v6, v4, v4653; SI-NEXT:    v_mul_f32_e32 v6, v5, v4654; SI-NEXT:    v_fma_f32 v7, -v3, v6, v5655; SI-NEXT:    v_fma_f32 v6, v7, v4, v6656; SI-NEXT:    v_fma_f32 v3, -v3, v6, v5657; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0658; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v6659; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, -1.0660; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0661; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2662; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]663; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64664; SI-NEXT:    s_endpgm665;666; GFX8-LABEL: v_rcp_f16_neg:667; GFX8:       ; %bb.0: ; %entry668; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24669; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v0670; GFX8-NEXT:    s_waitcnt lgkmcnt(0)671; GFX8-NEXT:    v_mov_b32_e32 v1, s3672; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v2673; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc674; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc675; GFX8-NEXT:    s_waitcnt vmcnt(0)676; GFX8-NEXT:    v_mov_b32_e32 v1, s1677; GFX8-NEXT:    v_rcp_f16_e64 v3, -v0678; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v2679; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc680; GFX8-NEXT:    flat_store_short v[0:1], v3681; GFX8-NEXT:    s_endpgm682;683; GFX9-LABEL: v_rcp_f16_neg:684; GFX9:       ; %bb.0: ; %entry685; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24686; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0687; GFX9-NEXT:    s_waitcnt lgkmcnt(0)688; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc689; GFX9-NEXT:    s_waitcnt vmcnt(0)690; GFX9-NEXT:    v_rcp_f16_e64 v1, -v1691; GFX9-NEXT:    global_store_short v0, v1, s[0:1]692; GFX9-NEXT:    s_endpgm693;694; GFX10-LABEL: v_rcp_f16_neg:695; GFX10:       ; %bb.0: ; %entry696; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24697; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0698; GFX10-NEXT:    s_waitcnt lgkmcnt(0)699; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc700; GFX10-NEXT:    s_waitcnt vmcnt(0)701; GFX10-NEXT:    v_rcp_f16_e64 v1, -v1702; GFX10-NEXT:    global_store_short v0, v1, s[0:1]703; GFX10-NEXT:    s_endpgm704;705; GFX11-TRUE16-LABEL: v_rcp_f16_neg:706; GFX11-TRUE16:       ; %bb.0: ; %entry707; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24708; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0709; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)710; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0711; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)712; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc713; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)714; GFX11-TRUE16-NEXT:    v_rcp_f16_e64 v0.l, -v0.l715; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]716; GFX11-TRUE16-NEXT:    s_endpgm717;718; GFX11-FAKE16-LABEL: v_rcp_f16_neg:719; GFX11-FAKE16:       ; %bb.0: ; %entry720; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24721; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0722; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)723; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0724; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)725; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc726; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)727; GFX11-FAKE16-NEXT:    v_rcp_f16_e64 v1, -v1728; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]729; GFX11-FAKE16-NEXT:    s_endpgm730entry:731  %tid = call i32 @llvm.amdgcn.workitem.id.x()732  %tid.ext = sext i32 %tid to i64733  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext734  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext735  %b.val = load volatile half, ptr addrspace(1) %gep.b736  %r.val = fdiv half -1.0, %b.val737  store half %r.val, ptr addrspace(1) %gep.r738  ret void739}740 741define amdgpu_kernel void @v_rsq_f16(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {742; SI-LABEL: v_rsq_f16:743; SI:       ; %bb.0: ; %entry744; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9745; SI-NEXT:    s_mov_b32 s7, 0xf000746; SI-NEXT:    s_mov_b32 s6, 0747; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0748; SI-NEXT:    v_mov_b32_e32 v1, 0749; SI-NEXT:    s_waitcnt lgkmcnt(0)750; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]751; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc752; SI-NEXT:    s_waitcnt vmcnt(0)753; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2754; SI-NEXT:    v_sqrt_f32_e32 v2, v2755; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0756; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2757; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2758; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, 1.0759; SI-NEXT:    v_rcp_f32_e32 v4, v3760; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v2, 1.0761; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3762; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.0763; SI-NEXT:    v_fma_f32 v4, v6, v4, v4764; SI-NEXT:    v_mul_f32_e32 v6, v5, v4765; SI-NEXT:    v_fma_f32 v7, -v3, v6, v5766; SI-NEXT:    v_fma_f32 v6, v7, v4, v6767; SI-NEXT:    v_fma_f32 v3, -v3, v6, v5768; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0769; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v6770; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, 1.0771; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2772; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]773; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64774; SI-NEXT:    s_endpgm775;776; GFX8-LABEL: v_rsq_f16:777; GFX8:       ; %bb.0: ; %entry778; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24779; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v0780; GFX8-NEXT:    s_waitcnt lgkmcnt(0)781; GFX8-NEXT:    v_mov_b32_e32 v1, s3782; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v2783; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc784; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc785; GFX8-NEXT:    s_waitcnt vmcnt(0)786; GFX8-NEXT:    v_mov_b32_e32 v1, s1787; GFX8-NEXT:    v_rsq_f16_e32 v3, v0788; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v2789; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc790; GFX8-NEXT:    flat_store_short v[0:1], v3791; GFX8-NEXT:    s_endpgm792;793; GFX9-LABEL: v_rsq_f16:794; GFX9:       ; %bb.0: ; %entry795; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24796; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0797; GFX9-NEXT:    s_waitcnt lgkmcnt(0)798; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc799; GFX9-NEXT:    s_waitcnt vmcnt(0)800; GFX9-NEXT:    v_rsq_f16_e32 v1, v1801; GFX9-NEXT:    global_store_short v0, v1, s[0:1]802; GFX9-NEXT:    s_endpgm803;804; GFX10-LABEL: v_rsq_f16:805; GFX10:       ; %bb.0: ; %entry806; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24807; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0808; GFX10-NEXT:    s_waitcnt lgkmcnt(0)809; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc810; GFX10-NEXT:    s_waitcnt vmcnt(0)811; GFX10-NEXT:    v_rsq_f16_e32 v1, v1812; GFX10-NEXT:    global_store_short v0, v1, s[0:1]813; GFX10-NEXT:    s_endpgm814;815; GFX11-TRUE16-LABEL: v_rsq_f16:816; GFX11-TRUE16:       ; %bb.0: ; %entry817; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24818; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0819; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)820; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0821; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)822; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc823; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)824; GFX11-TRUE16-NEXT:    v_rsq_f16_e32 v0.l, v0.l825; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]826; GFX11-TRUE16-NEXT:    s_endpgm827;828; GFX11-FAKE16-LABEL: v_rsq_f16:829; GFX11-FAKE16:       ; %bb.0: ; %entry830; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24831; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0832; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)833; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0834; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)835; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc836; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)837; GFX11-FAKE16-NEXT:    v_rsq_f16_e32 v1, v1838; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]839; GFX11-FAKE16-NEXT:    s_endpgm840entry:841  %tid = call i32 @llvm.amdgcn.workitem.id.x()842  %tid.ext = sext i32 %tid to i64843  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext844  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext845  %b.val = load volatile half, ptr addrspace(1) %gep.b846  %b.sqrt = call contract half @llvm.sqrt.f16(half %b.val)847  %r.val = fdiv contract half 1.0, %b.sqrt848  store half %r.val, ptr addrspace(1) %gep.r849  ret void850}851 852define amdgpu_kernel void @v_rsq_f16_neg(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {853; SI-LABEL: v_rsq_f16_neg:854; SI:       ; %bb.0: ; %entry855; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9856; SI-NEXT:    s_mov_b32 s7, 0xf000857; SI-NEXT:    s_mov_b32 s6, 0858; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0859; SI-NEXT:    v_mov_b32_e32 v1, 0860; SI-NEXT:    s_waitcnt lgkmcnt(0)861; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]862; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc863; SI-NEXT:    s_waitcnt vmcnt(0)864; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2865; SI-NEXT:    v_sqrt_f32_e32 v2, v2866; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0867; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2868; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2869; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, -1.0870; SI-NEXT:    v_rcp_f32_e32 v4, v3871; SI-NEXT:    v_div_scale_f32 v5, vcc, -1.0, v2, -1.0872; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3873; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.0874; SI-NEXT:    v_fma_f32 v4, v6, v4, v4875; SI-NEXT:    v_mul_f32_e32 v6, v5, v4876; SI-NEXT:    v_fma_f32 v7, -v3, v6, v5877; SI-NEXT:    v_fma_f32 v6, v7, v4, v6878; SI-NEXT:    v_fma_f32 v3, -v3, v6, v5879; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0880; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v6881; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, -1.0882; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2883; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]884; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr64885; SI-NEXT:    s_endpgm886;887; GFX8-LABEL: v_rsq_f16_neg:888; GFX8:       ; %bb.0: ; %entry889; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24890; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v0891; GFX8-NEXT:    s_waitcnt lgkmcnt(0)892; GFX8-NEXT:    v_mov_b32_e32 v1, s3893; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v2894; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc895; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc896; GFX8-NEXT:    s_waitcnt vmcnt(0)897; GFX8-NEXT:    v_mov_b32_e32 v1, s1898; GFX8-NEXT:    v_rsq_f16_e32 v3, v0899; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v2900; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc901; GFX8-NEXT:    v_xor_b32_e32 v2, 0x8000, v3902; GFX8-NEXT:    flat_store_short v[0:1], v2903; GFX8-NEXT:    s_endpgm904;905; GFX9-LABEL: v_rsq_f16_neg:906; GFX9:       ; %bb.0: ; %entry907; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24908; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v0909; GFX9-NEXT:    s_waitcnt lgkmcnt(0)910; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc911; GFX9-NEXT:    s_waitcnt vmcnt(0)912; GFX9-NEXT:    v_rsq_f16_e32 v1, v1913; GFX9-NEXT:    v_xor_b32_e32 v1, 0x8000, v1914; GFX9-NEXT:    global_store_short v0, v1, s[0:1]915; GFX9-NEXT:    s_endpgm916;917; GFX10-LABEL: v_rsq_f16_neg:918; GFX10:       ; %bb.0: ; %entry919; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24920; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0921; GFX10-NEXT:    s_waitcnt lgkmcnt(0)922; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc923; GFX10-NEXT:    s_waitcnt vmcnt(0)924; GFX10-NEXT:    v_rsq_f16_e32 v1, v1925; GFX10-NEXT:    v_xor_b32_e32 v1, 0x8000, v1926; GFX10-NEXT:    global_store_short v0, v1, s[0:1]927; GFX10-NEXT:    s_endpgm928;929; GFX11-TRUE16-LABEL: v_rsq_f16_neg:930; GFX11-TRUE16:       ; %bb.0: ; %entry931; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24932; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0933; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)934; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v0935; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)936; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc937; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)938; GFX11-TRUE16-NEXT:    v_rsq_f16_e32 v0.l, v0.l939; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)940; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l941; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]942; GFX11-TRUE16-NEXT:    s_endpgm943;944; GFX11-FAKE16-LABEL: v_rsq_f16_neg:945; GFX11-FAKE16:       ; %bb.0: ; %entry946; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24947; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0948; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)949; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v0950; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)951; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc952; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)953; GFX11-FAKE16-NEXT:    v_rsq_f16_e32 v1, v1954; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)955; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v1, 0x8000, v1956; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]957; GFX11-FAKE16-NEXT:    s_endpgm958entry:959  %tid = call i32 @llvm.amdgcn.workitem.id.x()960  %tid.ext = sext i32 %tid to i64961  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext962  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext963  %b.val = load volatile half, ptr addrspace(1) %gep.b964  %b.sqrt = call contract half @llvm.sqrt.f16(half %b.val)965  %r.val = fdiv contract half -1.0, %b.sqrt966  store half %r.val, ptr addrspace(1) %gep.r967  ret void968}969 970define amdgpu_kernel void @v_rsq_f16_multi_use(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {971; SI-LABEL: v_rsq_f16_multi_use:972; SI:       ; %bb.0: ; %entry973; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9974; SI-NEXT:    s_mov_b32 s7, 0xf000975; SI-NEXT:    s_mov_b32 s6, 0976; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v0977; SI-NEXT:    v_mov_b32_e32 v1, 0978; SI-NEXT:    s_waitcnt lgkmcnt(0)979; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]980; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc981; SI-NEXT:    s_waitcnt vmcnt(0)982; SI-NEXT:    v_cvt_f32_f16_e32 v3, v2983; SI-NEXT:    v_sqrt_f32_e32 v3, v3984; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0985; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3986; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3987; SI-NEXT:    v_div_scale_f32 v4, s[2:3], v3, v3, 1.0988; SI-NEXT:    v_rcp_f32_e32 v5, v4989; SI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0990; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3991; SI-NEXT:    v_fma_f32 v7, -v4, v5, 1.0992; SI-NEXT:    v_fma_f32 v5, v7, v5, v5993; SI-NEXT:    v_mul_f32_e32 v7, v6, v5994; SI-NEXT:    v_fma_f32 v8, -v4, v7, v6995; SI-NEXT:    v_fma_f32 v7, v8, v5, v7996; SI-NEXT:    v_fma_f32 v4, -v4, v7, v6997; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0998; SI-NEXT:    v_div_fmas_f32 v4, v4, v5, v7999; SI-NEXT:    v_div_fixup_f32 v3, v4, v3, 1.01000; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31001; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1002; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr641003; SI-NEXT:    s_waitcnt vmcnt(0)1004; SI-NEXT:    buffer_store_short v3, v[0:1], s[0:3], 0 addr641005; SI-NEXT:    s_endpgm1006;1007; GFX8-LABEL: v_rsq_f16_multi_use:1008; GFX8:       ; %bb.0: ; %entry1009; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241010; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v01011; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1012; GFX8-NEXT:    v_mov_b32_e32 v1, s31013; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v21014; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1015; GFX8-NEXT:    flat_load_ushort v3, v[0:1] glc1016; GFX8-NEXT:    s_waitcnt vmcnt(0)1017; GFX8-NEXT:    v_mov_b32_e32 v1, s11018; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v21019; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1020; GFX8-NEXT:    v_rsq_f16_e32 v4, v31021; GFX8-NEXT:    flat_store_short v[0:1], v31022; GFX8-NEXT:    s_waitcnt vmcnt(0)1023; GFX8-NEXT:    flat_store_short v[0:1], v41024; GFX8-NEXT:    s_endpgm1025;1026; GFX9-LABEL: v_rsq_f16_multi_use:1027; GFX9:       ; %bb.0: ; %entry1028; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241029; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v01030; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1031; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc1032; GFX9-NEXT:    s_waitcnt vmcnt(0)1033; GFX9-NEXT:    v_rsq_f16_e32 v2, v11034; GFX9-NEXT:    global_store_short v0, v1, s[0:1]1035; GFX9-NEXT:    s_waitcnt vmcnt(0)1036; GFX9-NEXT:    global_store_short v0, v2, s[0:1]1037; GFX9-NEXT:    s_endpgm1038;1039; GFX10-LABEL: v_rsq_f16_multi_use:1040; GFX10:       ; %bb.0: ; %entry1041; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241042; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v01043; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1044; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc1045; GFX10-NEXT:    s_waitcnt vmcnt(0)1046; GFX10-NEXT:    v_rsq_f16_e32 v2, v11047; GFX10-NEXT:    global_store_short v0, v1, s[0:1]1048; GFX10-NEXT:    s_waitcnt_vscnt null, 0x01049; GFX10-NEXT:    global_store_short v0, v2, s[0:1]1050; GFX10-NEXT:    s_endpgm1051;1052; GFX11-TRUE16-LABEL: v_rsq_f16_multi_use:1053; GFX11-TRUE16:       ; %bb.0: ; %entry1054; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241055; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01056; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1057; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v01058; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1059; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc1060; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1061; GFX11-TRUE16-NEXT:    v_rsq_f16_e32 v0.h, v0.l1062; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1] dlc1063; GFX11-TRUE16-NEXT:    s_waitcnt_vscnt null, 0x01064; GFX11-TRUE16-NEXT:    global_store_d16_hi_b16 v1, v0, s[0:1]1065; GFX11-TRUE16-NEXT:    s_endpgm1066;1067; GFX11-FAKE16-LABEL: v_rsq_f16_multi_use:1068; GFX11-FAKE16:       ; %bb.0: ; %entry1069; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241070; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01071; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1072; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v01073; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1074; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc1075; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1076; GFX11-FAKE16-NEXT:    v_rsq_f16_e32 v2, v11077; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1] dlc1078; GFX11-FAKE16-NEXT:    s_waitcnt_vscnt null, 0x01079; GFX11-FAKE16-NEXT:    global_store_b16 v0, v2, s[0:1]1080; GFX11-FAKE16-NEXT:    s_endpgm1081entry:1082  %tid = call i32 @llvm.amdgcn.workitem.id.x()1083  %tid.ext = sext i32 %tid to i641084  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext1085  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext1086  %b.val = load volatile half, ptr addrspace(1) %gep.b1087  store volatile half %b.val, ptr addrspace(1) %gep.r1088  %b.sqrt = call contract half @llvm.sqrt.f16(half %b.val)1089  %r.val = fdiv contract half 1.0, %b.sqrt1090  store half %r.val, ptr addrspace(1) %gep.r1091  ret void1092}1093 1094define amdgpu_kernel void @v_rsq_f16_missing_contract0(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {1095; SI-LABEL: v_rsq_f16_missing_contract0:1096; SI:       ; %bb.0: ; %entry1097; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91098; SI-NEXT:    s_mov_b32 s7, 0xf0001099; SI-NEXT:    s_mov_b32 s6, 01100; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v01101; SI-NEXT:    v_mov_b32_e32 v1, 01102; SI-NEXT:    s_waitcnt lgkmcnt(0)1103; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1104; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc1105; SI-NEXT:    s_waitcnt vmcnt(0)1106; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21107; SI-NEXT:    v_sqrt_f32_e32 v2, v21108; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 01109; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21110; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21111; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, 1.01112; SI-NEXT:    v_rcp_f32_e32 v4, v31113; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v2, 1.01114; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31115; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.01116; SI-NEXT:    v_fma_f32 v4, v6, v4, v41117; SI-NEXT:    v_mul_f32_e32 v6, v5, v41118; SI-NEXT:    v_fma_f32 v7, -v3, v6, v51119; SI-NEXT:    v_fma_f32 v6, v7, v4, v61120; SI-NEXT:    v_fma_f32 v3, -v3, v6, v51121; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01122; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v61123; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, 1.01124; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21125; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1126; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr641127; SI-NEXT:    s_endpgm1128;1129; GFX8-LABEL: v_rsq_f16_missing_contract0:1130; GFX8:       ; %bb.0: ; %entry1131; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241132; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v01133; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1134; GFX8-NEXT:    v_mov_b32_e32 v1, s31135; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v21136; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1137; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc1138; GFX8-NEXT:    s_waitcnt vmcnt(0)1139; GFX8-NEXT:    v_mov_b32_e32 v1, s11140; GFX8-NEXT:    v_sqrt_f16_e32 v0, v01141; GFX8-NEXT:    v_rcp_f16_e32 v3, v01142; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v21143; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1144; GFX8-NEXT:    flat_store_short v[0:1], v31145; GFX8-NEXT:    s_endpgm1146;1147; GFX9-LABEL: v_rsq_f16_missing_contract0:1148; GFX9:       ; %bb.0: ; %entry1149; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241150; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v01151; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1152; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc1153; GFX9-NEXT:    s_waitcnt vmcnt(0)1154; GFX9-NEXT:    v_sqrt_f16_e32 v1, v11155; GFX9-NEXT:    v_rcp_f16_e32 v1, v11156; GFX9-NEXT:    global_store_short v0, v1, s[0:1]1157; GFX9-NEXT:    s_endpgm1158;1159; GFX10-LABEL: v_rsq_f16_missing_contract0:1160; GFX10:       ; %bb.0: ; %entry1161; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241162; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v01163; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1164; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc1165; GFX10-NEXT:    s_waitcnt vmcnt(0)1166; GFX10-NEXT:    v_sqrt_f16_e32 v1, v11167; GFX10-NEXT:    v_rcp_f16_e32 v1, v11168; GFX10-NEXT:    global_store_short v0, v1, s[0:1]1169; GFX10-NEXT:    s_endpgm1170;1171; GFX11-TRUE16-LABEL: v_rsq_f16_missing_contract0:1172; GFX11-TRUE16:       ; %bb.0: ; %entry1173; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241174; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01175; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1176; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v01177; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1178; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc1179; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1180; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l1181; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1182; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l1183; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1184; GFX11-TRUE16-NEXT:    s_endpgm1185;1186; GFX11-FAKE16-LABEL: v_rsq_f16_missing_contract0:1187; GFX11-FAKE16:       ; %bb.0: ; %entry1188; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241189; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01190; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1191; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v01192; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1193; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc1194; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1195; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v1, v11196; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1197; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v1, v11198; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]1199; GFX11-FAKE16-NEXT:    s_endpgm1200entry:1201  %tid = call i32 @llvm.amdgcn.workitem.id.x()1202  %tid.ext = sext i32 %tid to i641203  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext1204  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext1205  %b.val = load volatile half, ptr addrspace(1) %gep.b1206  %b.sqrt = call half @llvm.sqrt.f16(half %b.val)1207  %r.val = fdiv contract half 1.0, %b.sqrt1208  store half %r.val, ptr addrspace(1) %gep.r1209  ret void1210}1211 1212define amdgpu_kernel void @v_rsq_f16_missing_contract1(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {1213; SI-LABEL: v_rsq_f16_missing_contract1:1214; SI:       ; %bb.0: ; %entry1215; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91216; SI-NEXT:    s_mov_b32 s7, 0xf0001217; SI-NEXT:    s_mov_b32 s6, 01218; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v01219; SI-NEXT:    v_mov_b32_e32 v1, 01220; SI-NEXT:    s_waitcnt lgkmcnt(0)1221; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1222; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc1223; SI-NEXT:    s_waitcnt vmcnt(0)1224; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21225; SI-NEXT:    v_sqrt_f32_e32 v2, v21226; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 01227; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21228; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21229; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, 1.01230; SI-NEXT:    v_rcp_f32_e32 v4, v31231; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v2, 1.01232; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31233; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.01234; SI-NEXT:    v_fma_f32 v4, v6, v4, v41235; SI-NEXT:    v_mul_f32_e32 v6, v5, v41236; SI-NEXT:    v_fma_f32 v7, -v3, v6, v51237; SI-NEXT:    v_fma_f32 v6, v7, v4, v61238; SI-NEXT:    v_fma_f32 v3, -v3, v6, v51239; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01240; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v61241; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, 1.01242; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21243; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1244; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr641245; SI-NEXT:    s_endpgm1246;1247; GFX8-LABEL: v_rsq_f16_missing_contract1:1248; GFX8:       ; %bb.0: ; %entry1249; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241250; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v01251; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1252; GFX8-NEXT:    v_mov_b32_e32 v1, s31253; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v21254; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1255; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc1256; GFX8-NEXT:    s_waitcnt vmcnt(0)1257; GFX8-NEXT:    v_mov_b32_e32 v1, s11258; GFX8-NEXT:    v_sqrt_f16_e32 v0, v01259; GFX8-NEXT:    v_rcp_f16_e32 v3, v01260; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v21261; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1262; GFX8-NEXT:    flat_store_short v[0:1], v31263; GFX8-NEXT:    s_endpgm1264;1265; GFX9-LABEL: v_rsq_f16_missing_contract1:1266; GFX9:       ; %bb.0: ; %entry1267; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241268; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v01269; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1270; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc1271; GFX9-NEXT:    s_waitcnt vmcnt(0)1272; GFX9-NEXT:    v_sqrt_f16_e32 v1, v11273; GFX9-NEXT:    v_rcp_f16_e32 v1, v11274; GFX9-NEXT:    global_store_short v0, v1, s[0:1]1275; GFX9-NEXT:    s_endpgm1276;1277; GFX10-LABEL: v_rsq_f16_missing_contract1:1278; GFX10:       ; %bb.0: ; %entry1279; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241280; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v01281; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1282; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc1283; GFX10-NEXT:    s_waitcnt vmcnt(0)1284; GFX10-NEXT:    v_sqrt_f16_e32 v1, v11285; GFX10-NEXT:    v_rcp_f16_e32 v1, v11286; GFX10-NEXT:    global_store_short v0, v1, s[0:1]1287; GFX10-NEXT:    s_endpgm1288;1289; GFX11-TRUE16-LABEL: v_rsq_f16_missing_contract1:1290; GFX11-TRUE16:       ; %bb.0: ; %entry1291; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241292; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01293; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1294; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v01295; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1296; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc1297; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1298; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l1299; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1300; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v0.l, v0.l1301; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1302; GFX11-TRUE16-NEXT:    s_endpgm1303;1304; GFX11-FAKE16-LABEL: v_rsq_f16_missing_contract1:1305; GFX11-FAKE16:       ; %bb.0: ; %entry1306; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241307; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01308; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1309; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v01310; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1311; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc1312; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1313; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v1, v11314; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1315; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v1, v11316; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]1317; GFX11-FAKE16-NEXT:    s_endpgm1318entry:1319  %tid = call i32 @llvm.amdgcn.workitem.id.x()1320  %tid.ext = sext i32 %tid to i641321  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext1322  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext1323  %b.val = load volatile half, ptr addrspace(1) %gep.b1324  %b.sqrt = call contract half @llvm.sqrt.f16(half %b.val)1325  %r.val = fdiv half 1.0, %b.sqrt1326  store half %r.val, ptr addrspace(1) %gep.r1327  ret void1328}1329 1330define amdgpu_kernel void @v_neg_rsq_f16_missing_contract1(ptr addrspace(1) %r, ptr addrspace(1) %b) #0 {1331; SI-LABEL: v_neg_rsq_f16_missing_contract1:1332; SI:       ; %bb.0: ; %entry1333; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91334; SI-NEXT:    s_mov_b32 s7, 0xf0001335; SI-NEXT:    s_mov_b32 s6, 01336; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v01337; SI-NEXT:    v_mov_b32_e32 v1, 01338; SI-NEXT:    s_waitcnt lgkmcnt(0)1339; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1340; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc1341; SI-NEXT:    s_waitcnt vmcnt(0)1342; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21343; SI-NEXT:    v_sqrt_f32_e32 v2, v21344; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 01345; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21346; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21347; SI-NEXT:    v_div_scale_f32 v3, s[2:3], v2, v2, -1.01348; SI-NEXT:    v_rcp_f32_e32 v4, v31349; SI-NEXT:    v_div_scale_f32 v5, vcc, -1.0, v2, -1.01350; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31351; SI-NEXT:    v_fma_f32 v6, -v3, v4, 1.01352; SI-NEXT:    v_fma_f32 v4, v6, v4, v41353; SI-NEXT:    v_mul_f32_e32 v6, v5, v41354; SI-NEXT:    v_fma_f32 v7, -v3, v6, v51355; SI-NEXT:    v_fma_f32 v6, v7, v4, v61356; SI-NEXT:    v_fma_f32 v3, -v3, v6, v51357; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01358; SI-NEXT:    v_div_fmas_f32 v3, v3, v4, v61359; SI-NEXT:    v_div_fixup_f32 v2, v3, v2, -1.01360; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21361; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1362; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr641363; SI-NEXT:    s_endpgm1364;1365; GFX8-LABEL: v_neg_rsq_f16_missing_contract1:1366; GFX8:       ; %bb.0: ; %entry1367; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241368; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 1, v01369; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1370; GFX8-NEXT:    v_mov_b32_e32 v1, s31371; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v21372; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1373; GFX8-NEXT:    flat_load_ushort v0, v[0:1] glc1374; GFX8-NEXT:    s_waitcnt vmcnt(0)1375; GFX8-NEXT:    v_mov_b32_e32 v1, s11376; GFX8-NEXT:    v_sqrt_f16_e32 v0, v01377; GFX8-NEXT:    v_rcp_f16_e64 v3, -v01378; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v21379; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1380; GFX8-NEXT:    flat_store_short v[0:1], v31381; GFX8-NEXT:    s_endpgm1382;1383; GFX9-LABEL: v_neg_rsq_f16_missing_contract1:1384; GFX9:       ; %bb.0: ; %entry1385; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241386; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v01387; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1388; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc1389; GFX9-NEXT:    s_waitcnt vmcnt(0)1390; GFX9-NEXT:    v_sqrt_f16_e32 v1, v11391; GFX9-NEXT:    v_rcp_f16_e64 v1, -v11392; GFX9-NEXT:    global_store_short v0, v1, s[0:1]1393; GFX9-NEXT:    s_endpgm1394;1395; GFX10-LABEL: v_neg_rsq_f16_missing_contract1:1396; GFX10:       ; %bb.0: ; %entry1397; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241398; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v01399; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1400; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc1401; GFX10-NEXT:    s_waitcnt vmcnt(0)1402; GFX10-NEXT:    v_sqrt_f16_e32 v1, v11403; GFX10-NEXT:    v_rcp_f16_e64 v1, -v11404; GFX10-NEXT:    global_store_short v0, v1, s[0:1]1405; GFX10-NEXT:    s_endpgm1406;1407; GFX11-TRUE16-LABEL: v_neg_rsq_f16_missing_contract1:1408; GFX11-TRUE16:       ; %bb.0: ; %entry1409; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241410; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01411; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1412; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v01413; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1414; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc1415; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1416; GFX11-TRUE16-NEXT:    v_sqrt_f16_e32 v0.l, v0.l1417; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1418; GFX11-TRUE16-NEXT:    v_rcp_f16_e64 v0.l, -v0.l1419; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1420; GFX11-TRUE16-NEXT:    s_endpgm1421;1422; GFX11-FAKE16-LABEL: v_neg_rsq_f16_missing_contract1:1423; GFX11-FAKE16:       ; %bb.0: ; %entry1424; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241425; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01426; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1427; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v01428; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1429; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc1430; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1431; GFX11-FAKE16-NEXT:    v_sqrt_f16_e32 v1, v11432; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1433; GFX11-FAKE16-NEXT:    v_rcp_f16_e64 v1, -v11434; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]1435; GFX11-FAKE16-NEXT:    s_endpgm1436entry:1437  %tid = call i32 @llvm.amdgcn.workitem.id.x()1438  %tid.ext = sext i32 %tid to i641439  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext1440  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext1441  %b.val = load volatile half, ptr addrspace(1) %gep.b1442  %b.sqrt = call contract half @llvm.sqrt.f16(half %b.val)1443  %r.val = fdiv half -1.0, %b.sqrt1444  store half %r.val, ptr addrspace(1) %gep.r1445  ret void1446}1447 1448define amdgpu_kernel void @v_fdiv_f16_afn(ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b) #0 {1449; SI-LABEL: v_fdiv_f16_afn:1450; SI:       ; %bb.0: ; %entry1451; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91452; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd1453; SI-NEXT:    s_mov_b32 s7, 0xf0001454; SI-NEXT:    s_mov_b32 s6, 01455; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v01456; SI-NEXT:    s_waitcnt lgkmcnt(0)1457; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1458; SI-NEXT:    v_mov_b32_e32 v1, 01459; SI-NEXT:    s_mov_b64 s[10:11], s[6:7]1460; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc1461; SI-NEXT:    s_waitcnt vmcnt(0)1462; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc1463; SI-NEXT:    s_waitcnt vmcnt(0)1464; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1465; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21466; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31467; SI-NEXT:    v_rcp_f32_e32 v3, v31468; SI-NEXT:    v_mul_f32_e32 v2, v2, v31469; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21470; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr641471; SI-NEXT:    s_endpgm1472;1473; GFX8-LABEL: v_fdiv_f16_afn:1474; GFX8:       ; %bb.0: ; %entry1475; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241476; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341477; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 1, v01478; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1479; GFX8-NEXT:    v_mov_b32_e32 v1, s31480; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v41481; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1482; GFX8-NEXT:    v_mov_b32_e32 v3, s51483; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s4, v41484; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc1485; GFX8-NEXT:    flat_load_ushort v5, v[0:1] glc1486; GFX8-NEXT:    s_waitcnt vmcnt(0)1487; GFX8-NEXT:    flat_load_ushort v0, v[2:3] glc1488; GFX8-NEXT:    s_waitcnt vmcnt(0)1489; GFX8-NEXT:    v_mov_b32_e32 v1, s11490; GFX8-NEXT:    v_rcp_f16_e32 v2, v01491; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v41492; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1493; GFX8-NEXT:    v_mul_f16_e32 v2, v5, v21494; GFX8-NEXT:    flat_store_short v[0:1], v21495; GFX8-NEXT:    s_endpgm1496;1497; GFX9-LABEL: v_fdiv_f16_afn:1498; GFX9:       ; %bb.0: ; %entry1499; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241500; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341501; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v01502; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1503; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc1504; GFX9-NEXT:    s_waitcnt vmcnt(0)1505; GFX9-NEXT:    global_load_ushort v2, v0, s[6:7] glc1506; GFX9-NEXT:    s_waitcnt vmcnt(0)1507; GFX9-NEXT:    v_rcp_f16_e32 v2, v21508; GFX9-NEXT:    v_mul_f16_e32 v1, v1, v21509; GFX9-NEXT:    global_store_short v0, v1, s[0:1]1510; GFX9-NEXT:    s_endpgm1511;1512; GFX10-LABEL: v_fdiv_f16_afn:1513; GFX10:       ; %bb.0: ; %entry1514; GFX10-NEXT:    s_clause 0x11515; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241516; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341517; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v01518; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1519; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc1520; GFX10-NEXT:    s_waitcnt vmcnt(0)1521; GFX10-NEXT:    global_load_ushort v2, v0, s[6:7] glc dlc1522; GFX10-NEXT:    s_waitcnt vmcnt(0)1523; GFX10-NEXT:    v_rcp_f16_e32 v2, v21524; GFX10-NEXT:    v_mul_f16_e32 v1, v1, v21525; GFX10-NEXT:    global_store_short v0, v1, s[0:1]1526; GFX10-NEXT:    s_endpgm1527;1528; GFX11-TRUE16-LABEL: v_fdiv_f16_afn:1529; GFX11-TRUE16:       ; %bb.0: ; %entry1530; GFX11-TRUE16-NEXT:    s_clause 0x11531; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241532; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341533; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01534; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1535; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v01536; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1537; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc1538; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1539; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[4:5] glc dlc1540; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1541; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v0.h, v0.h1542; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1543; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v0.h1544; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1545; GFX11-TRUE16-NEXT:    s_endpgm1546;1547; GFX11-FAKE16-LABEL: v_fdiv_f16_afn:1548; GFX11-FAKE16:       ; %bb.0: ; %entry1549; GFX11-FAKE16-NEXT:    s_clause 0x11550; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241551; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341552; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01553; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1554; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v01555; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1556; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc1557; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1558; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] glc dlc1559; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1560; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v2, v21561; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1562; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v1, v1, v21563; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]1564; GFX11-FAKE16-NEXT:    s_endpgm1565entry:1566  %tid = call i32 @llvm.amdgcn.workitem.id.x()1567  %tid.ext = sext i32 %tid to i641568  %gep.a = getelementptr inbounds half, ptr addrspace(1) %a, i64 %tid.ext1569  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext1570  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext1571  %a.val = load volatile half, ptr addrspace(1) %gep.a1572  %b.val = load volatile half, ptr addrspace(1) %gep.b1573  %r.val = fdiv afn half %a.val, %b.val1574  store half %r.val, ptr addrspace(1) %gep.r1575  ret void1576}1577 1578define amdgpu_kernel void @v_fdiv_f16_unsafe(ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b) #2 {1579; SI-LABEL: v_fdiv_f16_unsafe:1580; SI:       ; %bb.0: ; %entry1581; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91582; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd1583; SI-NEXT:    s_mov_b32 s7, 0xf0001584; SI-NEXT:    s_mov_b32 s6, 01585; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v01586; SI-NEXT:    s_waitcnt lgkmcnt(0)1587; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]1588; SI-NEXT:    v_mov_b32_e32 v1, 01589; SI-NEXT:    s_mov_b64 s[10:11], s[6:7]1590; SI-NEXT:    buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc1591; SI-NEXT:    s_waitcnt vmcnt(0)1592; SI-NEXT:    buffer_load_ushort v3, v[0:1], s[8:11], 0 addr64 glc1593; SI-NEXT:    s_waitcnt vmcnt(0)1594; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1595; SI-NEXT:    v_cvt_f32_f16_e32 v2, v21596; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31597; SI-NEXT:    v_rcp_f32_e32 v3, v31598; SI-NEXT:    v_mul_f32_e32 v2, v2, v31599; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21600; SI-NEXT:    buffer_store_short v2, v[0:1], s[0:3], 0 addr641601; SI-NEXT:    s_endpgm1602;1603; GFX8-LABEL: v_fdiv_f16_unsafe:1604; GFX8:       ; %bb.0: ; %entry1605; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241606; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341607; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 1, v01608; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1609; GFX8-NEXT:    v_mov_b32_e32 v1, s31610; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v41611; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1612; GFX8-NEXT:    v_mov_b32_e32 v3, s51613; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s4, v41614; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc1615; GFX8-NEXT:    flat_load_ushort v5, v[0:1] glc1616; GFX8-NEXT:    s_waitcnt vmcnt(0)1617; GFX8-NEXT:    flat_load_ushort v0, v[2:3] glc1618; GFX8-NEXT:    s_waitcnt vmcnt(0)1619; GFX8-NEXT:    v_mov_b32_e32 v1, s11620; GFX8-NEXT:    v_rcp_f16_e32 v2, v01621; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v41622; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1623; GFX8-NEXT:    v_mul_f16_e32 v2, v5, v21624; GFX8-NEXT:    flat_store_short v[0:1], v21625; GFX8-NEXT:    s_endpgm1626;1627; GFX9-LABEL: v_fdiv_f16_unsafe:1628; GFX9:       ; %bb.0: ; %entry1629; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241630; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341631; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 1, v01632; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1633; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3] glc1634; GFX9-NEXT:    s_waitcnt vmcnt(0)1635; GFX9-NEXT:    global_load_ushort v2, v0, s[6:7] glc1636; GFX9-NEXT:    s_waitcnt vmcnt(0)1637; GFX9-NEXT:    v_rcp_f16_e32 v2, v21638; GFX9-NEXT:    v_mul_f16_e32 v1, v1, v21639; GFX9-NEXT:    global_store_short v0, v1, s[0:1]1640; GFX9-NEXT:    s_endpgm1641;1642; GFX10-LABEL: v_fdiv_f16_unsafe:1643; GFX10:       ; %bb.0: ; %entry1644; GFX10-NEXT:    s_clause 0x11645; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241646; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341647; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v01648; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1649; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc1650; GFX10-NEXT:    s_waitcnt vmcnt(0)1651; GFX10-NEXT:    global_load_ushort v2, v0, s[6:7] glc dlc1652; GFX10-NEXT:    s_waitcnt vmcnt(0)1653; GFX10-NEXT:    v_rcp_f16_e32 v2, v21654; GFX10-NEXT:    v_mul_f16_e32 v1, v1, v21655; GFX10-NEXT:    global_store_short v0, v1, s[0:1]1656; GFX10-NEXT:    s_endpgm1657;1658; GFX11-TRUE16-LABEL: v_fdiv_f16_unsafe:1659; GFX11-TRUE16:       ; %bb.0: ; %entry1660; GFX11-TRUE16-NEXT:    s_clause 0x11661; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241662; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341663; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01664; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1665; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 1, v01666; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1667; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[2:3] glc dlc1668; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1669; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v1, s[4:5] glc dlc1670; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1671; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v0.h, v0.h1672; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1673; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v0.h1674; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1675; GFX11-TRUE16-NEXT:    s_endpgm1676;1677; GFX11-FAKE16-LABEL: v_fdiv_f16_unsafe:1678; GFX11-FAKE16:       ; %bb.0: ; %entry1679; GFX11-FAKE16-NEXT:    s_clause 0x11680; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241681; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341682; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v01683; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1684; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v01685; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1686; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3] glc dlc1687; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1688; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] glc dlc1689; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1690; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v2, v21691; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1692; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v1, v1, v21693; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]1694; GFX11-FAKE16-NEXT:    s_endpgm1695entry:1696  %tid = call i32 @llvm.amdgcn.workitem.id.x()1697  %tid.ext = sext i32 %tid to i641698  %gep.a = getelementptr inbounds half, ptr addrspace(1) %a, i64 %tid.ext1699  %gep.b = getelementptr inbounds half, ptr addrspace(1) %b, i64 %tid.ext1700  %gep.r = getelementptr inbounds half, ptr addrspace(1) %r, i64 %tid.ext1701  %a.val = load volatile half, ptr addrspace(1) %gep.a1702  %b.val = load volatile half, ptr addrspace(1) %gep.b1703  %r.val = fdiv afn half %a.val, %b.val1704  store half %r.val, ptr addrspace(1) %gep.r1705  ret void1706}1707 1708define amdgpu_kernel void @div_afn_2_x_pat_f16(ptr addrspace(1) %out) #0 {1709; SI-LABEL: div_afn_2_x_pat_f16:1710; SI:       ; %bb.0:1711; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91712; SI-NEXT:    s_mov_b32 s3, 0xf0001713; SI-NEXT:    s_mov_b32 s2, -11714; SI-NEXT:    s_waitcnt lgkmcnt(0)1715; SI-NEXT:    buffer_load_ushort v0, off, s[0:3], 01716; SI-NEXT:    s_waitcnt vmcnt(0)1717; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01718; SI-NEXT:    v_mul_f32_e32 v0, 0.5, v01719; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01720; SI-NEXT:    buffer_store_short v0, off, s[0:3], 01721; SI-NEXT:    s_endpgm1722;1723; GFX8-LABEL: div_afn_2_x_pat_f16:1724; GFX8:       ; %bb.0:1725; GFX8-NEXT:    flat_load_ushort v0, v[0:1]1726; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241727; GFX8-NEXT:    s_waitcnt vmcnt(0)1728; GFX8-NEXT:    v_mul_f16_e32 v2, 0.5, v01729; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1730; GFX8-NEXT:    v_mov_b32_e32 v0, s01731; GFX8-NEXT:    v_mov_b32_e32 v1, s11732; GFX8-NEXT:    flat_store_short v[0:1], v21733; GFX8-NEXT:    s_endpgm1734;1735; GFX9-LABEL: div_afn_2_x_pat_f16:1736; GFX9:       ; %bb.0:1737; GFX9-NEXT:    global_load_ushort v0, v[0:1], off1738; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241739; GFX9-NEXT:    v_mov_b32_e32 v1, 01740; GFX9-NEXT:    s_waitcnt vmcnt(0)1741; GFX9-NEXT:    v_mul_f16_e32 v0, 0.5, v01742; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1743; GFX9-NEXT:    global_store_short v1, v0, s[0:1]1744; GFX9-NEXT:    s_endpgm1745;1746; GFX10-LABEL: div_afn_2_x_pat_f16:1747; GFX10:       ; %bb.0:1748; GFX10-NEXT:    global_load_ushort v0, v[0:1], off1749; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241750; GFX10-NEXT:    v_mov_b32_e32 v1, 01751; GFX10-NEXT:    s_waitcnt vmcnt(0)1752; GFX10-NEXT:    v_mul_f16_e32 v0, 0.5, v01753; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1754; GFX10-NEXT:    global_store_short v1, v0, s[0:1]1755; GFX10-NEXT:    s_endpgm1756;1757; GFX11-TRUE16-LABEL: div_afn_2_x_pat_f16:1758; GFX11-TRUE16:       ; %bb.0:1759; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off1760; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241761; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 01762; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1763; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0.5, v0.l1764; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1765; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1766; GFX11-TRUE16-NEXT:    s_endpgm1767;1768; GFX11-FAKE16-LABEL: div_afn_2_x_pat_f16:1769; GFX11-FAKE16:       ; %bb.0:1770; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off1771; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241772; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 01773; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1774; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, 0.5, v01775; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1776; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]1777; GFX11-FAKE16-NEXT:    s_endpgm1778  %x = load half, ptr addrspace(1) poison1779  %rcp = fdiv afn half %x, 2.01780  store half %rcp, ptr addrspace(1) %out, align 41781  ret void1782}1783 1784define amdgpu_kernel void @div_afn_k_x_pat_f16(ptr addrspace(1) %out) #0 {1785; SI-LABEL: div_afn_k_x_pat_f16:1786; SI:       ; %bb.0:1787; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91788; SI-NEXT:    s_mov_b32 s3, 0xf0001789; SI-NEXT:    s_mov_b32 s2, -11790; SI-NEXT:    s_waitcnt lgkmcnt(0)1791; SI-NEXT:    buffer_load_ushort v0, off, s[0:3], 01792; SI-NEXT:    s_waitcnt vmcnt(0)1793; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01794; SI-NEXT:    v_mul_f32_e32 v0, 0x3dcccccd, v01795; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01796; SI-NEXT:    buffer_store_short v0, off, s[0:3], 01797; SI-NEXT:    s_endpgm1798;1799; GFX8-LABEL: div_afn_k_x_pat_f16:1800; GFX8:       ; %bb.0:1801; GFX8-NEXT:    flat_load_ushort v0, v[0:1]1802; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241803; GFX8-NEXT:    s_waitcnt vmcnt(0)1804; GFX8-NEXT:    v_mul_f16_e32 v2, 0x2e66, v01805; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1806; GFX8-NEXT:    v_mov_b32_e32 v0, s01807; GFX8-NEXT:    v_mov_b32_e32 v1, s11808; GFX8-NEXT:    flat_store_short v[0:1], v21809; GFX8-NEXT:    s_endpgm1810;1811; GFX9-LABEL: div_afn_k_x_pat_f16:1812; GFX9:       ; %bb.0:1813; GFX9-NEXT:    global_load_ushort v0, v[0:1], off1814; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241815; GFX9-NEXT:    v_mov_b32_e32 v1, 01816; GFX9-NEXT:    s_waitcnt vmcnt(0)1817; GFX9-NEXT:    v_mul_f16_e32 v0, 0x2e66, v01818; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1819; GFX9-NEXT:    global_store_short v1, v0, s[0:1]1820; GFX9-NEXT:    s_endpgm1821;1822; GFX10-LABEL: div_afn_k_x_pat_f16:1823; GFX10:       ; %bb.0:1824; GFX10-NEXT:    global_load_ushort v0, v[0:1], off1825; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241826; GFX10-NEXT:    v_mov_b32_e32 v1, 01827; GFX10-NEXT:    s_waitcnt vmcnt(0)1828; GFX10-NEXT:    v_mul_f16_e32 v0, 0x2e66, v01829; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1830; GFX10-NEXT:    global_store_short v1, v0, s[0:1]1831; GFX10-NEXT:    s_endpgm1832;1833; GFX11-TRUE16-LABEL: div_afn_k_x_pat_f16:1834; GFX11-TRUE16:       ; %bb.0:1835; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off1836; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241837; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 01838; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1839; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0x2e66, v0.l1840; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1841; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1842; GFX11-TRUE16-NEXT:    s_endpgm1843;1844; GFX11-FAKE16-LABEL: div_afn_k_x_pat_f16:1845; GFX11-FAKE16:       ; %bb.0:1846; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off1847; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241848; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 01849; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1850; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, 0x2e66, v01851; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1852; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]1853; GFX11-FAKE16-NEXT:    s_endpgm1854  %x = load half, ptr addrspace(1) poison1855  %rcp = fdiv afn half %x, 10.01856  store half %rcp, ptr addrspace(1) %out, align 41857  ret void1858}1859 1860define amdgpu_kernel void @div_afn_neg_k_x_pat_f16(ptr addrspace(1) %out) #0 {1861; SI-LABEL: div_afn_neg_k_x_pat_f16:1862; SI:       ; %bb.0:1863; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x91864; SI-NEXT:    s_mov_b32 s3, 0xf0001865; SI-NEXT:    s_mov_b32 s2, -11866; SI-NEXT:    s_waitcnt lgkmcnt(0)1867; SI-NEXT:    buffer_load_ushort v0, off, s[0:3], 01868; SI-NEXT:    s_waitcnt vmcnt(0)1869; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01870; SI-NEXT:    v_mul_f32_e32 v0, 0xbdcccccd, v01871; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01872; SI-NEXT:    buffer_store_short v0, off, s[0:3], 01873; SI-NEXT:    s_endpgm1874;1875; GFX8-LABEL: div_afn_neg_k_x_pat_f16:1876; GFX8:       ; %bb.0:1877; GFX8-NEXT:    flat_load_ushort v0, v[0:1]1878; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241879; GFX8-NEXT:    s_waitcnt vmcnt(0)1880; GFX8-NEXT:    v_mul_f16_e32 v2, 0xae66, v01881; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1882; GFX8-NEXT:    v_mov_b32_e32 v0, s01883; GFX8-NEXT:    v_mov_b32_e32 v1, s11884; GFX8-NEXT:    flat_store_short v[0:1], v21885; GFX8-NEXT:    s_endpgm1886;1887; GFX9-LABEL: div_afn_neg_k_x_pat_f16:1888; GFX9:       ; %bb.0:1889; GFX9-NEXT:    global_load_ushort v0, v[0:1], off1890; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241891; GFX9-NEXT:    v_mov_b32_e32 v1, 01892; GFX9-NEXT:    s_waitcnt vmcnt(0)1893; GFX9-NEXT:    v_mul_f16_e32 v0, 0xae66, v01894; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1895; GFX9-NEXT:    global_store_short v1, v0, s[0:1]1896; GFX9-NEXT:    s_endpgm1897;1898; GFX10-LABEL: div_afn_neg_k_x_pat_f16:1899; GFX10:       ; %bb.0:1900; GFX10-NEXT:    global_load_ushort v0, v[0:1], off1901; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x241902; GFX10-NEXT:    v_mov_b32_e32 v1, 01903; GFX10-NEXT:    s_waitcnt vmcnt(0)1904; GFX10-NEXT:    v_mul_f16_e32 v0, 0xae66, v01905; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1906; GFX10-NEXT:    global_store_short v1, v0, s[0:1]1907; GFX10-NEXT:    s_endpgm1908;1909; GFX11-TRUE16-LABEL: div_afn_neg_k_x_pat_f16:1910; GFX11-TRUE16:       ; %bb.0:1911; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v[0:1], off1912; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241913; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 01914; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)1915; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, 0xae66, v0.l1916; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)1917; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]1918; GFX11-TRUE16-NEXT:    s_endpgm1919;1920; GFX11-FAKE16-LABEL: div_afn_neg_k_x_pat_f16:1921; GFX11-FAKE16:       ; %bb.0:1922; GFX11-FAKE16-NEXT:    global_load_u16 v0, v[0:1], off1923; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x241924; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 01925; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)1926; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, 0xae66, v01927; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)1928; GFX11-FAKE16-NEXT:    global_store_b16 v1, v0, s[0:1]1929; GFX11-FAKE16-NEXT:    s_endpgm1930  %x = load half, ptr addrspace(1) poison1931  %rcp = fdiv afn half %x, -10.01932  store half %rcp, ptr addrspace(1) %out, align 41933  ret void1934}1935 1936define half @v_fdiv_f16_arcp(half %x, half %y) {1937; SI-LABEL: v_fdiv_f16_arcp:1938; SI:       ; %bb.0:1939; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1940; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 01941; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11942; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01943; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11944; SI-NEXT:    v_cvt_f32_f16_e32 v0, v01945; SI-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v01946; SI-NEXT:    v_rcp_f32_e32 v3, v21947; SI-NEXT:    v_div_scale_f32 v4, vcc, v0, v1, v01948; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31949; SI-NEXT:    v_fma_f32 v5, -v2, v3, 1.01950; SI-NEXT:    v_fma_f32 v3, v5, v3, v31951; SI-NEXT:    v_mul_f32_e32 v5, v4, v31952; SI-NEXT:    v_fma_f32 v6, -v2, v5, v41953; SI-NEXT:    v_fma_f32 v5, v6, v3, v51954; SI-NEXT:    v_fma_f32 v2, -v2, v5, v41955; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01956; SI-NEXT:    v_div_fmas_f32 v2, v2, v3, v51957; SI-NEXT:    v_div_fixup_f32 v0, v2, v1, v01958; SI-NEXT:    s_setpc_b64 s[30:31]1959;1960; GFX8-LABEL: v_fdiv_f16_arcp:1961; GFX8:       ; %bb.0:1962; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1963; GFX8-NEXT:    v_rcp_f16_e32 v1, v11964; GFX8-NEXT:    v_mul_f16_e32 v0, v0, v11965; GFX8-NEXT:    s_setpc_b64 s[30:31]1966;1967; GFX9-LABEL: v_fdiv_f16_arcp:1968; GFX9:       ; %bb.0:1969; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1970; GFX9-NEXT:    v_rcp_f16_e32 v1, v11971; GFX9-NEXT:    v_mul_f16_e32 v0, v0, v11972; GFX9-NEXT:    s_setpc_b64 s[30:31]1973;1974; GFX10-LABEL: v_fdiv_f16_arcp:1975; GFX10:       ; %bb.0:1976; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1977; GFX10-NEXT:    v_rcp_f16_e32 v1, v11978; GFX10-NEXT:    v_mul_f16_e32 v0, v0, v11979; GFX10-NEXT:    s_setpc_b64 s[30:31]1980;1981; GFX11-TRUE16-LABEL: v_fdiv_f16_arcp:1982; GFX11-TRUE16:       ; %bb.0:1983; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1984; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v1.l1985; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1986; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l1987; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1988;1989; GFX11-FAKE16-LABEL: v_fdiv_f16_arcp:1990; GFX11-FAKE16:       ; %bb.0:1991; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1992; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v1, v11993; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)1994; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v11995; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1996  %fdiv = fdiv arcp half %x, %y1997  ret half %fdiv1998}1999 2000define half @v_fdiv_f16_afn_nsz(half %x, half %y) {2001; SI-LABEL: v_fdiv_f16_afn_nsz:2002; SI:       ; %bb.0:2003; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2004; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12005; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02006; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12007; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02008; SI-NEXT:    v_rcp_f32_e32 v1, v12009; SI-NEXT:    v_mul_f32_e32 v0, v0, v12010; SI-NEXT:    s_setpc_b64 s[30:31]2011;2012; GFX8-LABEL: v_fdiv_f16_afn_nsz:2013; GFX8:       ; %bb.0:2014; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2015; GFX8-NEXT:    v_rcp_f16_e32 v1, v12016; GFX8-NEXT:    v_mul_f16_e32 v0, v0, v12017; GFX8-NEXT:    s_setpc_b64 s[30:31]2018;2019; GFX9-LABEL: v_fdiv_f16_afn_nsz:2020; GFX9:       ; %bb.0:2021; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2022; GFX9-NEXT:    v_rcp_f16_e32 v1, v12023; GFX9-NEXT:    v_mul_f16_e32 v0, v0, v12024; GFX9-NEXT:    s_setpc_b64 s[30:31]2025;2026; GFX10-LABEL: v_fdiv_f16_afn_nsz:2027; GFX10:       ; %bb.0:2028; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2029; GFX10-NEXT:    v_rcp_f16_e32 v1, v12030; GFX10-NEXT:    v_mul_f16_e32 v0, v0, v12031; GFX10-NEXT:    s_setpc_b64 s[30:31]2032;2033; GFX11-TRUE16-LABEL: v_fdiv_f16_afn_nsz:2034; GFX11-TRUE16:       ; %bb.0:2035; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2036; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v1.l2037; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)2038; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v0.l, v0.l, v1.l2039; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2040;2041; GFX11-FAKE16-LABEL: v_fdiv_f16_afn_nsz:2042; GFX11-FAKE16:       ; %bb.0:2043; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2044; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v1, v12045; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)2046; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v0, v0, v12047; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2048  %fdiv = fdiv afn nsz half %x, %y2049  ret half %fdiv2050}2051 2052define <2 x half> @v_rsq_v2f16(<2 x half> %a) {2053; GFX6-IEEE-LABEL: v_rsq_v2f16:2054; GFX6-IEEE:       ; %bb.0:2055; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2056; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v02057; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v12058; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, 1.02059; GFX6-IEEE-NEXT:    v_sqrt_f32_e32 v0, v02060; GFX6-IEEE-NEXT:    v_sqrt_f32_e32 v1, v12061; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v02062; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v12063; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v02064; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v12065; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v22066; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v32067; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v2, v0, v22068; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v22069; GFX6-IEEE-NEXT:    v_fma_f32 v9, -v3, v6, 1.02070; GFX6-IEEE-NEXT:    v_fma_f32 v6, v9, v6, v62071; GFX6-IEEE-NEXT:    v_mul_f32_e32 v9, v4, v62072; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v52073; GFX6-IEEE-NEXT:    v_fma_f32 v10, -v3, v9, v42074; GFX6-IEEE-NEXT:    v_fma_f32 v9, v10, v6, v92075; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v42076; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v6, v92077; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v22078; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v8, 1.02079; GFX6-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v2, v1, v22080; GFX6-IEEE-NEXT:    v_fma_f32 v3, v3, v8, v82081; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v7, v32082; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v5, v4, v72083; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v3, v42084; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v5, v4, v72085; GFX6-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]2086; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v5, v3, v42087; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v22088; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v02089; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v12090; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]2091;2092; GFX6-FLUSH-LABEL: v_rsq_v2f16:2093; GFX6-FLUSH:       ; %bb.0:2094; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2095; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v02096; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v12097; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, 1.02098; GFX6-FLUSH-NEXT:    v_sqrt_f32_e32 v0, v02099; GFX6-FLUSH-NEXT:    v_sqrt_f32_e32 v1, v12100; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02101; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v02102; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v12103; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v02104; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v22105; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v32106; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v22107; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32108; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.02109; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v42110; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v42111; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v52112; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v62113; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v52114; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02115; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v62116; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, 1.02117; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v12118; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v0, v22119; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v02120; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v42121; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v22122; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v1, v42123; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32124; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.02125; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v32126; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v32127; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v52128; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v62129; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v52130; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02131; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v62132; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v42133; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v12134; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]2135;2136; SI-LABEL: v_rsq_v2f16:2137; SI:       ; %bb.0:2138; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2139; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02140; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02141; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12142; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02143; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12144; SI-NEXT:    v_sqrt_f32_e32 v0, v02145; SI-NEXT:    v_sqrt_f32_e32 v1, v12146; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02147; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12148; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02149; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12150; SI-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.02151; SI-NEXT:    v_rcp_f32_e32 v3, v22152; SI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.02153; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32154; SI-NEXT:    v_fma_f32 v5, -v2, v3, 1.02155; SI-NEXT:    v_fma_f32 v3, v5, v3, v32156; SI-NEXT:    v_mul_f32_e32 v5, v4, v32157; SI-NEXT:    v_fma_f32 v6, -v2, v5, v42158; SI-NEXT:    v_fma_f32 v5, v6, v3, v52159; SI-NEXT:    v_fma_f32 v2, -v2, v5, v42160; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02161; SI-NEXT:    v_div_fmas_f32 v2, v2, v3, v52162; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.02163; SI-NEXT:    v_rcp_f32_e32 v4, v32164; SI-NEXT:    v_div_scale_f32 v5, vcc, 1.0, v1, 1.02165; SI-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.02166; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32167; SI-NEXT:    v_fma_f32 v2, -v3, v4, 1.02168; SI-NEXT:    v_fma_f32 v2, v2, v4, v42169; SI-NEXT:    v_mul_f32_e32 v4, v5, v22170; SI-NEXT:    v_fma_f32 v6, -v3, v4, v52171; SI-NEXT:    v_fma_f32 v4, v6, v2, v42172; SI-NEXT:    v_fma_f32 v3, -v3, v4, v52173; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02174; SI-NEXT:    v_div_fmas_f32 v2, v3, v2, v42175; SI-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.02176; SI-NEXT:    s_setpc_b64 s[30:31]2177;2178; GFX8-LABEL: v_rsq_v2f16:2179; GFX8:       ; %bb.0:2180; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2181; GFX8-NEXT:    v_rsq_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_12182; GFX8-NEXT:    v_rsq_f16_e32 v0, v02183; GFX8-NEXT:    v_or_b32_e32 v0, v0, v12184; GFX8-NEXT:    s_setpc_b64 s[30:31]2185;2186; GFX9-LABEL: v_rsq_v2f16:2187; GFX9:       ; %bb.0:2188; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2189; GFX9-NEXT:    v_rsq_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12190; GFX9-NEXT:    v_rsq_f16_e32 v0, v02191; GFX9-NEXT:    v_pack_b32_f16 v0, v0, v12192; GFX9-NEXT:    s_setpc_b64 s[30:31]2193;2194; GFX10-LABEL: v_rsq_v2f16:2195; GFX10:       ; %bb.0:2196; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2197; GFX10-NEXT:    v_rsq_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12198; GFX10-NEXT:    v_rsq_f16_e32 v0, v02199; GFX10-NEXT:    v_pack_b32_f16 v0, v0, v12200; GFX10-NEXT:    s_setpc_b64 s[30:31]2201;2202; GFX11-TRUE16-LABEL: v_rsq_v2f16:2203; GFX11-TRUE16:       ; %bb.0:2204; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2205; GFX11-TRUE16-NEXT:    v_rsq_f16_e32 v0.h, v0.h2206; GFX11-TRUE16-NEXT:    v_rsq_f16_e32 v0.l, v0.l2207; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)2208; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h2209; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2210;2211; GFX11-FAKE16-LABEL: v_rsq_v2f16:2212; GFX11-FAKE16:       ; %bb.0:2213; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2214; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v02215; GFX11-FAKE16-NEXT:    v_rsq_f16_e32 v0, v02216; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2217; GFX11-FAKE16-NEXT:    v_rsq_f16_e32 v1, v12218; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)2219; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v12220; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2221; GFX9-IEEE-LABEL: v_rsq_v2f16:2222; GFX9-IEEE:       ; %bb.0:2223; GFX9-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2224; GFX9-IEEE-NEXT:    v_sqrt_f16_e32 v1, v02225; GFX9-IEEE-NEXT:    v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12226; GFX9-IEEE-NEXT:    v_cvt_f32_f16_e32 v4, 1.02227; GFX9-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v12228; GFX9-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v02229; GFX9-IEEE-NEXT:    v_rcp_f32_e32 v2, v22230; GFX9-IEEE-NEXT:    v_rcp_f32_e32 v3, v32231; GFX9-IEEE-NEXT:    v_mul_f32_e32 v2, v4, v22232; GFX9-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v32233; GFX9-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v22234; GFX9-IEEE-NEXT:    v_cvt_f16_f32_e32 v3, v32235; GFX9-IEEE-NEXT:    v_div_fixup_f16 v1, v2, v1, 1.02236; GFX9-IEEE-NEXT:    v_div_fixup_f16 v0, v3, v0, 1.02237; GFX9-IEEE-NEXT:    v_pack_b32_f16 v0, v1, v02238; GFX9-IEEE-NEXT:    s_setpc_b64 s[30:31]2239; GFX9-FLUSH-LABEL: v_rsq_v2f16:2240; GFX9-FLUSH:       ; %bb.0:2241; GFX9-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2242; GFX9-FLUSH-NEXT:    v_sqrt_f16_e32 v1, v02243; GFX9-FLUSH-NEXT:    v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12244; GFX9-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v12245; GFX9-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v02246; GFX9-FLUSH-NEXT:    v_rcp_f32_e32 v2, v22247; GFX9-FLUSH-NEXT:    v_rcp_f32_e32 v3, v32248; GFX9-FLUSH-NEXT:    v_mad_mixlo_f16 v2, 1.0, v2, 0 op_sel_hi:[1,0,0]2249; GFX9-FLUSH-NEXT:    v_mad_mixlo_f16 v3, 1.0, v3, 0 op_sel_hi:[1,0,0]2250; GFX9-FLUSH-NEXT:    v_div_fixup_f16 v1, v2, v1, 1.02251; GFX9-FLUSH-NEXT:    v_div_fixup_f16 v0, v3, v0, 1.02252; GFX9-FLUSH-NEXT:    v_pack_b32_f16 v0, v1, v02253; GFX9-FLUSH-NEXT:    s_setpc_b64 s[30:31]2254  %sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)2255  %fdiv = fdiv contract <2 x half> <half 1.0, half 1.0>, %sqrt2256  ret <2 x half> %fdiv2257}2258 2259define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {2260; GFX6-IEEE-LABEL: v_neg_rsq_v2f16:2261; GFX6-IEEE:       ; %bb.0:2262; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2263; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v02264; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v12265; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, -1.02266; GFX6-IEEE-NEXT:    v_sqrt_f32_e32 v0, v02267; GFX6-IEEE-NEXT:    v_sqrt_f32_e32 v1, v12268; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v02269; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v12270; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v02271; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v12272; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v22273; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v32274; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, v2, v0, v22275; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v22276; GFX6-IEEE-NEXT:    v_fma_f32 v9, -v3, v6, 1.02277; GFX6-IEEE-NEXT:    v_fma_f32 v6, v9, v6, v62278; GFX6-IEEE-NEXT:    v_mul_f32_e32 v9, v4, v62279; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v52280; GFX6-IEEE-NEXT:    v_fma_f32 v10, -v3, v9, v42281; GFX6-IEEE-NEXT:    v_fma_f32 v9, v10, v6, v92282; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v9, v42283; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v6, v92284; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v22285; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v8, 1.02286; GFX6-IEEE-NEXT:    v_div_scale_f32 v7, s[4:5], v2, v1, v22287; GFX6-IEEE-NEXT:    v_fma_f32 v3, v3, v8, v82288; GFX6-IEEE-NEXT:    v_mul_f32_e32 v4, v7, v32289; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v5, v4, v72290; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v3, v42291; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v5, v4, v72292; GFX6-IEEE-NEXT:    s_mov_b64 vcc, s[4:5]2293; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v5, v3, v42294; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v3, v1, v22295; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v02296; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v1, v12297; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]2298;2299; GFX6-FLUSH-LABEL: v_neg_rsq_v2f16:2300; GFX6-FLUSH:       ; %bb.0:2301; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2302; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v02303; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v12304; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, -1.02305; GFX6-FLUSH-NEXT:    v_sqrt_f32_e32 v0, v02306; GFX6-FLUSH-NEXT:    v_sqrt_f32_e32 v1, v12307; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02308; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v02309; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v12310; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v02311; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v22312; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v32313; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v2, v0, v22314; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32315; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.02316; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v42317; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v42318; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v52319; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v62320; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v52321; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02322; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v62323; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, -1.02324; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v1, v12325; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v3, v0, v22326; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v02327; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v42328; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v22329; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v1, v42330; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32331; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.02332; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v32333; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v32334; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v52335; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v62336; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v52337; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02338; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v62339; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, v42340; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v12341; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]2342;2343; SI-LABEL: v_neg_rsq_v2f16:2344; SI:       ; %bb.0:2345; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2346; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02347; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02348; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12349; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02350; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12351; SI-NEXT:    v_sqrt_f32_e32 v0, v02352; SI-NEXT:    v_sqrt_f32_e32 v1, v12353; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02354; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12355; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02356; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12357; SI-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, -1.02358; SI-NEXT:    v_rcp_f32_e32 v3, v22359; SI-NEXT:    v_div_scale_f32 v4, vcc, -1.0, v0, -1.02360; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32361; SI-NEXT:    v_fma_f32 v5, -v2, v3, 1.02362; SI-NEXT:    v_fma_f32 v3, v5, v3, v32363; SI-NEXT:    v_mul_f32_e32 v5, v4, v32364; SI-NEXT:    v_fma_f32 v6, -v2, v5, v42365; SI-NEXT:    v_fma_f32 v5, v6, v3, v52366; SI-NEXT:    v_fma_f32 v2, -v2, v5, v42367; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02368; SI-NEXT:    v_div_fmas_f32 v2, v2, v3, v52369; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, -1.02370; SI-NEXT:    v_rcp_f32_e32 v4, v32371; SI-NEXT:    v_div_scale_f32 v5, vcc, -1.0, v1, -1.02372; SI-NEXT:    v_div_fixup_f32 v0, v2, v0, -1.02373; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32374; SI-NEXT:    v_fma_f32 v2, -v3, v4, 1.02375; SI-NEXT:    v_fma_f32 v2, v2, v4, v42376; SI-NEXT:    v_mul_f32_e32 v4, v5, v22377; SI-NEXT:    v_fma_f32 v6, -v3, v4, v52378; SI-NEXT:    v_fma_f32 v4, v6, v2, v42379; SI-NEXT:    v_fma_f32 v3, -v3, v4, v52380; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02381; SI-NEXT:    v_div_fmas_f32 v2, v3, v2, v42382; SI-NEXT:    v_div_fixup_f32 v1, v2, v1, -1.02383; SI-NEXT:    s_setpc_b64 s[30:31]2384;2385; GFX8-LABEL: v_neg_rsq_v2f16:2386; GFX8:       ; %bb.0:2387; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2388; GFX8-NEXT:    v_rsq_f16_e32 v1, v02389; GFX8-NEXT:    v_rsq_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12390; GFX8-NEXT:    v_mov_b32_e32 v2, 0x80002391; GFX8-NEXT:    v_xor_b32_e32 v1, 0x8000, v12392; GFX8-NEXT:    v_xor_b32_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2393; GFX8-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2394; GFX8-NEXT:    s_setpc_b64 s[30:31]2395;2396; GFX9-LABEL: v_neg_rsq_v2f16:2397; GFX9:       ; %bb.0:2398; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2399; GFX9-NEXT:    v_rsq_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12400; GFX9-NEXT:    v_rsq_f16_e32 v0, v02401; GFX9-NEXT:    v_pack_b32_f16 v0, -v0, -v12402; GFX9-NEXT:    s_setpc_b64 s[30:31]2403;2404; GFX10-LABEL: v_neg_rsq_v2f16:2405; GFX10:       ; %bb.0:2406; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2407; GFX10-NEXT:    v_rsq_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12408; GFX10-NEXT:    v_rsq_f16_e32 v0, v02409; GFX10-NEXT:    v_pack_b32_f16 v0, -v0, -v12410; GFX10-NEXT:    s_setpc_b64 s[30:31]2411;2412; GFX11-TRUE16-LABEL: v_neg_rsq_v2f16:2413; GFX11-TRUE16:       ; %bb.0:2414; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2415; GFX11-TRUE16-NEXT:    v_rsq_f16_e32 v0.h, v0.h2416; GFX11-TRUE16-NEXT:    v_rsq_f16_e32 v0.l, v0.l2417; GFX11-TRUE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)2418; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, -v0.l, -v0.h2419; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2420;2421; GFX11-FAKE16-LABEL: v_neg_rsq_v2f16:2422; GFX11-FAKE16:       ; %bb.0:2423; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2424; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v02425; GFX11-FAKE16-NEXT:    v_rsq_f16_e32 v0, v02426; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2427; GFX11-FAKE16-NEXT:    v_rsq_f16_e32 v1, v12428; GFX11-FAKE16-NEXT:    s_waitcnt_depctr depctr_va_vdst(0)2429; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, -v0, -v12430; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2431; GFX9-IEEE-LABEL: v_neg_rsq_v2f16:2432; GFX9-IEEE:       ; %bb.0:2433; GFX9-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2434; GFX9-IEEE-NEXT:    v_sqrt_f16_e32 v1, v02435; GFX9-IEEE-NEXT:    v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12436; GFX9-IEEE-NEXT:    v_cvt_f32_f16_e32 v4, -1.02437; GFX9-IEEE-NEXT:    v_cvt_f32_f16_e32 v2, v12438; GFX9-IEEE-NEXT:    v_cvt_f32_f16_e32 v3, v02439; GFX9-IEEE-NEXT:    v_rcp_f32_e32 v2, v22440; GFX9-IEEE-NEXT:    v_rcp_f32_e32 v3, v32441; GFX9-IEEE-NEXT:    v_mul_f32_e32 v2, v4, v22442; GFX9-IEEE-NEXT:    v_mul_f32_e32 v3, v4, v32443; GFX9-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v22444; GFX9-IEEE-NEXT:    v_cvt_f16_f32_e32 v3, v32445; GFX9-IEEE-NEXT:    v_div_fixup_f16 v1, v2, v1, -1.02446; GFX9-IEEE-NEXT:    v_div_fixup_f16 v0, v3, v0, -1.02447; GFX9-IEEE-NEXT:    v_pack_b32_f16 v0, v1, v02448; GFX9-IEEE-NEXT:    s_setpc_b64 s[30:31]2449; GFX9-FLUSH-LABEL: v_neg_rsq_v2f16:2450; GFX9-FLUSH:       ; %bb.0:2451; GFX9-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2452; GFX9-FLUSH-NEXT:    v_sqrt_f16_e32 v1, v02453; GFX9-FLUSH-NEXT:    v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12454; GFX9-FLUSH-NEXT:    v_cvt_f32_f16_e32 v2, v12455; GFX9-FLUSH-NEXT:    v_cvt_f32_f16_e32 v3, v02456; GFX9-FLUSH-NEXT:    v_rcp_f32_e32 v2, v22457; GFX9-FLUSH-NEXT:    v_rcp_f32_e32 v3, v32458; GFX9-FLUSH-NEXT:    v_mad_mixlo_f16 v2, -1.0, v2, 0 op_sel_hi:[1,0,0]2459; GFX9-FLUSH-NEXT:    v_mad_mixlo_f16 v3, -1.0, v3, 0 op_sel_hi:[1,0,0]2460; GFX9-FLUSH-NEXT:    v_div_fixup_f16 v1, v2, v1, -1.02461; GFX9-FLUSH-NEXT:    v_div_fixup_f16 v0, v3, v0, -1.02462; GFX9-FLUSH-NEXT:    v_pack_b32_f16 v0, v1, v02463; GFX9-FLUSH-NEXT:    s_setpc_b64 s[30:31]2464  %sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)2465  %fdiv = fdiv contract <2 x half> <half -1.0, half -1.0>, %sqrt2466  ret <2 x half> %fdiv2467}2468 2469declare i32 @llvm.amdgcn.workitem.id.x() #22470declare half @llvm.sqrt.f16(half) #22471declare half @llvm.fabs.f16(half) #22472declare <2 x half> @llvm.sqrt.v2f16(<2 x half>) #22473 2474attributes #0 = { nounwind }2475attributes #1 = { nounwind readnone }2476attributes #2 = { nounwind }2477