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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Check for consistency of interpretation of fast math flags on fdiv3; between implementations.4 5; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,CODEGEN-IEEE-SDAG %s6; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,CODEGEN-IEEE-GISEL %s7; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,IR-IEEE,IR-IEEE-SDAG %s8; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=CHECK,IEEE,IR-IEEE,IR-IEEE-GISEL %s9 10; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,CODEGEN-DAZ,CODEGEN-DAZ-SDAG %s11; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=0 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,CODEGEN-DAZ,CODEGEN-DAZ-GISEL %s12; RUN: llc -global-isel=0 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,IR-DAZ,IR-DAZ-SDAG %s13; RUN: llc -global-isel=1 -amdgpu-codegenprepare-disable-fdiv-expansion=1 -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=CHECK,DAZ,IR-DAZ,IR-DAZ-GISEL %s14 15define float @v_fdiv_f32(float %x, float %y) {16; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_f32:17; CODEGEN-IEEE-SDAG: ; %bb.0:18; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; CODEGEN-IEEE-SDAG-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v020; CODEGEN-IEEE-SDAG-NEXT: v_rcp_f32_e32 v3, v221; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v4, -v2, v3, 1.022; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v3, v4, v3, v323; CODEGEN-IEEE-SDAG-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v024; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v5, v4, v325; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v6, -v2, v5, v426; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v5, v6, v3, v527; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v2, -v2, v5, v428; CODEGEN-IEEE-SDAG-NEXT: v_div_fmas_f32 v2, v2, v3, v529; CODEGEN-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v2, v1, v030; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]31;32; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_f32:33; CODEGEN-IEEE-GISEL: ; %bb.0:34; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v036; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v3, v237; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v038; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v2, v3, 1.039; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v3, v5, v3, v340; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v5, v4, v341; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v6, -v2, v5, v442; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, v6, v3, v543; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v2, -v2, v5, v444; CODEGEN-IEEE-GISEL-NEXT: v_div_fmas_f32 v2, v2, v3, v545; CODEGEN-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v2, v1, v046; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]47;48; IR-IEEE-SDAG-LABEL: v_fdiv_f32:49; IR-IEEE-SDAG: ; %bb.0:50; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v052; IR-IEEE-SDAG-NEXT: v_rcp_f32_e32 v3, v253; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, -v2, v3, 1.054; IR-IEEE-SDAG-NEXT: v_fma_f32 v3, v4, v3, v355; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v056; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v5, v4, v357; IR-IEEE-SDAG-NEXT: v_fma_f32 v6, -v2, v5, v458; IR-IEEE-SDAG-NEXT: v_fma_f32 v5, v6, v3, v559; IR-IEEE-SDAG-NEXT: v_fma_f32 v2, -v2, v5, v460; IR-IEEE-SDAG-NEXT: v_div_fmas_f32 v2, v2, v3, v561; IR-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v2, v1, v062; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]63;64; IR-IEEE-GISEL-LABEL: v_fdiv_f32:65; IR-IEEE-GISEL: ; %bb.0:66; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)67; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v068; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v3, v269; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v070; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v2, v3, 1.071; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, v5, v3, v372; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v5, v4, v373; IR-IEEE-GISEL-NEXT: v_fma_f32 v6, -v2, v5, v474; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, v6, v3, v575; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, -v2, v5, v476; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v2, v2, v3, v577; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v2, v1, v078; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]79;80; DAZ-LABEL: v_fdiv_f32:81; DAZ: ; %bb.0:82; DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; DAZ-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v084; DAZ-NEXT: v_rcp_f32_e32 v3, v285; DAZ-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v086; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 387; DAZ-NEXT: v_fma_f32 v5, -v2, v3, 1.088; DAZ-NEXT: v_fma_f32 v3, v5, v3, v389; DAZ-NEXT: v_mul_f32_e32 v5, v4, v390; DAZ-NEXT: v_fma_f32 v6, -v2, v5, v491; DAZ-NEXT: v_fma_f32 v5, v6, v3, v592; DAZ-NEXT: v_fma_f32 v2, -v2, v5, v493; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 094; DAZ-NEXT: v_div_fmas_f32 v2, v2, v3, v595; DAZ-NEXT: v_div_fixup_f32 v0, v2, v1, v096; DAZ-NEXT: s_setpc_b64 s[30:31]97 %fdiv = fdiv float %x, %y98 ret float %fdiv99}100 101define float @v_fdiv_f32_afn(float %x, float %y) {102; CHECK-LABEL: v_fdiv_f32_afn:103; CHECK: ; %bb.0:104; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)105; CHECK-NEXT: v_rcp_f32_e32 v1, v1106; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1107; CHECK-NEXT: s_setpc_b64 s[30:31]108 %fdiv = fdiv afn float %x, %y109 ret float %fdiv110}111 112define float @v_fdiv_f32_arcp(float %x, float %y) {113; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_f32_arcp:114; CODEGEN-IEEE-SDAG: ; %bb.0:115; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)116; CODEGEN-IEEE-SDAG-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0117; CODEGEN-IEEE-SDAG-NEXT: v_rcp_f32_e32 v3, v2118; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v4, -v2, v3, 1.0119; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v3, v4, v3, v3120; CODEGEN-IEEE-SDAG-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0121; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v5, v4, v3122; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v6, -v2, v5, v4123; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v5, v6, v3, v5124; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v2, -v2, v5, v4125; CODEGEN-IEEE-SDAG-NEXT: v_div_fmas_f32 v2, v2, v3, v5126; CODEGEN-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v2, v1, v0127; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]128;129; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_f32_arcp:130; CODEGEN-IEEE-GISEL: ; %bb.0:131; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)132; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0133; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v3, v2134; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0135; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v2, v3, 1.0136; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v3, v5, v3, v3137; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v5, v4, v3138; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v6, -v2, v5, v4139; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, v6, v3, v5140; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v2, -v2, v5, v4141; CODEGEN-IEEE-GISEL-NEXT: v_div_fmas_f32 v2, v2, v3, v5142; CODEGEN-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v2, v1, v0143; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]144;145; IR-IEEE-SDAG-LABEL: v_fdiv_f32_arcp:146; IR-IEEE-SDAG: ; %bb.0:147; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)148; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0149; IR-IEEE-SDAG-NEXT: v_rcp_f32_e32 v3, v2150; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, -v2, v3, 1.0151; IR-IEEE-SDAG-NEXT: v_fma_f32 v3, v4, v3, v3152; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0153; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v5, v4, v3154; IR-IEEE-SDAG-NEXT: v_fma_f32 v6, -v2, v5, v4155; IR-IEEE-SDAG-NEXT: v_fma_f32 v5, v6, v3, v5156; IR-IEEE-SDAG-NEXT: v_fma_f32 v2, -v2, v5, v4157; IR-IEEE-SDAG-NEXT: v_div_fmas_f32 v2, v2, v3, v5158; IR-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v2, v1, v0159; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]160;161; IR-IEEE-GISEL-LABEL: v_fdiv_f32_arcp:162; IR-IEEE-GISEL: ; %bb.0:163; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)164; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0165; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v3, v2166; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0167; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v2, v3, 1.0168; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, v5, v3, v3169; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v5, v4, v3170; IR-IEEE-GISEL-NEXT: v_fma_f32 v6, -v2, v5, v4171; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, v6, v3, v5172; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, -v2, v5, v4173; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v2, v2, v3, v5174; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v2, v1, v0175; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]176;177; DAZ-LABEL: v_fdiv_f32_arcp:178; DAZ: ; %bb.0:179; DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)180; DAZ-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0181; DAZ-NEXT: v_rcp_f32_e32 v3, v2182; DAZ-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0183; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3184; DAZ-NEXT: v_fma_f32 v5, -v2, v3, 1.0185; DAZ-NEXT: v_fma_f32 v3, v5, v3, v3186; DAZ-NEXT: v_mul_f32_e32 v5, v4, v3187; DAZ-NEXT: v_fma_f32 v6, -v2, v5, v4188; DAZ-NEXT: v_fma_f32 v5, v6, v3, v5189; DAZ-NEXT: v_fma_f32 v2, -v2, v5, v4190; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0191; DAZ-NEXT: v_div_fmas_f32 v2, v2, v3, v5192; DAZ-NEXT: v_div_fixup_f32 v0, v2, v1, v0193; DAZ-NEXT: s_setpc_b64 s[30:31]194 %fdiv = fdiv arcp float %x, %y195 ret float %fdiv196}197 198define float @v_fdiv_f32_arcp_afn(float %x, float %y) {199; CHECK-LABEL: v_fdiv_f32_arcp_afn:200; CHECK: ; %bb.0:201; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)202; CHECK-NEXT: v_rcp_f32_e32 v1, v1203; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1204; CHECK-NEXT: s_setpc_b64 s[30:31]205 %fdiv = fdiv arcp afn float %x, %y206 ret float %fdiv207}208 209define float @v_fdiv_recip_f32(float %x) {210; IEEE-LABEL: v_fdiv_recip_f32:211; IEEE: ; %bb.0:212; IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)213; IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0214; IEEE-NEXT: v_rcp_f32_e32 v2, v1215; IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0216; IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0217; IEEE-NEXT: v_fma_f32 v2, v4, v2, v2218; IEEE-NEXT: v_mul_f32_e32 v4, v3, v2219; IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3220; IEEE-NEXT: v_fma_f32 v4, v5, v2, v4221; IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3222; IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4223; IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0224; IEEE-NEXT: s_setpc_b64 s[30:31]225;226; DAZ-LABEL: v_fdiv_recip_f32:227; DAZ: ; %bb.0:228; DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)229; DAZ-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0230; DAZ-NEXT: v_rcp_f32_e32 v2, v1231; DAZ-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0232; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3233; DAZ-NEXT: v_fma_f32 v4, -v1, v2, 1.0234; DAZ-NEXT: v_fma_f32 v2, v4, v2, v2235; DAZ-NEXT: v_mul_f32_e32 v4, v3, v2236; DAZ-NEXT: v_fma_f32 v5, -v1, v4, v3237; DAZ-NEXT: v_fma_f32 v4, v5, v2, v4238; DAZ-NEXT: v_fma_f32 v1, -v1, v4, v3239; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0240; DAZ-NEXT: v_div_fmas_f32 v1, v1, v2, v4241; DAZ-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0242; DAZ-NEXT: s_setpc_b64 s[30:31]243 %fdiv = fdiv float 1.0, %x244 ret float %fdiv245}246 247define float @v_fdiv_recip_f32_afn(float %x) {248; CHECK-LABEL: v_fdiv_recip_f32_afn:249; CHECK: ; %bb.0:250; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)251; CHECK-NEXT: v_rcp_f32_e32 v0, v0252; CHECK-NEXT: s_setpc_b64 s[30:31]253 %fdiv = fdiv afn float 1.0, %x254 ret float %fdiv255}256 257define float @v_fdiv_recip_f32_arcp(float %x) {258; IEEE-LABEL: v_fdiv_recip_f32_arcp:259; IEEE: ; %bb.0:260; IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)261; IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0262; IEEE-NEXT: v_rcp_f32_e32 v2, v1263; IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0264; IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0265; IEEE-NEXT: v_fma_f32 v2, v4, v2, v2266; IEEE-NEXT: v_mul_f32_e32 v4, v3, v2267; IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3268; IEEE-NEXT: v_fma_f32 v4, v5, v2, v4269; IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3270; IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4271; IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0272; IEEE-NEXT: s_setpc_b64 s[30:31]273;274; DAZ-LABEL: v_fdiv_recip_f32_arcp:275; DAZ: ; %bb.0:276; DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)277; DAZ-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0278; DAZ-NEXT: v_rcp_f32_e32 v2, v1279; DAZ-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0280; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3281; DAZ-NEXT: v_fma_f32 v4, -v1, v2, 1.0282; DAZ-NEXT: v_fma_f32 v2, v4, v2, v2283; DAZ-NEXT: v_mul_f32_e32 v4, v3, v2284; DAZ-NEXT: v_fma_f32 v5, -v1, v4, v3285; DAZ-NEXT: v_fma_f32 v4, v5, v2, v4286; DAZ-NEXT: v_fma_f32 v1, -v1, v4, v3287; DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0288; DAZ-NEXT: v_div_fmas_f32 v1, v1, v2, v4289; DAZ-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0290; DAZ-NEXT: s_setpc_b64 s[30:31]291 %fdiv = fdiv arcp float 1.0, %x292 ret float %fdiv293}294 295define float @v_fdiv_recip_f32_arcp_afn(float %x) {296; CHECK-LABEL: v_fdiv_recip_f32_arcp_afn:297; CHECK: ; %bb.0:298; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)299; CHECK-NEXT: v_rcp_f32_e32 v0, v0300; CHECK-NEXT: s_setpc_b64 s[30:31]301 %fdiv = fdiv arcp afn float 1.0, %x302 ret float %fdiv303}304 305define float @v_fdiv_recip_sqrt_f32(float %x) {306; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32:307; CODEGEN-IEEE-SDAG: ; %bb.0:308; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)309; CODEGEN-IEEE-SDAG-NEXT: s_mov_b32 s4, 0xf800000310; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0311; CODEGEN-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0312; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc313; CODEGEN-IEEE-SDAG-NEXT: v_sqrt_f32_e32 v1, v0314; CODEGEN-IEEE-SDAG-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1315; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v3, -v2, v1, v0316; CODEGEN-IEEE-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3317; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]318; CODEGEN-IEEE-SDAG-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1319; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v1, -v3, v1, v0320; CODEGEN-IEEE-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1321; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]322; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v1323; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc324; CODEGEN-IEEE-SDAG-NEXT: v_mov_b32_e32 v2, 0x260325; CODEGEN-IEEE-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v2326; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc327; CODEGEN-IEEE-SDAG-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0328; CODEGEN-IEEE-SDAG-NEXT: v_rcp_f32_e32 v2, v1329; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v3, -v1, v2, 1.0330; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v2, v3, v2, v2331; CODEGEN-IEEE-SDAG-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0332; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v4, v3, v2333; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v5, -v1, v4, v3334; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v4, v5, v2, v4335; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v1, -v1, v4, v3336; CODEGEN-IEEE-SDAG-NEXT: v_div_fmas_f32 v1, v1, v2, v4337; CODEGEN-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0338; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]339;340; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32:341; CODEGEN-IEEE-GISEL: ; %bb.0:342; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)343; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000344; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0345; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1346; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc347; CODEGEN-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v0348; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1349; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v0350; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v1351; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v0352; CODEGEN-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3353; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]354; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v5355; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]356; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1357; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc358; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x260359; CODEGEN-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2360; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc361; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0362; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v1363; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0364; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0365; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2366; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2367; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3368; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4369; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3370; CODEGEN-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4371; CODEGEN-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0372; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]373;374; IR-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32:375; IR-IEEE-SDAG: ; %bb.0:376; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)377; IR-IEEE-SDAG-NEXT: s_mov_b32 s4, 0xf800000378; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0379; IR-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0380; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc381; IR-IEEE-SDAG-NEXT: v_sqrt_f32_e32 v1, v0382; IR-IEEE-SDAG-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1383; IR-IEEE-SDAG-NEXT: v_fma_f32 v3, -v2, v1, v0384; IR-IEEE-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3385; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]386; IR-IEEE-SDAG-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1387; IR-IEEE-SDAG-NEXT: v_fma_f32 v1, -v3, v1, v0388; IR-IEEE-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1389; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]390; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v1391; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc392; IR-IEEE-SDAG-NEXT: v_mov_b32_e32 v2, 0x260393; IR-IEEE-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v2394; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc395; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0396; IR-IEEE-SDAG-NEXT: v_rcp_f32_e32 v2, v1397; IR-IEEE-SDAG-NEXT: v_fma_f32 v3, -v1, v2, 1.0398; IR-IEEE-SDAG-NEXT: v_fma_f32 v2, v3, v2, v2399; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0400; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v4, v3, v2401; IR-IEEE-SDAG-NEXT: v_fma_f32 v5, -v1, v4, v3402; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, v5, v2, v4403; IR-IEEE-SDAG-NEXT: v_fma_f32 v1, -v1, v4, v3404; IR-IEEE-SDAG-NEXT: v_div_fmas_f32 v1, v1, v2, v4405; IR-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0406; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]407;408; IR-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32:409; IR-IEEE-GISEL: ; %bb.0:410; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)411; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000412; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0413; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1414; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc415; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v0416; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1417; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v0418; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v1419; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v0420; IR-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3421; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]422; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v5423; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]424; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1425; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc426; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x260427; IR-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2428; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc429; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0430; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v1431; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0432; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0433; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2434; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2435; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3436; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4437; IR-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3438; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4439; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0440; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]441;442; CODEGEN-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32:443; CODEGEN-DAZ-SDAG: ; %bb.0:444; CODEGEN-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)445; CODEGEN-DAZ-SDAG-NEXT: s_mov_b32 s4, 0xf800000446; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0447; CODEGEN-DAZ-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0448; CODEGEN-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc449; CODEGEN-DAZ-SDAG-NEXT: v_rsq_f32_e32 v1, v0450; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, v0, v1451; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0.5, v1452; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v3, -v1, v2, 0.5453; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v2, v2, v3, v2454; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v4, -v2, v2, v0455; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v1, v1, v3, v1456; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v1, v4, v1, v2457; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v1458; CODEGEN-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc459; CODEGEN-DAZ-SDAG-NEXT: v_mov_b32_e32 v2, 0x260460; CODEGEN-DAZ-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v2461; CODEGEN-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc462; CODEGEN-DAZ-SDAG-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0463; CODEGEN-DAZ-SDAG-NEXT: v_rcp_f32_e32 v2, v1464; CODEGEN-DAZ-SDAG-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0465; CODEGEN-DAZ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3466; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v4, -v1, v2, 1.0467; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v2, v4, v2, v2468; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v4, v3, v2469; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v5, -v1, v4, v3470; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v4, v5, v2, v4471; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v1, -v1, v4, v3472; CODEGEN-DAZ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0473; CODEGEN-DAZ-SDAG-NEXT: v_div_fmas_f32 v1, v1, v2, v4474; CODEGEN-DAZ-SDAG-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0475; CODEGEN-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]476;477; CODEGEN-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32:478; CODEGEN-DAZ-GISEL: ; %bb.0:479; CODEGEN-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)480; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000481; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0482; CODEGEN-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1483; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc484; CODEGEN-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v0485; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1486; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v1487; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.5488; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v2489; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v1490; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v0491; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v2492; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1493; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc494; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x260495; CODEGEN-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2496; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc497; CODEGEN-DAZ-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0498; CODEGEN-DAZ-GISEL-NEXT: v_rcp_f32_e32 v2, v1499; CODEGEN-DAZ-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0500; CODEGEN-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3501; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0502; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2503; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2504; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3505; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4506; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3507; CODEGEN-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0508; CODEGEN-DAZ-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4509; CODEGEN-DAZ-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0510; CODEGEN-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]511;512; IR-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32:513; IR-DAZ-SDAG: ; %bb.0:514; IR-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)515; IR-DAZ-SDAG-NEXT: s_mov_b32 s4, 0xf800000516; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0517; IR-DAZ-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0518; IR-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc519; IR-DAZ-SDAG-NEXT: v_rsq_f32_e32 v1, v0520; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, v0, v1521; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0.5, v1522; IR-DAZ-SDAG-NEXT: v_fma_f32 v3, -v1, v2, 0.5523; IR-DAZ-SDAG-NEXT: v_fma_f32 v2, v2, v3, v2524; IR-DAZ-SDAG-NEXT: v_fma_f32 v4, -v2, v2, v0525; IR-DAZ-SDAG-NEXT: v_fma_f32 v1, v1, v3, v1526; IR-DAZ-SDAG-NEXT: v_fma_f32 v1, v4, v1, v2527; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v1528; IR-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc529; IR-DAZ-SDAG-NEXT: v_mov_b32_e32 v2, 0x260530; IR-DAZ-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v2531; IR-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc532; IR-DAZ-SDAG-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0533; IR-DAZ-SDAG-NEXT: v_rcp_f32_e32 v2, v1534; IR-DAZ-SDAG-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0535; IR-DAZ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3536; IR-DAZ-SDAG-NEXT: v_fma_f32 v4, -v1, v2, 1.0537; IR-DAZ-SDAG-NEXT: v_fma_f32 v2, v4, v2, v2538; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v4, v3, v2539; IR-DAZ-SDAG-NEXT: v_fma_f32 v5, -v1, v4, v3540; IR-DAZ-SDAG-NEXT: v_fma_f32 v4, v5, v2, v4541; IR-DAZ-SDAG-NEXT: v_fma_f32 v1, -v1, v4, v3542; IR-DAZ-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0543; IR-DAZ-SDAG-NEXT: v_div_fmas_f32 v1, v1, v2, v4544; IR-DAZ-SDAG-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0545; IR-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]546;547; IR-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32:548; IR-DAZ-GISEL: ; %bb.0:549; IR-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)550; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000551; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0552; IR-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1553; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc554; IR-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v0555; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1556; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v1557; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.5558; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v2559; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v1560; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v0561; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v2562; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1563; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc564; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x260565; IR-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2566; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc567; IR-DAZ-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0568; IR-DAZ-GISEL-NEXT: v_rcp_f32_e32 v2, v1569; IR-DAZ-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0570; IR-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3571; IR-DAZ-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0572; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2573; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2574; IR-DAZ-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3575; IR-DAZ-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4576; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3577; IR-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0578; IR-DAZ-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4579; IR-DAZ-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0580; IR-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]581 %sqrt = call float @llvm.sqrt.f32(float %x)582 %fdiv = fdiv float 1.0, %sqrt583 ret float %fdiv584}585 586define float @v_fdiv_recip_sqrt_f32_afn(float %x) {587; CHECK-LABEL: v_fdiv_recip_sqrt_f32_afn:588; CHECK: ; %bb.0:589; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)590; CHECK-NEXT: v_sqrt_f32_e32 v0, v0591; CHECK-NEXT: v_rcp_f32_e32 v0, v0592; CHECK-NEXT: s_setpc_b64 s[30:31]593 %sqrt = call afn float @llvm.sqrt.f32(float %x)594 %fdiv = fdiv afn float 1.0, %sqrt595 ret float %fdiv596}597 598define float @v_fdiv_recip_sqrt_f32_arcp(float %x) {599; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp:600; CODEGEN-IEEE-SDAG: ; %bb.0:601; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)602; CODEGEN-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v0603; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]604;605; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp:606; CODEGEN-IEEE-GISEL: ; %bb.0:607; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)608; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000609; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0610; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1611; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc612; CODEGEN-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v0613; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1614; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v0615; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v1616; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v0617; CODEGEN-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3618; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]619; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v5620; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]621; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1622; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc623; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x260624; CODEGEN-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2625; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc626; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0627; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v1628; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0629; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0630; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2631; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2632; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3633; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4634; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3635; CODEGEN-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4636; CODEGEN-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0637; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]638;639; IR-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp:640; IR-IEEE-SDAG: ; %bb.0:641; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)642; IR-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v0643; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]644;645; IR-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp:646; IR-IEEE-GISEL: ; %bb.0:647; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)648; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000649; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0650; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1651; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc652; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v0653; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1654; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v0655; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v1656; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v0657; IR-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3658; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]659; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v5660; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]661; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1662; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc663; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x260664; IR-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2665; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc666; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0667; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v1668; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0669; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0670; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2671; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2672; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3673; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4674; IR-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3675; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4676; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0677; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]678;679; CODEGEN-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp:680; CODEGEN-DAZ-SDAG: ; %bb.0:681; CODEGEN-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)682; CODEGEN-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v0683; CODEGEN-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]684;685; CODEGEN-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp:686; CODEGEN-DAZ-GISEL: ; %bb.0:687; CODEGEN-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)688; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000689; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0690; CODEGEN-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1691; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc692; CODEGEN-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v0693; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1694; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v1695; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.5696; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v2697; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v1698; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v0699; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v2700; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1701; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc702; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x260703; CODEGEN-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2704; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc705; CODEGEN-DAZ-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0706; CODEGEN-DAZ-GISEL-NEXT: v_rcp_f32_e32 v2, v1707; CODEGEN-DAZ-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0708; CODEGEN-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3709; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0710; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2711; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2712; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3713; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4714; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3715; CODEGEN-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0716; CODEGEN-DAZ-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4717; CODEGEN-DAZ-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0718; CODEGEN-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]719;720; IR-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp:721; IR-DAZ-SDAG: ; %bb.0:722; IR-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)723; IR-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v0724; IR-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]725;726; IR-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp:727; IR-DAZ-GISEL: ; %bb.0:728; IR-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)729; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000730; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0731; IR-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1732; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc733; IR-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v0734; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1735; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v1736; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.5737; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v2738; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v1739; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v0740; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v2741; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1742; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc743; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x260744; IR-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2745; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc746; IR-DAZ-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0747; IR-DAZ-GISEL-NEXT: v_rcp_f32_e32 v2, v1748; IR-DAZ-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0749; IR-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3750; IR-DAZ-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0751; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2752; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2753; IR-DAZ-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3754; IR-DAZ-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4755; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3756; IR-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0757; IR-DAZ-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4758; IR-DAZ-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0759; IR-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]760 %sqrt = call arcp float @llvm.sqrt.f32(float %x)761 %fdiv = fdiv arcp float 1.0, %sqrt762 ret float %fdiv763}764 765define float @v_fdiv_recip_sqrt_f32_arcp_afn(float %x) {766; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:767; CODEGEN-IEEE-SDAG: ; %bb.0:768; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)769; CODEGEN-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v0770; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]771;772; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:773; CODEGEN-IEEE-GISEL: ; %bb.0:774; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)775; CODEGEN-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v0, v0776; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v0, v0777; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]778;779; IR-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:780; IR-IEEE-SDAG: ; %bb.0:781; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)782; IR-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v0783; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]784;785; IR-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:786; IR-IEEE-GISEL: ; %bb.0:787; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)788; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v0, v0789; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v0, v0790; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]791;792; CODEGEN-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:793; CODEGEN-DAZ-SDAG: ; %bb.0:794; CODEGEN-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)795; CODEGEN-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v0796; CODEGEN-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]797;798; CODEGEN-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:799; CODEGEN-DAZ-GISEL: ; %bb.0:800; CODEGEN-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)801; CODEGEN-DAZ-GISEL-NEXT: v_sqrt_f32_e32 v0, v0802; CODEGEN-DAZ-GISEL-NEXT: v_rcp_f32_e32 v0, v0803; CODEGEN-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]804;805; IR-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:806; IR-DAZ-SDAG: ; %bb.0:807; IR-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)808; IR-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v0809; IR-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]810;811; IR-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn:812; IR-DAZ-GISEL: ; %bb.0:813; IR-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)814; IR-DAZ-GISEL-NEXT: v_sqrt_f32_e32 v0, v0815; IR-DAZ-GISEL-NEXT: v_rcp_f32_e32 v0, v0816; IR-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]817 %sqrt = call arcp afn float @llvm.sqrt.f32(float %x)818 %fdiv = fdiv arcp afn float 1.0, %sqrt819 ret float %fdiv820}821 822define float @v_fdiv_recip_sqrt_f32_arcp_fdiv_only(float %x) {823; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:824; CODEGEN-IEEE-SDAG: ; %bb.0:825; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)826; CODEGEN-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v0827; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]828;829; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:830; CODEGEN-IEEE-GISEL: ; %bb.0:831; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)832; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000833; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0834; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1835; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc836; CODEGEN-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v0837; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1838; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v0839; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v1840; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v0841; CODEGEN-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3842; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]843; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v5844; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]845; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1846; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc847; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x260848; CODEGEN-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2849; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc850; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0851; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v1852; CODEGEN-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0853; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0854; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2855; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2856; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3857; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4858; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3859; CODEGEN-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4860; CODEGEN-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0861; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]862;863; IR-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:864; IR-IEEE-SDAG: ; %bb.0:865; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)866; IR-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v0867; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]868;869; IR-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:870; IR-IEEE-GISEL: ; %bb.0:871; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)872; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000873; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0874; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1875; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc876; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v0877; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1878; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v0879; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v1880; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v0881; IR-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3882; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]883; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v5884; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]885; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1886; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc887; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x260888; IR-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2889; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc890; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0891; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v1892; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0893; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0894; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2895; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2896; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3897; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4898; IR-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3899; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4900; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0901; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]902;903; CODEGEN-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:904; CODEGEN-DAZ-SDAG: ; %bb.0:905; CODEGEN-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)906; CODEGEN-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v0907; CODEGEN-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]908;909; CODEGEN-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:910; CODEGEN-DAZ-GISEL: ; %bb.0:911; CODEGEN-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)912; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000913; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0914; CODEGEN-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1915; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc916; CODEGEN-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v0917; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1918; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v1919; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.5920; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v2921; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v1922; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v0923; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v2924; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1925; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc926; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x260927; CODEGEN-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2928; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc929; CODEGEN-DAZ-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0930; CODEGEN-DAZ-GISEL-NEXT: v_rcp_f32_e32 v2, v1931; CODEGEN-DAZ-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0932; CODEGEN-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3933; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0934; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2935; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2936; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3937; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4938; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3939; CODEGEN-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0940; CODEGEN-DAZ-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4941; CODEGEN-DAZ-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0942; CODEGEN-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]943;944; IR-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:945; IR-DAZ-SDAG: ; %bb.0:946; IR-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)947; IR-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v0948; IR-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]949;950; IR-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_fdiv_only:951; IR-DAZ-GISEL: ; %bb.0:952; IR-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)953; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf800000954; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0955; IR-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1956; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc957; IR-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v0958; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1959; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v1960; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.5961; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v2962; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v1963; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v0964; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v2965; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v1966; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc967; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x260968; IR-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v2969; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc970; IR-DAZ-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0971; IR-DAZ-GISEL-NEXT: v_rcp_f32_e32 v2, v1972; IR-DAZ-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0973; IR-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3974; IR-DAZ-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.0975; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v4, v2, v2976; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v4, v3, v2977; IR-DAZ-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v3978; IR-DAZ-GISEL-NEXT: v_fma_f32 v4, v5, v2, v4979; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v3980; IR-DAZ-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0981; IR-DAZ-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v4982; IR-DAZ-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0983; IR-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]984 %sqrt = call float @llvm.sqrt.f32(float %x)985 %fdiv = fdiv arcp float 1.0, %sqrt986 ret float %fdiv987}988 989define float @v_fdiv_recip_sqrt_f32_afn_fdiv_only(float %x) {990; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:991; CODEGEN-IEEE-SDAG: ; %bb.0:992; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)993; CODEGEN-IEEE-SDAG-NEXT: s_mov_b32 s4, 0xf800000994; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0995; CODEGEN-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0996; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc997; CODEGEN-IEEE-SDAG-NEXT: v_sqrt_f32_e32 v1, v0998; CODEGEN-IEEE-SDAG-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1999; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v3, -v2, v1, v01000; CODEGEN-IEEE-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31001; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1002; CODEGEN-IEEE-SDAG-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11003; CODEGEN-IEEE-SDAG-NEXT: v_fma_f32 v1, -v3, v1, v01004; CODEGEN-IEEE-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11005; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1006; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v11007; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1008; CODEGEN-IEEE-SDAG-NEXT: v_mov_b32_e32 v2, 0x2601009; CODEGEN-IEEE-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v21010; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1011; CODEGEN-IEEE-SDAG-NEXT: v_rcp_f32_e32 v0, v01012; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1013;1014; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:1015; CODEGEN-IEEE-GISEL: ; %bb.0:1016; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1017; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001018; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01019; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11020; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1021; CODEGEN-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v01022; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11023; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v01024; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v11025; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v01026; CODEGEN-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31027; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]1028; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v51029; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]1030; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11031; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1032; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601033; CODEGEN-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21034; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1035; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v0, v01036; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1037;1038; IR-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:1039; IR-IEEE-SDAG: ; %bb.0:1040; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1041; IR-IEEE-SDAG-NEXT: s_mov_b32 s4, 0xf8000001042; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01043; IR-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01044; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1045; IR-IEEE-SDAG-NEXT: v_sqrt_f32_e32 v1, v01046; IR-IEEE-SDAG-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11047; IR-IEEE-SDAG-NEXT: v_fma_f32 v3, -v2, v1, v01048; IR-IEEE-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31049; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1050; IR-IEEE-SDAG-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11051; IR-IEEE-SDAG-NEXT: v_fma_f32 v1, -v3, v1, v01052; IR-IEEE-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11053; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1054; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v11055; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1056; IR-IEEE-SDAG-NEXT: v_mov_b32_e32 v2, 0x2601057; IR-IEEE-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v21058; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1059; IR-IEEE-SDAG-NEXT: v_rcp_f32_e32 v0, v01060; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1061;1062; IR-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:1063; IR-IEEE-GISEL: ; %bb.0:1064; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1065; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001066; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01067; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11068; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1069; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v01070; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11071; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v01072; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v11073; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v01074; IR-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31075; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]1076; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v51077; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]1078; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11079; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1080; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601081; IR-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21082; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1083; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v0, v01084; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1085;1086; CODEGEN-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:1087; CODEGEN-DAZ-SDAG: ; %bb.0:1088; CODEGEN-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1089; CODEGEN-DAZ-SDAG-NEXT: s_mov_b32 s4, 0xf8000001090; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01091; CODEGEN-DAZ-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01092; CODEGEN-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1093; CODEGEN-DAZ-SDAG-NEXT: v_rsq_f32_e32 v1, v01094; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, v0, v11095; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0.5, v11096; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v3, -v1, v2, 0.51097; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v2, v2, v3, v21098; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v4, -v2, v2, v01099; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v1, v1, v3, v11100; CODEGEN-DAZ-SDAG-NEXT: v_fma_f32 v1, v4, v1, v21101; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v11102; CODEGEN-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1103; CODEGEN-DAZ-SDAG-NEXT: v_mov_b32_e32 v2, 0x2601104; CODEGEN-DAZ-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v21105; CODEGEN-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1106; CODEGEN-DAZ-SDAG-NEXT: v_rcp_f32_e32 v0, v01107; CODEGEN-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]1108;1109; CODEGEN-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:1110; CODEGEN-DAZ-GISEL: ; %bb.0:1111; CODEGEN-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1112; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001113; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01114; CODEGEN-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11115; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1116; CODEGEN-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v01117; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v11118; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v11119; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.51120; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v21121; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v11122; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v01123; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v21124; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11125; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1126; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601127; CODEGEN-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21128; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1129; CODEGEN-DAZ-GISEL-NEXT: v_rcp_f32_e32 v0, v01130; CODEGEN-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]1131;1132; IR-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:1133; IR-DAZ-SDAG: ; %bb.0:1134; IR-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1135; IR-DAZ-SDAG-NEXT: s_mov_b32 s4, 0xf8000001136; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01137; IR-DAZ-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01138; IR-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1139; IR-DAZ-SDAG-NEXT: v_rsq_f32_e32 v1, v01140; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, v0, v11141; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, 0.5, v11142; IR-DAZ-SDAG-NEXT: v_fma_f32 v3, -v1, v2, 0.51143; IR-DAZ-SDAG-NEXT: v_fma_f32 v2, v2, v3, v21144; IR-DAZ-SDAG-NEXT: v_fma_f32 v4, -v2, v2, v01145; IR-DAZ-SDAG-NEXT: v_fma_f32 v1, v1, v3, v11146; IR-DAZ-SDAG-NEXT: v_fma_f32 v1, v4, v1, v21147; IR-DAZ-SDAG-NEXT: v_mul_f32_e32 v2, 0x37800000, v11148; IR-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1149; IR-DAZ-SDAG-NEXT: v_mov_b32_e32 v2, 0x2601150; IR-DAZ-SDAG-NEXT: v_cmp_class_f32_e32 vcc, v0, v21151; IR-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1152; IR-DAZ-SDAG-NEXT: v_rcp_f32_e32 v0, v01153; IR-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]1154;1155; IR-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_afn_fdiv_only:1156; IR-DAZ-GISEL: ; %bb.0:1157; IR-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1158; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001159; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01160; IR-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11161; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1162; IR-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v01163; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v11164; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v11165; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.51166; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v21167; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v11168; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v01169; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v21170; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11171; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1172; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601173; IR-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21174; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1175; IR-DAZ-GISEL-NEXT: v_rcp_f32_e32 v0, v01176; IR-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]1177 %sqrt = call float @llvm.sqrt.f32(float %x)1178 %fdiv = fdiv afn float 1.0, %sqrt1179 ret float %fdiv1180}1181 1182define float @v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only(float %x) {1183; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1184; CODEGEN-IEEE-SDAG: ; %bb.0:1185; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1186; CODEGEN-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v01187; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1188;1189; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1190; CODEGEN-IEEE-GISEL: ; %bb.0:1191; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1192; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001193; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01194; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11195; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1196; CODEGEN-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v01197; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11198; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v01199; CODEGEN-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v11200; CODEGEN-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v01201; CODEGEN-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31202; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]1203; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v51204; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]1205; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11206; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1207; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601208; CODEGEN-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21209; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1210; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v0, v01211; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1212;1213; IR-IEEE-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1214; IR-IEEE-SDAG: ; %bb.0:1215; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1216; IR-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v01217; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1218;1219; IR-IEEE-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1220; IR-IEEE-GISEL: ; %bb.0:1221; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1222; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001223; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01224; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11225; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1226; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v1, v01227; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11228; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, -v2, v1, v01229; IR-IEEE-GISEL-NEXT: v_add_i32_e64 v4, s[4:5], 1, v11230; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v4, v1, v01231; IR-IEEE-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31232; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5]1233; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v51234; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[4:5]1235; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11236; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1237; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601238; IR-IEEE-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21239; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1240; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v0, v01241; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1242;1243; CODEGEN-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1244; CODEGEN-DAZ-SDAG: ; %bb.0:1245; CODEGEN-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1246; CODEGEN-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v01247; CODEGEN-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]1248;1249; CODEGEN-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1250; CODEGEN-DAZ-GISEL: ; %bb.0:1251; CODEGEN-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1252; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001253; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01254; CODEGEN-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11255; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1256; CODEGEN-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v01257; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v11258; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v11259; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.51260; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v21261; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v11262; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v01263; CODEGEN-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v21264; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11265; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1266; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601267; CODEGEN-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21268; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1269; CODEGEN-DAZ-GISEL-NEXT: v_rcp_f32_e32 v0, v01270; CODEGEN-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]1271;1272; IR-DAZ-SDAG-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1273; IR-DAZ-SDAG: ; %bb.0:1274; IR-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1275; IR-DAZ-SDAG-NEXT: v_rsq_f32_e32 v0, v01276; IR-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]1277;1278; IR-DAZ-GISEL-LABEL: v_fdiv_recip_sqrt_f32_arcp_afn_fdiv_only:1279; IR-DAZ-GISEL: ; %bb.0:1280; IR-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1281; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v1, 0xf8000001282; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01283; IR-DAZ-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11284; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1285; IR-DAZ-GISEL-NEXT: v_rsq_f32_e32 v1, v01286; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, v0, v11287; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, 0.5, v11288; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v1, v2, 0.51289; IR-DAZ-GISEL-NEXT: v_fma_f32 v2, v2, v3, v21290; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v1, v3, v11291; IR-DAZ-GISEL-NEXT: v_fma_f32 v3, -v2, v2, v01292; IR-DAZ-GISEL-NEXT: v_fma_f32 v1, v3, v1, v21293; IR-DAZ-GISEL-NEXT: v_mul_f32_e32 v2, 0x37800000, v11294; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1295; IR-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x2601296; IR-DAZ-GISEL-NEXT: v_cmp_class_f32_e32 vcc, v0, v21297; IR-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1298; IR-DAZ-GISEL-NEXT: v_rcp_f32_e32 v0, v01299; IR-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]1300 %sqrt = call float @llvm.sqrt.f32(float %x)1301 %fdiv = fdiv arcp afn float 1.0, %sqrt1302 ret float %fdiv1303}1304 1305define float @v_fdiv_f32_ulp25(float %x, float %y) {1306; CODEGEN-IEEE-SDAG-LABEL: v_fdiv_f32_ulp25:1307; CODEGEN-IEEE-SDAG: ; %bb.0:1308; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1309; CODEGEN-IEEE-SDAG-NEXT: v_frexp_mant_f32_e32 v2, v11310; CODEGEN-IEEE-SDAG-NEXT: v_rcp_f32_e32 v2, v21311; CODEGEN-IEEE-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v1, v11312; CODEGEN-IEEE-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v3, v01313; CODEGEN-IEEE-SDAG-NEXT: v_frexp_mant_f32_e32 v0, v01314; CODEGEN-IEEE-SDAG-NEXT: v_mul_f32_e32 v0, v0, v21315; CODEGEN-IEEE-SDAG-NEXT: v_sub_i32_e32 v1, vcc, v3, v11316; CODEGEN-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11317; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1318;1319; CODEGEN-IEEE-GISEL-LABEL: v_fdiv_f32_ulp25:1320; CODEGEN-IEEE-GISEL: ; %bb.0:1321; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1322; CODEGEN-IEEE-GISEL-NEXT: v_frexp_mant_f32_e32 v2, v11323; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v21324; CODEGEN-IEEE-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v1, v11325; CODEGEN-IEEE-GISEL-NEXT: v_frexp_mant_f32_e32 v3, v01326; CODEGEN-IEEE-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, v01327; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v2, v3, v21328; CODEGEN-IEEE-GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v11329; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v2, v01330; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1331;1332; IR-IEEE-SDAG-LABEL: v_fdiv_f32_ulp25:1333; IR-IEEE-SDAG: ; %bb.0:1334; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1335; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v01336; IR-IEEE-SDAG-NEXT: v_rcp_f32_e32 v3, v21337; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, -v2, v3, 1.01338; IR-IEEE-SDAG-NEXT: v_fma_f32 v3, v4, v3, v31339; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v01340; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v5, v4, v31341; IR-IEEE-SDAG-NEXT: v_fma_f32 v6, -v2, v5, v41342; IR-IEEE-SDAG-NEXT: v_fma_f32 v5, v6, v3, v51343; IR-IEEE-SDAG-NEXT: v_fma_f32 v2, -v2, v5, v41344; IR-IEEE-SDAG-NEXT: v_div_fmas_f32 v2, v2, v3, v51345; IR-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v2, v1, v01346; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1347;1348; IR-IEEE-GISEL-LABEL: v_fdiv_f32_ulp25:1349; IR-IEEE-GISEL: ; %bb.0:1350; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1351; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v01352; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v3, v21353; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v01354; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v2, v3, 1.01355; IR-IEEE-GISEL-NEXT: v_fma_f32 v3, v5, v3, v31356; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v5, v4, v31357; IR-IEEE-GISEL-NEXT: v_fma_f32 v6, -v2, v5, v41358; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, v6, v3, v51359; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, -v2, v5, v41360; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v2, v2, v3, v51361; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v2, v1, v01362; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1363;1364; CODEGEN-DAZ-SDAG-LABEL: v_fdiv_f32_ulp25:1365; CODEGEN-DAZ-SDAG: ; %bb.0:1366; CODEGEN-DAZ-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1367; CODEGEN-DAZ-SDAG-NEXT: s_mov_b32 s4, 0x6f8000001368; CODEGEN-DAZ-SDAG-NEXT: v_mov_b32_e32 v2, 0x2f8000001369; CODEGEN-DAZ-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s41370; CODEGEN-DAZ-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc1371; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v1, v1, v21372; CODEGEN-DAZ-SDAG-NEXT: v_rcp_f32_e32 v1, v11373; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v0, v0, v11374; CODEGEN-DAZ-SDAG-NEXT: v_mul_f32_e32 v0, v2, v01375; CODEGEN-DAZ-SDAG-NEXT: s_setpc_b64 s[30:31]1376;1377; CODEGEN-DAZ-GISEL-LABEL: v_fdiv_f32_ulp25:1378; CODEGEN-DAZ-GISEL: ; %bb.0:1379; CODEGEN-DAZ-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1380; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v2, 0x6f8000001381; CODEGEN-DAZ-GISEL-NEXT: v_mov_b32_e32 v3, 0x2f8000001382; CODEGEN-DAZ-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, v21383; CODEGEN-DAZ-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc1384; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v1, v1, v21385; CODEGEN-DAZ-GISEL-NEXT: v_rcp_f32_e32 v1, v11386; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v0, v0, v11387; CODEGEN-DAZ-GISEL-NEXT: v_mul_f32_e32 v0, v2, v01388; CODEGEN-DAZ-GISEL-NEXT: s_setpc_b64 s[30:31]1389;1390; IR-DAZ-LABEL: v_fdiv_f32_ulp25:1391; IR-DAZ: ; %bb.0:1392; IR-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1393; IR-DAZ-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v01394; IR-DAZ-NEXT: v_rcp_f32_e32 v3, v21395; IR-DAZ-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v01396; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31397; IR-DAZ-NEXT: v_fma_f32 v5, -v2, v3, 1.01398; IR-DAZ-NEXT: v_fma_f32 v3, v5, v3, v31399; IR-DAZ-NEXT: v_mul_f32_e32 v5, v4, v31400; IR-DAZ-NEXT: v_fma_f32 v6, -v2, v5, v41401; IR-DAZ-NEXT: v_fma_f32 v5, v6, v3, v51402; IR-DAZ-NEXT: v_fma_f32 v2, -v2, v5, v41403; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01404; IR-DAZ-NEXT: v_div_fmas_f32 v2, v2, v3, v51405; IR-DAZ-NEXT: v_div_fixup_f32 v0, v2, v1, v01406; IR-DAZ-NEXT: s_setpc_b64 s[30:31]1407 %fdiv = fdiv float %x, %y, !fpmath !01408 ret float %fdiv1409}1410 1411define float @v_fdiv_f32_afn_ulp25(float %x, float %y) {1412; CHECK-LABEL: v_fdiv_f32_afn_ulp25:1413; CHECK: ; %bb.0:1414; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1415; CHECK-NEXT: v_rcp_f32_e32 v1, v11416; CHECK-NEXT: v_mul_f32_e32 v0, v0, v11417; CHECK-NEXT: s_setpc_b64 s[30:31]1418 %fdiv = fdiv afn float %x, %y, !fpmath !01419 ret float %fdiv1420}1421 1422define float @v_recip_f32_ulp25(float %x) {1423; CODEGEN-IEEE-SDAG-LABEL: v_recip_f32_ulp25:1424; CODEGEN-IEEE-SDAG: ; %bb.0:1425; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1426; CODEGEN-IEEE-SDAG-NEXT: v_frexp_mant_f32_e32 v1, v01427; CODEGEN-IEEE-SDAG-NEXT: v_rcp_f32_e32 v1, v11428; CODEGEN-IEEE-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, v01429; CODEGEN-IEEE-SDAG-NEXT: v_sub_i32_e32 v0, vcc, 0, v01430; CODEGEN-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v1, v01431; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1432;1433; CODEGEN-IEEE-GISEL-LABEL: v_recip_f32_ulp25:1434; CODEGEN-IEEE-GISEL: ; %bb.0:1435; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1436; CODEGEN-IEEE-GISEL-NEXT: v_frexp_mant_f32_e32 v1, v01437; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v1, v11438; CODEGEN-IEEE-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, v01439; CODEGEN-IEEE-GISEL-NEXT: v_sub_i32_e32 v0, vcc, 0, v01440; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v1, v01441; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1442;1443; IR-IEEE-LABEL: v_recip_f32_ulp25:1444; IR-IEEE: ; %bb.0:1445; IR-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1446; IR-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01447; IR-IEEE-NEXT: v_rcp_f32_e32 v2, v11448; IR-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01449; IR-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.01450; IR-IEEE-NEXT: v_fma_f32 v2, v4, v2, v21451; IR-IEEE-NEXT: v_mul_f32_e32 v4, v3, v21452; IR-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v31453; IR-IEEE-NEXT: v_fma_f32 v4, v5, v2, v41454; IR-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v31455; IR-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v41456; IR-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01457; IR-IEEE-NEXT: s_setpc_b64 s[30:31]1458;1459; CODEGEN-DAZ-LABEL: v_recip_f32_ulp25:1460; CODEGEN-DAZ: ; %bb.0:1461; CODEGEN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1462; CODEGEN-DAZ-NEXT: v_rcp_f32_e32 v0, v01463; CODEGEN-DAZ-NEXT: s_setpc_b64 s[30:31]1464;1465; IR-DAZ-LABEL: v_recip_f32_ulp25:1466; IR-DAZ: ; %bb.0:1467; IR-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1468; IR-DAZ-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01469; IR-DAZ-NEXT: v_rcp_f32_e32 v2, v11470; IR-DAZ-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01471; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31472; IR-DAZ-NEXT: v_fma_f32 v4, -v1, v2, 1.01473; IR-DAZ-NEXT: v_fma_f32 v2, v4, v2, v21474; IR-DAZ-NEXT: v_mul_f32_e32 v4, v3, v21475; IR-DAZ-NEXT: v_fma_f32 v5, -v1, v4, v31476; IR-DAZ-NEXT: v_fma_f32 v4, v5, v2, v41477; IR-DAZ-NEXT: v_fma_f32 v1, -v1, v4, v31478; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01479; IR-DAZ-NEXT: v_div_fmas_f32 v1, v1, v2, v41480; IR-DAZ-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01481; IR-DAZ-NEXT: s_setpc_b64 s[30:31]1482 %fdiv = fdiv float 1.0, %x, !fpmath !01483 ret float %fdiv1484}1485 1486define float @v_recip_f32_afn_ulp25(float %x) {1487; CHECK-LABEL: v_recip_f32_afn_ulp25:1488; CHECK: ; %bb.0:1489; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1490; CHECK-NEXT: v_rcp_f32_e32 v0, v01491; CHECK-NEXT: s_setpc_b64 s[30:31]1492 %fdiv = fdiv afn float 1.0, %x, !fpmath !01493 ret float %fdiv1494}1495 1496define float @v_recip_sqrt_f32_ulp25(float %x) {1497; CODEGEN-IEEE-SDAG-LABEL: v_recip_sqrt_f32_ulp25:1498; CODEGEN-IEEE-SDAG: ; %bb.0:1499; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1500; CODEGEN-IEEE-SDAG-NEXT: s_mov_b32 s4, 0x8000001501; CODEGEN-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01502; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc1503; CODEGEN-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11504; CODEGEN-IEEE-SDAG-NEXT: v_sqrt_f32_e32 v0, v01505; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -16, vcc1506; CODEGEN-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11507; CODEGEN-IEEE-SDAG-NEXT: v_frexp_mant_f32_e32 v1, v01508; CODEGEN-IEEE-SDAG-NEXT: v_rcp_f32_e32 v1, v11509; CODEGEN-IEEE-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v0, v01510; CODEGEN-IEEE-SDAG-NEXT: v_sub_i32_e32 v0, vcc, 0, v01511; CODEGEN-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v1, v01512; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1513;1514; CODEGEN-IEEE-GISEL-LABEL: v_recip_sqrt_f32_ulp25:1515; CODEGEN-IEEE-GISEL: ; %bb.0:1516; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1517; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0x8000001518; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11519; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc1520; CODEGEN-IEEE-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v11521; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11522; CODEGEN-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v0, v01523; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -16, vcc1524; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11525; CODEGEN-IEEE-GISEL-NEXT: v_frexp_mant_f32_e32 v1, v01526; CODEGEN-IEEE-GISEL-NEXT: v_rcp_f32_e32 v1, v11527; CODEGEN-IEEE-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v0, v01528; CODEGEN-IEEE-GISEL-NEXT: v_sub_i32_e32 v0, vcc, 0, v01529; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v1, v01530; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1531;1532; IR-IEEE-SDAG-LABEL: v_recip_sqrt_f32_ulp25:1533; IR-IEEE-SDAG: ; %bb.0:1534; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1535; IR-IEEE-SDAG-NEXT: s_mov_b32 s4, 0x8000001536; IR-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01537; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc1538; IR-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11539; IR-IEEE-SDAG-NEXT: v_sqrt_f32_e32 v0, v01540; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -16, vcc1541; IR-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11542; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01543; IR-IEEE-SDAG-NEXT: v_rcp_f32_e32 v2, v11544; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01545; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, -v1, v2, 1.01546; IR-IEEE-SDAG-NEXT: v_fma_f32 v2, v4, v2, v21547; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v4, v3, v21548; IR-IEEE-SDAG-NEXT: v_fma_f32 v5, -v1, v4, v31549; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, v5, v2, v41550; IR-IEEE-SDAG-NEXT: v_fma_f32 v1, -v1, v4, v31551; IR-IEEE-SDAG-NEXT: v_div_fmas_f32 v1, v1, v2, v41552; IR-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01553; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1554;1555; IR-IEEE-GISEL-LABEL: v_recip_sqrt_f32_ulp25:1556; IR-IEEE-GISEL: ; %bb.0:1557; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1558; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0x8000001559; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11560; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc1561; IR-IEEE-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v11562; IR-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11563; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v0, v01564; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -16, vcc1565; IR-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11566; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01567; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v11568; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01569; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.01570; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v21571; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v21572; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v31573; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v41574; IR-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v31575; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v41576; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01577; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1578;1579; CODEGEN-DAZ-LABEL: v_recip_sqrt_f32_ulp25:1580; CODEGEN-DAZ: ; %bb.0:1581; CODEGEN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1582; CODEGEN-DAZ-NEXT: v_sqrt_f32_e32 v0, v01583; CODEGEN-DAZ-NEXT: v_rcp_f32_e32 v0, v01584; CODEGEN-DAZ-NEXT: s_setpc_b64 s[30:31]1585;1586; IR-DAZ-LABEL: v_recip_sqrt_f32_ulp25:1587; IR-DAZ: ; %bb.0:1588; IR-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1589; IR-DAZ-NEXT: v_sqrt_f32_e32 v0, v01590; IR-DAZ-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01591; IR-DAZ-NEXT: v_rcp_f32_e32 v2, v11592; IR-DAZ-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01593; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31594; IR-DAZ-NEXT: v_fma_f32 v4, -v1, v2, 1.01595; IR-DAZ-NEXT: v_fma_f32 v2, v4, v2, v21596; IR-DAZ-NEXT: v_mul_f32_e32 v4, v3, v21597; IR-DAZ-NEXT: v_fma_f32 v5, -v1, v4, v31598; IR-DAZ-NEXT: v_fma_f32 v4, v5, v2, v41599; IR-DAZ-NEXT: v_fma_f32 v1, -v1, v4, v31600; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01601; IR-DAZ-NEXT: v_div_fmas_f32 v1, v1, v2, v41602; IR-DAZ-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01603; IR-DAZ-NEXT: s_setpc_b64 s[30:31]1604 %sqrt = call float @llvm.sqrt.f32(float %x), !fpmath !01605 %fdiv = fdiv float 1.0, %sqrt, !fpmath !01606 ret float %fdiv1607}1608 1609define float @v_recip_sqrt_f32_ulp25_contract(float %x) {1610; CODEGEN-IEEE-SDAG-LABEL: v_recip_sqrt_f32_ulp25_contract:1611; CODEGEN-IEEE-SDAG: ; %bb.0:1612; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1613; CODEGEN-IEEE-SDAG-NEXT: s_mov_b32 s4, 0x8000001614; CODEGEN-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01615; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 24, vcc1616; CODEGEN-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11617; CODEGEN-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v01618; CODEGEN-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 12, vcc1619; CODEGEN-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11620; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1621;1622; CODEGEN-IEEE-GISEL-LABEL: v_recip_sqrt_f32_ulp25_contract:1623; CODEGEN-IEEE-GISEL: ; %bb.0:1624; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1625; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0x8000001626; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11627; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 24, vcc1628; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11629; CODEGEN-IEEE-GISEL-NEXT: v_rsq_f32_e32 v0, v01630; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 12, vcc1631; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11632; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1633;1634; IR-IEEE-SDAG-LABEL: v_recip_sqrt_f32_ulp25_contract:1635; IR-IEEE-SDAG: ; %bb.0:1636; IR-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1637; IR-IEEE-SDAG-NEXT: s_mov_b32 s4, 0x8000001638; IR-IEEE-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01639; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc1640; IR-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11641; IR-IEEE-SDAG-NEXT: v_sqrt_f32_e32 v0, v01642; IR-IEEE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -16, vcc1643; IR-IEEE-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v11644; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01645; IR-IEEE-SDAG-NEXT: v_rcp_f32_e32 v2, v11646; IR-IEEE-SDAG-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01647; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, -v1, v2, 1.01648; IR-IEEE-SDAG-NEXT: v_fma_f32 v2, v4, v2, v21649; IR-IEEE-SDAG-NEXT: v_mul_f32_e32 v4, v3, v21650; IR-IEEE-SDAG-NEXT: v_fma_f32 v5, -v1, v4, v31651; IR-IEEE-SDAG-NEXT: v_fma_f32 v4, v5, v2, v41652; IR-IEEE-SDAG-NEXT: v_fma_f32 v1, -v1, v4, v31653; IR-IEEE-SDAG-NEXT: v_div_fmas_f32 v1, v1, v2, v41654; IR-IEEE-SDAG-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01655; IR-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1656;1657; IR-IEEE-GISEL-LABEL: v_recip_sqrt_f32_ulp25_contract:1658; IR-IEEE-GISEL: ; %bb.0:1659; IR-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1660; IR-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0x8000001661; IR-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v11662; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc1663; IR-IEEE-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v11664; IR-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11665; IR-IEEE-GISEL-NEXT: v_sqrt_f32_e32 v0, v01666; IR-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -16, vcc1667; IR-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v11668; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01669; IR-IEEE-GISEL-NEXT: v_rcp_f32_e32 v2, v11670; IR-IEEE-GISEL-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01671; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, -v1, v2, 1.01672; IR-IEEE-GISEL-NEXT: v_fma_f32 v2, v4, v2, v21673; IR-IEEE-GISEL-NEXT: v_mul_f32_e32 v4, v3, v21674; IR-IEEE-GISEL-NEXT: v_fma_f32 v5, -v1, v4, v31675; IR-IEEE-GISEL-NEXT: v_fma_f32 v4, v5, v2, v41676; IR-IEEE-GISEL-NEXT: v_fma_f32 v1, -v1, v4, v31677; IR-IEEE-GISEL-NEXT: v_div_fmas_f32 v1, v1, v2, v41678; IR-IEEE-GISEL-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01679; IR-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1680;1681; CODEGEN-DAZ-LABEL: v_recip_sqrt_f32_ulp25_contract:1682; CODEGEN-DAZ: ; %bb.0:1683; CODEGEN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1684; CODEGEN-DAZ-NEXT: v_rsq_f32_e32 v0, v01685; CODEGEN-DAZ-NEXT: s_setpc_b64 s[30:31]1686;1687; IR-DAZ-LABEL: v_recip_sqrt_f32_ulp25_contract:1688; IR-DAZ: ; %bb.0:1689; IR-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1690; IR-DAZ-NEXT: v_sqrt_f32_e32 v0, v01691; IR-DAZ-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.01692; IR-DAZ-NEXT: v_rcp_f32_e32 v2, v11693; IR-DAZ-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01694; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31695; IR-DAZ-NEXT: v_fma_f32 v4, -v1, v2, 1.01696; IR-DAZ-NEXT: v_fma_f32 v2, v4, v2, v21697; IR-DAZ-NEXT: v_mul_f32_e32 v4, v3, v21698; IR-DAZ-NEXT: v_fma_f32 v5, -v1, v4, v31699; IR-DAZ-NEXT: v_fma_f32 v4, v5, v2, v41700; IR-DAZ-NEXT: v_fma_f32 v1, -v1, v4, v31701; IR-DAZ-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01702; IR-DAZ-NEXT: v_div_fmas_f32 v1, v1, v2, v41703; IR-DAZ-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01704; IR-DAZ-NEXT: s_setpc_b64 s[30:31]1705 %sqrt = call contract float @llvm.sqrt.f32(float %x), !fpmath !01706 %fdiv = fdiv contract float 1.0, %sqrt, !fpmath !01707 ret float %fdiv1708}1709 1710define float @v_recip_sqrt_f32_afn_ulp25(float %x) {1711; CHECK-LABEL: v_recip_sqrt_f32_afn_ulp25:1712; CHECK: ; %bb.0:1713; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1714; CHECK-NEXT: v_sqrt_f32_e32 v0, v01715; CHECK-NEXT: v_rcp_f32_e32 v0, v01716; CHECK-NEXT: s_setpc_b64 s[30:31]1717 %sqrt = call afn float @llvm.sqrt.f32(float %x), !fpmath !01718 %fdiv = fdiv afn float 1.0, %sqrt, !fpmath !01719 ret float %fdiv1720}1721 1722define float @v_recip_sqrt_f32_afn_ulp25_contract(float %x) {1723; CODEGEN-IEEE-SDAG-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:1724; CODEGEN-IEEE-SDAG: ; %bb.0:1725; CODEGEN-IEEE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1726; CODEGEN-IEEE-SDAG-NEXT: v_rsq_f32_e32 v0, v01727; CODEGEN-IEEE-SDAG-NEXT: s_setpc_b64 s[30:31]1728;1729; CODEGEN-IEEE-GISEL-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:1730; CODEGEN-IEEE-GISEL: ; %bb.0:1731; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1732; CODEGEN-IEEE-GISEL-NEXT: v_rsq_f32_e32 v0, v01733; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31]1734;1735; IR-IEEE-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:1736; IR-IEEE: ; %bb.0:1737; IR-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1738; IR-IEEE-NEXT: v_sqrt_f32_e32 v0, v01739; IR-IEEE-NEXT: v_rcp_f32_e32 v0, v01740; IR-IEEE-NEXT: s_setpc_b64 s[30:31]1741;1742; CODEGEN-DAZ-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:1743; CODEGEN-DAZ: ; %bb.0:1744; CODEGEN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1745; CODEGEN-DAZ-NEXT: v_rsq_f32_e32 v0, v01746; CODEGEN-DAZ-NEXT: s_setpc_b64 s[30:31]1747;1748; IR-DAZ-LABEL: v_recip_sqrt_f32_afn_ulp25_contract:1749; IR-DAZ: ; %bb.0:1750; IR-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1751; IR-DAZ-NEXT: v_sqrt_f32_e32 v0, v01752; IR-DAZ-NEXT: v_rcp_f32_e32 v0, v01753; IR-DAZ-NEXT: s_setpc_b64 s[30:31]1754 %sqrt = call contract afn float @llvm.sqrt.f32(float %x), !fpmath !01755 %fdiv = fdiv contract afn float 1.0, %sqrt, !fpmath !01756 ret float %fdiv1757}1758 1759declare float @llvm.sqrt.f32(float)1760 1761!0 = !{float 2.500000e+00}1762