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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s3 4@lds = internal addrspace(3) global [576 x double] poison, align 165 6; Stores to the same address appear multiple places in the same7; block. When sorted by offset, the merges would fail. We should form8; two groupings of ds_write2_b64 on either side of the fence.9define amdgpu_kernel void @same_address_fence_merge_write2() #0 {10; GCN-LABEL: same_address_fence_merge_write2:11; GCN: ; %bb.0: ; %bb12; GCN-NEXT: s_mov_b32 s0, 013; GCN-NEXT: v_lshlrev_b32_e32 v2, 3, v014; GCN-NEXT: s_mov_b32 s1, 0x4010000015; GCN-NEXT: v_mov_b32_e32 v0, s016; GCN-NEXT: v_mov_b32_e32 v1, s117; GCN-NEXT: v_add_u32_e32 v3, 0x800, v218; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:6619; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:19820; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:8 offset1:7421; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:140 offset1:20622; GCN-NEXT: s_mov_b32 s1, 0x3ff0000023; GCN-NEXT: v_mov_b32_e32 v0, s024; GCN-NEXT: v_mov_b32_e32 v1, s125; GCN-NEXT: s_waitcnt lgkmcnt(0)26; GCN-NEXT: s_barrier27; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:6628; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:19829; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:8 offset1:7430; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:140 offset1:20631; GCN-NEXT: s_endpgm32bb:33 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !034 %tmp1 = getelementptr inbounds [576 x double], ptr addrspace(3) @lds, i32 0, i32 %tmp35 store double 4.000000e+00, ptr addrspace(3) %tmp1, align 836 %tmp2 = getelementptr inbounds double, ptr addrspace(3) %tmp1, i32 6637 store double 4.000000e+00, ptr addrspace(3) %tmp2, align 838 %tmp3 = getelementptr inbounds double, ptr addrspace(3) %tmp1, i32 13239 store double 4.000000e+00, ptr addrspace(3) %tmp3, align 840 %tmp4 = getelementptr inbounds double, ptr addrspace(3) %tmp1, i32 19841 store double 4.000000e+00, ptr addrspace(3) %tmp4, align 842 %tmp5 = getelementptr inbounds double, ptr addrspace(3) %tmp1, i32 26443 store double 4.000000e+00, ptr addrspace(3) %tmp5, align 844 %tmp6 = getelementptr inbounds double, ptr addrspace(3) %tmp1, i32 33045 store double 4.000000e+00, ptr addrspace(3) %tmp6, align 846 %tmp7 = getelementptr inbounds double, ptr addrspace(3) %tmp1, i32 39647 store double 4.000000e+00, ptr addrspace(3) %tmp7, align 848 %tmp8 = getelementptr inbounds double, ptr addrspace(3) %tmp1, i32 46249 store double 4.000000e+00, ptr addrspace(3) %tmp8, align 850 fence syncscope("workgroup") release51 tail call void @llvm.amdgcn.s.barrier()52 fence syncscope("workgroup") acquire53 store double 1.000000e+00, ptr addrspace(3) %tmp1, align 854 store double 1.000000e+00, ptr addrspace(3) %tmp2, align 855 store double 1.000000e+00, ptr addrspace(3) %tmp3, align 856 store double 1.000000e+00, ptr addrspace(3) %tmp4, align 857 store double 1.000000e+00, ptr addrspace(3) %tmp5, align 858 store double 1.000000e+00, ptr addrspace(3) %tmp6, align 859 store double 1.000000e+00, ptr addrspace(3) %tmp7, align 860 store double 1.000000e+00, ptr addrspace(3) %tmp8, align 861 ret void62}63 64declare i32 @llvm.amdgcn.workitem.id.x() #065declare void @llvm.amdgcn.s.barrier() #166 67attributes #0 = { nounwind readnone speculatable }68attributes #1 = { convergent nounwind }69 70!0 = !{i32 0, i32 1024}71