74 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s3 4---5name: v_s_exp_f166body: |7 bb.0.entry:8 ; GCN-LABEL: name: v_s_exp_f169 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF10 ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec11 ; GCN-NEXT: [[V_EXP_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F16_fake16_e64 1, [[V_CVT_F32_U32_e64_]], 1, 1, implicit $mode, implicit $exec12 %0:vgpr_32 = IMPLICIT_DEF13 %1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec14 %2:sreg_32 = COPY %1:vgpr_3215 %3:sreg_32_xexec = V_S_EXP_F16_e64 1, %2:sreg_32, 1, 1, implicit $mode, implicit $exec16...17 18---19name: v_s_log_f1620body: |21 bb.0.entry:22 ; GCN-LABEL: name: v_s_log_f1623 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF24 ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec25 ; GCN-NEXT: [[V_LOG_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_LOG_F16_fake16_e64 1, [[V_CVT_F32_U32_e64_]], 1, 1, implicit $mode, implicit $exec26 %0:vgpr_32 = IMPLICIT_DEF27 %1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec28 %2:sreg_32 = COPY %1:vgpr_3229 %3:sreg_32_xexec = V_S_LOG_F16_e64 1, %2:sreg_32, 1, 1, implicit $mode, implicit $exec30...31 32---33name: v_s_rcp_f1634body: |35 bb.0.entry:36 ; GCN-LABEL: name: v_s_rcp_f1637 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF38 ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec39 ; GCN-NEXT: [[V_RCP_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_fake16_e64 1, [[V_CVT_F32_U32_e64_]], 1, 1, implicit $mode, implicit $exec40 %0:vgpr_32 = IMPLICIT_DEF41 %1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec42 %2:sreg_32 = COPY %1:vgpr_3243 %3:sreg_32_xexec = V_S_RCP_F16_e64 1, %2:sreg_32, 1, 1, implicit $mode, implicit $exec44...45 46---47name: v_s_rsq_f1648body: |49 bb.0.entry:50 ; GCN-LABEL: name: v_s_rsq_f1651 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF52 ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec53 ; GCN-NEXT: [[V_RSQ_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_fake16_e64 1, [[V_CVT_F32_U32_e64_]], 1, 1, implicit $mode, implicit $exec54 %0:vgpr_32 = IMPLICIT_DEF55 %1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec56 %2:sreg_32 = COPY %1:vgpr_3257 %3:sreg_32_xexec = V_S_RSQ_F16_e64 1, %2:sreg_32, 1, 1, implicit $mode, implicit $exec58...59 60---61name: v_s_sqrt_f1662body: |63 bb.0.entry:64 ; GCN-LABEL: name: v_s_sqrt_f1665 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF66 ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec67 ; GCN-NEXT: [[V_SQRT_F16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_SQRT_F16_fake16_e64 1, [[V_CVT_F32_U32_e64_]], 1, 1, implicit $mode, implicit $exec68 %0:vgpr_32 = IMPLICIT_DEF69 %1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec70 %2:sreg_32 = COPY %1:vgpr_3271 %3:sreg_32_xexec = V_S_SQRT_F16_e64 1, %2:sreg_32, 1, 1, implicit $mode, implicit $exec72...73 74