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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s3 4define amdgpu_gs void @f(i32 inreg %arg, i32 %arg1, i32 %arg2) {5; CHECK-LABEL: f:6; CHECK: ; %bb.0: ; %bb7; CHECK-NEXT: s_cmp_eq_u32 s0, 08; CHECK-NEXT: s_mov_b32 s0, 09; CHECK-NEXT: s_cbranch_scc1 .LBB0_210; CHECK-NEXT: ; %bb.1: ; %bb311; CHECK-NEXT: v_mov_b32_e32 v2, v012; CHECK-NEXT: s_branch .LBB0_313; CHECK-NEXT: .LBB0_2:14; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 115; CHECK-NEXT: .LBB0_3: ; %bb416; CHECK-NEXT: v_mov_b32_e32 v3, 017; CHECK-NEXT: s_mov_b32 s1, s018; CHECK-NEXT: s_mov_b32 s2, s019; CHECK-NEXT: s_mov_b32 s3, s020; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)21; CHECK-NEXT: v_mov_b32_e32 v4, v322; CHECK-NEXT: v_mov_b32_e32 v5, v323; CHECK-NEXT: buffer_store_b128 v[2:5], v3, s[0:3], 0 idxen24; CHECK-NEXT: v_mov_b32_e32 v2, v325; CHECK-NEXT: buffer_store_b128 v[1:4], v3, s[0:3], 0 idxen26; CHECK-NEXT: s_endpgm27bb:28 %i = icmp eq i32 %arg, 029 br i1 %i, label %bb4, label %bb330 31bb3:32 br label %bb433 34bb4:35 %i5 = phi i32 [ %arg1, %bb3 ], [ 1, %bb ]36 %i6 = phi i32 [ %arg2, %bb3 ], [ 0, %bb ]37 %i7 = insertelement <4 x i32> zeroinitializer, i32 %i5, i64 038 %i8 = bitcast <4 x i32> %i7 to <4 x float>39 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %i8, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)40 %i9 = insertelement <4 x i32> zeroinitializer, i32 %i6, i64 041 %i10 = bitcast <4 x i32> %i9 to <4 x float>42 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %i10, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)43 ret void44}45 46declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg)47