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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s3---4name: issue1306465tracksRegLiveness: true6body: |7 ; CHECK-LABEL: name: issue1306468 ; CHECK: bb.0:9 ; CHECK-NEXT: successors: %bb.3(0x80000000)10 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1_vgpr2, $sgpr8_sgpr9, $sgpr1011 ; CHECK-NEXT: {{ $}}12 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr013 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr914 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr215 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1016 ; CHECK-NEXT: S_BRANCH %bb.317 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: bb.1:19 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)20 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI %13, %bb.3, %5, %bb.422 ; CHECK-NEXT: S_CMP_LG_U32 1, 1, implicit-def $scc23 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc24 ; CHECK-NEXT: S_BRANCH %bb.225 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: bb.2:27 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]]28 ; CHECK-NEXT: SI_RETURN implicit $vgpr029 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: bb.3:31 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_64 = PHI [[COPY1]], %bb.0, [[PHI]], %bb.134 ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 035 ; CHECK-NEXT: S_CMP_EQ_U64 [[PHI1]], killed [[S_MOV_B64_]], implicit-def $scc36 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub037 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec38 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub139 ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec40 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub141 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc42 ; CHECK-NEXT: S_BRANCH %bb.443 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: bb.4:45 ; CHECK-NEXT: successors: %bb.1(0x80000000)46 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[PHI1]], [[COPY3]], implicit-def dead $scc48 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_LSHR_B64_]].sub149 ; CHECK-NEXT: [[S_LSHR_B64_1:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[PHI1]], killed [[COPY6]], implicit-def dead $scc50 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_LSHR_B64_1]].sub151 ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 killed [[COPY7]], [[COPY3]], implicit-def dead $scc52 ; CHECK-NEXT: [[S_LSHR_B64_2:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[PHI1]], killed [[S_OR_B32_]], implicit-def dead $scc53 ; CHECK-NEXT: S_BRANCH %bb.154 bb.0:55 liveins: $vgpr0, $vgpr1_vgpr2, $sgpr8_sgpr9, $sgpr1056 57 %0:vgpr_32 = COPY $vgpr058 %1:sreg_64 = COPY $sgpr8_sgpr959 %2:vreg_64 = COPY $vgpr1_vgpr260 %3:sreg_32 = COPY $sgpr1061 S_BRANCH %bb.362 63 bb.1:64 %4:sreg_64 = PHI %2, %bb.3, %5, %bb.465 S_CMP_LG_U32 1, 1, implicit-def $scc66 S_CBRANCH_SCC1 %bb.3, implicit $scc67 S_BRANCH %bb.268 69 bb.2:70 $vgpr0 = COPY %071 SI_RETURN implicit $vgpr072 73 bb.3:74 %6:sreg_64 = PHI %1, %bb.0, %4, %bb.175 %7:sreg_64 = S_MOV_B64 076 S_CMP_EQ_U64 %6, killed %7, implicit-def $scc77 S_CBRANCH_SCC1 %bb.1, implicit $scc78 S_BRANCH %bb.479 80 bb.4:81 %8:sreg_64 = S_LSHR_B64 %6, %3, implicit-def dead $scc82 %9:sreg_32 = COPY %8.sub183 %10:sreg_64 = S_LSHR_B64 %6, killed %9, implicit-def dead $scc84 %11:sreg_32 = COPY %10.sub185 %12:sreg_32 = S_OR_B32 killed %11, %3, implicit-def dead $scc86 %5:sreg_64 = S_LSHR_B64 %6, killed %12, implicit-def dead $scc87 S_BRANCH %bb.188 89...90