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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s3 4; SIFixSGPRCopies will insert a readfirstlane from an AV source5; register, which needs to be constrained by VGPR to satisfy the6; operand constraint.7 8define amdgpu_kernel void @constrain_readfirstlane_av(i64 %arg, ptr addrspace(1) %ptr) {9; CHECK-LABEL: constrain_readfirstlane_av:10; CHECK: ; %bb.0: ; %bb11; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x012; CHECK-NEXT: v_mov_b32_e32 v0, 013; CHECK-NEXT: s_mov_b32 s5, 014; CHECK-NEXT: s_mov_b64 s[6:7], 015; CHECK-NEXT: s_and_b64 vcc, exec, -116; CHECK-NEXT: s_waitcnt lgkmcnt(0)17; CHECK-NEXT: global_load_ushort v1, v0, s[2:3] glc18; CHECK-NEXT: s_waitcnt vmcnt(0)19; CHECK-NEXT: v_readfirstlane_b32 s4, v120; CHECK-NEXT: s_and_b32 s4, s4, 0xffff21; CHECK-NEXT: .LBB0_1: ; %bb1622; CHECK-NEXT: ; =>This Inner Loop Header: Depth=123; CHECK-NEXT: s_mul_i32 s8, s6, s124; CHECK-NEXT: s_mul_hi_u32 s9, s6, s025; CHECK-NEXT: s_mul_i32 s7, s7, s026; CHECK-NEXT: s_add_i32 s8, s9, s827; CHECK-NEXT: s_mul_i32 s6, s6, s028; CHECK-NEXT: s_add_i32 s7, s8, s729; CHECK-NEXT: s_lshl_b64 s[6:7], s[6:7], 530; CHECK-NEXT: s_add_u32 s6, s2, s631; CHECK-NEXT: s_addc_u32 s7, s3, s732; CHECK-NEXT: global_load_dword v1, v0, s[6:7] glc33; CHECK-NEXT: s_waitcnt vmcnt(0)34; CHECK-NEXT: s_mov_b64 s[6:7], s[4:5]35; CHECK-NEXT: s_mov_b64 vcc, vcc36; CHECK-NEXT: s_cbranch_vccnz .LBB0_137; CHECK-NEXT: ; %bb.2: ; %DummyReturnBlock38; CHECK-NEXT: s_endpgm39bb:40 %i = load volatile i16, ptr addrspace(1) %ptr, align 241 %i6 = zext i16 %i to i6442 br label %bb1643 44bb16: ; preds = %bb16, %bb45 %i17 = phi i64 [ %i6, %bb16 ], [ 0, %bb ]46 %i23 = mul i64 %i17, %arg47 %i25.split = getelementptr [16 x half], ptr addrspace(1) %ptr, i64 %i2348 %i27 = load volatile <2 x half>, ptr addrspace(1) %i25.split, align 1649 br label %bb1650}51 52define void @av_class_to_m0(ptr addrspace(1) %ptr) {53; CHECK-LABEL: av_class_to_m0:54; CHECK: ; %bb.0:55; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; CHECK-NEXT: global_load_dword v0, v[0:1], off57; CHECK-NEXT: s_waitcnt vmcnt(0)58; CHECK-NEXT: v_readfirstlane_b32 s4, v059; CHECK-NEXT: s_mov_b32 m0, s460; CHECK-NEXT: ;;#ASMSTART61; CHECK-NEXT: ; use m062; CHECK-NEXT: ;;#ASMEND63; CHECK-NEXT: s_setpc_b64 s[30:31]64 %load = load i32, ptr addrspace(1) %ptr65 call void asm sideeffect "; use $0", "{m0}"(i32 %load)66 ret void67}68