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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s3 4@lds = external local_unnamed_addr addrspace(3) global [4 x float], align 45 6; expect readfirstlane to pick the 32bit register7define amdgpu_gs i32 @vgpr16_copyto_sgpr() {8; CHECK-LABEL: vgpr16_copyto_sgpr:9; CHECK: ; %bb.0: ; %entry10; CHECK-NEXT: v_mov_b32_e32 v0, lds@abs32@lo11; CHECK-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:112; CHECK-NEXT: s_waitcnt lgkmcnt(0)13; CHECK-NEXT: v_cvt_f16_f32_e32 v0.l, v014; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)15; CHECK-NEXT: v_readfirstlane_b32 s0, v016; CHECK-NEXT: s_and_b32 s0, 0xffff, s017; CHECK-NEXT: s_mul_i32 s0, s0, 518; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)19; CHECK-NEXT: s_cmp_lg_u32 s0, 220; CHECK-NEXT: s_cbranch_scc1 .LBB0_221; CHECK-NEXT: ; %bb.1: ; %a122; CHECK-NEXT: s_mov_b32 s0, 123; CHECK-NEXT: s_branch .LBB0_324; CHECK-NEXT: .LBB0_2: ; %a225; CHECK-NEXT: s_mov_b32 s0, 226; CHECK-NEXT: s_branch .LBB0_327; CHECK-NEXT: .LBB0_3:28entry:29 %ptr = load <4 x float>, ptr addrspace(3) @lds, align 430 %f = extractelement <4 x float> %ptr, i32 031 %half = fptrunc float %f to half32 %i16 = bitcast half %half to i1633 %i32 = zext i16 %i16 to i3234 %add = add i32 %i32, 135 %mul = mul i32 %add, 536 %icmp = icmp eq i32 %mul, 737 br i1 %icmp, label %a1, label %a238 39a1:40 ret i32 141 42a2:43 ret i32 244}45