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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s3 4define amdgpu_gs i32 @main() {5; CHECK-LABEL: main:6; CHECK: ; %bb.0: ; %bb7; CHECK-NEXT: s_bitcmp1_b32 0, 08; CHECK-NEXT: s_mov_b32 s0, 09; CHECK-NEXT: s_cselect_b32 s1, -1, 010; CHECK-NEXT: s_or_saveexec_b32 s2, -111; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s112; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)13; CHECK-NEXT: v_readfirstlane_b32 s1, v014; CHECK-NEXT: s_mov_b32 exec_lo, s215; CHECK-NEXT: s_or_b32 s0, s0, s116; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)17; CHECK-NEXT: s_bitcmp1_b32 s0, 018; CHECK-NEXT: s_cselect_b32 s0, -1, 019; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)20; CHECK-NEXT: s_xor_b32 s0, s0, -121; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)22; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s023; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)24; CHECK-NEXT: v_readfirstlane_b32 s0, v125; CHECK-NEXT: s_wait_alu depctr_va_sdst(0)26; CHECK-NEXT: ; return to shader part epilog27bb:28 %i = call i1 @llvm.amdgcn.readfirstlane.i1(i1 false)29 br label %bb130 31bb1:32 %i2 = zext i1 %i to i3233 %i3 = call i32 @llvm.amdgcn.wwm.i32(i32 0)34 %i4 = call i32 @llvm.amdgcn.wwm.i32(i32 %i2)35 %i5 = trunc i32 %i4 to i136 %i6 = trunc i32 %i3 to i137 %i7 = or i1 %i6, %i538 %i8 = select i1 %i7, i32 0, i32 139 ret i32 %i840}41