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1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s3 4# GCN-LABEL: name: fix-sgpr-copies5# GCN: V_ADD_CO_U32_e326# GCN: V_ADDC_U32_e327---8name: fix-sgpr-copies9body: |10 bb.0:11 %0:vgpr_32 = IMPLICIT_DEF12 %1:sreg_32 = IMPLICIT_DEF13 %2:sreg_32 = IMPLICIT_DEF14 %3:sreg_32 = IMPLICIT_DEF15 %4:vgpr_32 = V_CVT_U32_F32_e64 0, %0:vgpr_32, 0, 0, implicit $mode, implicit $exec16 %5:sreg_32 = COPY %4:vgpr_3217 %6:sreg_32 = S_ADD_I32 %2:sreg_32, %5:sreg_32, implicit-def $scc18 %7:sreg_32 = S_ADDC_U32 %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $scc19...20 21# Test to ensure i1 phi copies from scalar registers through another phi won't22# be promoted into vector ones.23# GCN-LABEL: name: fix-sgpr-i1-phi-copies24# GCN: .8:25# GCN-NOT: vreg_64 = PHI26---27name: fix-sgpr-i1-phi-copies28tracksRegLiveness: true29body: |30 bb.9:31 S_BRANCH %bb.032 33 bb.4:34 S_CBRANCH_SCC1 %bb.6, implicit undef $scc35 36 bb.5:37 %3:vreg_1 = IMPLICIT_DEF38 39 bb.6:40 %4:vreg_1 = PHI %2:sreg_64, %bb.4, %3:vreg_1, %bb.541 42 bb.7:43 %5:vreg_1 = PHI %2:sreg_64, %bb.3, %4:vreg_1, %bb.644 S_BRANCH %bb.845 46 bb.0:47 S_CBRANCH_SCC1 %bb.2, implicit undef $scc48 49 bb.1:50 %0:sreg_64 = S_MOV_B64 051 S_BRANCH %bb.352 53 bb.2:54 %1:sreg_64 = S_MOV_B64 -155 S_BRANCH %bb.356 57 bb.3:58 %2:sreg_64 = PHI %0:sreg_64, %bb.1, %1:sreg_64, %bb.259 S_CBRANCH_SCC1 %bb.7, implicit undef $scc60 S_BRANCH %bb.461 62 bb.8:63...64 65# Avoid infinite loop in SIInstrInfo::legalizeGenericOperand when checking for ImpDef.66# GCN-LABEL: name: legalize-operand-search-each-def-once67# GCN-NOT: sreg_64 PHI68---69name: legalize-operand-search-each-def-once70tracksRegLiveness: true71body: |72 bb.0:73 successors: %bb.1, %bb.274 liveins: $sgpr0_sgpr175 76 %0:sgpr_64 = COPY $sgpr0_sgpr177 S_CBRANCH_VCCZ %bb.2, implicit undef $vcc78 S_BRANCH %bb.179 80 bb.1:81 %1:vreg_64 = IMPLICIT_DEF82 S_BRANCH %bb.283 84 bb.2:85 %2:sgpr_64 = PHI %0, %bb.0, %1, %bb.186 $sgpr0_sgpr1 = COPY %087...88 89# A REG_SEQUENCE that uses registers defined by both a PHI and a COPY could90# result in an endless search.91# GCN-LABEL: name: process-phi-search-each-use-once92# GCN-NOT: sreg_32 PHI93---94name: process-phi-search-each-use-once95tracksRegLiveness: true96body: |97 bb.0:98 successors: %bb.1, %bb.299 liveins: $vgpr3100 101 %0:vgpr_32 = COPY $vgpr3102 S_CBRANCH_VCCZ %bb.2, implicit undef $vcc103 S_BRANCH %bb.1104 105 bb.1:106 %1:sgpr_32 = IMPLICIT_DEF107 S_BRANCH %bb.2108 109 bb.2:110 %2:sgpr_32 = PHI %0, %bb.0, %1, %bb.1111 %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %0, %subreg.sub1112 $vgpr3 = COPY %3.sub0113...114 115# Test to ensure that undef SCC gets properly propagated.116# GCN-LABEL: name: scc_undef117# GCN: S_CSELECT_B64 -1, 0, implicit undef $scc118# GCN: V_CNDMASK119---120name: scc_undef121tracksRegLiveness: true122 123body: |124 bb.0:125 %1:vgpr_32 = IMPLICIT_DEF126 %2:sreg_32 = S_MOV_B32 1127 %3:sreg_32 = COPY %1:vgpr_32128 %4:sreg_32 = S_CSELECT_B32 killed %2:sreg_32, killed %3:sreg_32, implicit undef $scc129...130 131---132# Test that the VGPR immediate is replaced with an SGPR one.133# GCN-LABEL: name: reg_sequence_vgpr_immediate134# GCN: [[A_SGPR:%[0-9]+]]:sreg_32 = IMPLICIT_DEF135# GCN-NEXT: [[VGPR_CONST:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 37136# GCN-NEXT: [[SGPR_CONST:%[0-9]+]]:sgpr_32 = S_MOV_B32 37137# GCN-NEXT: {{%[0-9]+}}:sreg_64 = REG_SEQUENCE [[SGPR_CONST]], %subreg.sub0, [[A_SGPR]], %subreg.sub1138name: reg_sequence_vgpr_immediate139body: |140 bb.0:141 %0:sreg_32 = IMPLICIT_DEF142 %1:vgpr_32 = V_MOV_B32_e32 37, implicit $exec143 %2:sreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, %0:sreg_32, %subreg.sub1144 145 %3:vgpr_32 = V_ADD_U32_e32 %1:vgpr_32, %1:vgpr_32, implicit $exec146...147 148---149# GCN-LABEL: name: insert_subreg_vgpr_immediate150# GCN: [[DST:%[0-9]+]]:sgpr_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2151# GCN-NEXT: [[SGPR_CONST:%[0-9]+]]:sgpr_32 = S_MOV_B32 43152# GCN-NEXT: {{%[0-9]+}}:sgpr_128 = INSERT_SUBREG [[DST]], [[SGPR_CONST]], %subreg.sub3153name: insert_subreg_vgpr_immediate154body: |155 bb.0:156 %0:sgpr_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2157 %1:vgpr_32 = V_MOV_B32_e32 43, implicit $exec158 %2:sgpr_128 = INSERT_SUBREG %0, %1, %subreg.sub3159...160 161---162# GCN-LABEL: name: phi_vgpr_immediate163# GCN: bb.1:164# GCN: [[SGPR:%[0-9]+]]:sgpr_32 = S_MOV_B32 51165# GCN: bb.2:166# GCN: IMPLICIT_DEF167# GCN: bb.3:168# GCN: sreg_32 = PHI [[SGPR]], %bb.1169name: phi_vgpr_immediate170tracksRegLiveness: true171body: |172 bb.0:173 S_CBRANCH_SCC1 %bb.2, implicit undef $scc174 175 bb.1:176 %0:vgpr_32 = V_MOV_B32_e32 51, implicit $exec177 S_BRANCH %bb.3178 179 bb.2:180 %1:sreg_32 = IMPLICIT_DEF181 S_BRANCH %bb.3182 183 bb.3:184 %2:sreg_32 = PHI %0:vgpr_32, %bb.1, %1:sreg_32, %bb.2185 186---187name: cmp_f32188body: |189 bb.0:190 ; GCN-LABEL: name: cmp_f32191 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF192 ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF193 ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec194 ; GCN-NEXT: %6:sreg_64_xexec = nofpexcept V_CMP_LT_F32_e64 0, [[V_CVT_F32_U32_e64_]], 0, [[DEF1]], 0, implicit $mode, implicit $exec195 ; GCN-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %6, implicit $exec196 %0:vgpr_32 = IMPLICIT_DEF197 %1:sreg_32 = IMPLICIT_DEF198 %2:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec199 %3:sreg_32 = COPY %2:vgpr_32200 nofpexcept S_CMP_LT_F32 killed %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $mode201 %4:sreg_64_xexec = COPY $scc202 %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %4, implicit $exec203...204 205# Test to ensure that src2 of fmac is moved to vgpr206---207name: fmac_f32208body: |209 bb.0:210 ; GCN-LABEL: name: fmac_f32211 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF212 ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF213 ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF214 ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec215 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]216 ; GCN-NEXT: %6:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[V_CVT_F32_U32_e64_]], 0, [[DEF1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec217 %0:vgpr_32 = IMPLICIT_DEF218 %1:sreg_32 = IMPLICIT_DEF219 %2:sreg_32 = IMPLICIT_DEF220 %3:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec221 %4:sreg_32 = COPY %3:vgpr_32222 %5:sreg_32 = nofpexcept S_FMAC_F32 killed %4:sreg_32, %1:sreg_32, %2:sreg_32, implicit $mode223...224 225---226# GCN-LABEL: name: moveimm_subreg_input227# GCN: %0:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec228# GCN: :vgpr_32 = COPY %0.sub0229name: moveimm_subreg_input230body: |231 bb.0:232 %0:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec233 %1:sreg_32 = COPY %0.sub0234...235 236---237# GCN-LABEL: name: s_cselect_b64238# GCN: %0:vgpr_32 = IMPLICIT_DEF239# GCN: %1:vreg_64 = IMPLICIT_DEF240# GCN: %7:sreg_64_xexec = V_CMP_EQ_U32_e64 %0, 0, implicit $exec241# GCN: %6:vreg_64 = V_CNDMASK_B64_PSEUDO 0, %1, %7, implicit $exec242name: s_cselect_b64243body: |244 bb.0:245 %0:vgpr_32 = IMPLICIT_DEF246 %1:vreg_64 = IMPLICIT_DEF247 %2:sreg_32 = COPY %0248 %3:sreg_64 = COPY %1249 S_CMP_EQ_U32 %2, 0, implicit-def $scc250 %4:sreg_64 = S_CSELECT_B64 %3, 0, implicit $scc251...252## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:253# GCN: {{.*}}254