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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s3 4; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead.5 6define amdgpu_hs void @wwm(i32 inreg %arg, ptr addrspace(8) inreg %buffer) {7; GCN-LABEL: wwm:8; GCN: ; %bb.0: ; %entry9; GCN-NEXT: s_mov_b32 s6, s310; GCN-NEXT: s_mov_b32 s5, s211; GCN-NEXT: s_or_saveexec_b64 s[2:3], -112; GCN-NEXT: s_mov_b32 s7, s413; GCN-NEXT: s_mov_b32 s4, s114; GCN-NEXT: s_mov_b32 s1, 115; GCN-NEXT: v_cndmask_b32_e64 v0, 1, 4, s[2:3]16; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v017; GCN-NEXT: s_mov_b64 exec, s[2:3]18; GCN-NEXT: s_cmp_lg_u32 s0, 019; GCN-NEXT: v_mov_b32_e32 v1, v020; GCN-NEXT: s_cbranch_scc0 .LBB0_221; GCN-NEXT: ; %bb.1: ; %bb4222; GCN-NEXT: s_mov_b32 s1, 023; GCN-NEXT: .LBB0_2: ; %bb60224; GCN-NEXT: v_cmp_ne_u32_e32 vcc, s1, v125; GCN-NEXT: s_cbranch_vccnz .LBB0_426; GCN-NEXT: ; %bb.3: ; %bb4927; GCN-NEXT: v_mov_b32_e32 v1, 1.028; GCN-NEXT: tbuffer_store_format_x v1, off, s[4:7], 1 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] offset:4 glc29; GCN-NEXT: .LBB0_4: ; %bb5430; GCN-NEXT: s_endpgm31entry:32 br label %work33 34bb42:35 br label %bb60236 37bb602:38 %tmp603 = phi i32 [ 0, %bb42 ], [ 1, %work ]39 %tmp607 = icmp eq i32 %tmp603, %tmp119640 br i1 %tmp607, label %bb49, label %bb5441 42bb49:43 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float 1.0, ptr addrspace(8) %buffer, i32 4, i32 1, i32 116, i32 1)44 ret void45 46bb54:47 ret void48 49work:50 %tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)51 52 %tmp1191 = mul i32 %tmp1189, 453 54 %tmp1196 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp1191)55 56 %tmp34 = icmp eq i32 %arg, 057 br i1 %tmp34, label %bb602, label %bb4258}59 60define amdgpu_hs void @strict_wwm(i32 inreg %arg, ptr addrspace(8) inreg %buffer) {61; GCN-LABEL: strict_wwm:62; GCN: ; %bb.0: ; %entry63; GCN-NEXT: s_mov_b32 s6, s364; GCN-NEXT: s_mov_b32 s5, s265; GCN-NEXT: s_or_saveexec_b64 s[2:3], -166; GCN-NEXT: s_mov_b32 s7, s467; GCN-NEXT: s_mov_b32 s4, s168; GCN-NEXT: s_mov_b32 s1, 169; GCN-NEXT: v_cndmask_b32_e64 v0, 1, 4, s[2:3]70; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v071; GCN-NEXT: s_mov_b64 exec, s[2:3]72; GCN-NEXT: s_cmp_lg_u32 s0, 073; GCN-NEXT: v_mov_b32_e32 v1, v074; GCN-NEXT: s_cbranch_scc0 .LBB1_275; GCN-NEXT: ; %bb.1: ; %bb4276; GCN-NEXT: s_mov_b32 s1, 077; GCN-NEXT: .LBB1_2: ; %bb60278; GCN-NEXT: v_cmp_ne_u32_e32 vcc, s1, v179; GCN-NEXT: s_cbranch_vccnz .LBB1_480; GCN-NEXT: ; %bb.3: ; %bb4981; GCN-NEXT: v_mov_b32_e32 v1, 1.082; GCN-NEXT: tbuffer_store_format_x v1, off, s[4:7], 1 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] offset:4 glc83; GCN-NEXT: .LBB1_4: ; %bb5484; GCN-NEXT: s_endpgm85entry:86 br label %work87 88bb42:89 br label %bb60290 91bb602:92 %tmp603 = phi i32 [ 0, %bb42 ], [ 1, %work ]93 %tmp607 = icmp eq i32 %tmp603, %tmp119694 br i1 %tmp607, label %bb49, label %bb5495 96bb49:97 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float 1.0, ptr addrspace(8) %buffer, i32 4, i32 1, i32 116, i32 1)98 ret void99 100bb54:101 ret void102 103work:104 %tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)105 106 %tmp1191 = mul i32 %tmp1189, 4107 108 %tmp1196 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp1191)109 110 %tmp34 = icmp eq i32 %arg, 0111 br i1 %tmp34, label %bb602, label %bb42112}113 114declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0115declare i32 @llvm.amdgcn.wwm.i32(i32) #1116declare i32 @llvm.amdgcn.strict.wwm.i32(i32) #1117declare void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float, ptr addrspace(8), i32, i32, i32 immarg, i32 immarg) #2118 119attributes #0 = { convergent nounwind readnone willreturn }120attributes #1 = { convergent nounwind readnone speculatable willreturn }121attributes #2 = { nounwind willreturn memory(argmem: write) }122