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1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,CIVI %s2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,CIVI %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,CIVI,CIVI-HSA %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10PLUS %s6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,GFX10PLUS,GFX11-FAKE16 %s8 9; GCN-LABEL: {{^}}store_flat_i32:10; GCN-DAG: s_load_{{dwordx2|b64}} s[[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]],11; GCN-DAG: s_load_{{dword|b32}} s[[SDATA:[0-9]+]],12; GCN: s_waitcnt lgkmcnt(0)13; GCN-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]]14; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]15; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]16; GCN: flat_store_{{dword|b32}} v[[[LO_VREG]]:[[HI_VREG]]], v[[DATA]]17define amdgpu_kernel void @store_flat_i32(ptr addrspace(1) %gptr, i32 %x) #0 {18 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr19 store volatile i32 %x, ptr %fptr, align 420 ret void21}22 23; GCN-LABEL: {{^}}store_flat_i64:24; GCN: flat_store_{{dword|b64}}25define amdgpu_kernel void @store_flat_i64(ptr addrspace(1) %gptr, i64 %x) #0 {26 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr27 store volatile i64 %x, ptr %fptr, align 828 ret void29}30 31; GCN-LABEL: {{^}}store_flat_v4i32:32; GCN: flat_store_{{dword|b128}}33define amdgpu_kernel void @store_flat_v4i32(ptr addrspace(1) %gptr, <4 x i32> %x) #0 {34 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr35 store volatile <4 x i32> %x, ptr %fptr, align 1636 ret void37}38 39; GCN-LABEL: {{^}}store_flat_trunc_i16:40; GCN: flat_store_{{short|b16}}41define amdgpu_kernel void @store_flat_trunc_i16(ptr addrspace(1) %gptr, i32 %x) #0 {42 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr43 %y = trunc i32 %x to i1644 store volatile i16 %y, ptr %fptr, align 245 ret void46}47 48; GCN-LABEL: {{^}}store_flat_trunc_i8:49; GCN: flat_store_{{byte|b8}}50define amdgpu_kernel void @store_flat_trunc_i8(ptr addrspace(1) %gptr, i32 %x) #0 {51 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr52 %y = trunc i32 %x to i853 store volatile i8 %y, ptr %fptr, align 254 ret void55}56 57 58 59; GCN-LABEL: load_flat_i32:60; GCN: flat_load_{{dword|b32}}61define amdgpu_kernel void @load_flat_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {62 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr63 %fload = load volatile i32, ptr %fptr, align 464 store i32 %fload, ptr addrspace(1) %out, align 465 ret void66}67 68; GCN-LABEL: load_flat_i64:69; GCN: flat_load_{{dword|b64}}70define amdgpu_kernel void @load_flat_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {71 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr72 %fload = load volatile i64, ptr %fptr, align 873 store i64 %fload, ptr addrspace(1) %out, align 874 ret void75}76 77; GCN-LABEL: load_flat_v4i32:78; GCN: flat_load_{{dword|b128}}79define amdgpu_kernel void @load_flat_v4i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {80 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr81 %fload = load volatile <4 x i32>, ptr %fptr, align 3282 store <4 x i32> %fload, ptr addrspace(1) %out, align 883 ret void84}85 86; GCN-LABEL: sextload_flat_i8:87; GCN: flat_load_{{sbyte|i8}}88define amdgpu_kernel void @sextload_flat_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {89 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr90 %fload = load volatile i8, ptr %fptr, align 491 %ext = sext i8 %fload to i3292 store i32 %ext, ptr addrspace(1) %out, align 493 ret void94}95 96; GCN-LABEL: zextload_flat_i8:97; GCN: flat_load_{{ubyte|u8}}98define amdgpu_kernel void @zextload_flat_i8(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {99 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr100 %fload = load volatile i8, ptr %fptr, align 4101 %ext = zext i8 %fload to i32102 store i32 %ext, ptr addrspace(1) %out, align 4103 ret void104}105 106; GCN-LABEL: sextload_flat_i16:107; GCN: flat_load_{{sshort|i16}}108define amdgpu_kernel void @sextload_flat_i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {109 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr110 %fload = load volatile i16, ptr %fptr, align 4111 %ext = sext i16 %fload to i32112 store i32 %ext, ptr addrspace(1) %out, align 4113 ret void114}115 116; GCN-LABEL: zextload_flat_i16:117; GCN: flat_load_{{ushort|u16}}118define amdgpu_kernel void @zextload_flat_i16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %gptr) #0 {119 %fptr = addrspacecast ptr addrspace(1) %gptr to ptr120 %fload = load volatile i16, ptr %fptr, align 4121 %ext = zext i16 %fload to i32122 store i32 %ext, ptr addrspace(1) %out, align 4123 ret void124}125 126; GCN-LABEL: flat_scratch_unaligned_load:127; GFX9: flat_load_dword128; GFX10PLUS: flat_load_{{dword|b32}}129define amdgpu_kernel void @flat_scratch_unaligned_load() {130 %scratch = alloca i32, addrspace(5)131 %fptr = addrspacecast ptr addrspace(5) %scratch to ptr132 store volatile ptr %fptr, ptr addrspace(3) null133 %ld = load volatile i32, ptr %fptr, align 1134 ret void135}136 137; GCN-LABEL: flat_scratch_unaligned_store:138; GFX9: flat_store_dword139; GFX10PLUS: flat_store_{{dword|b32}}140define amdgpu_kernel void @flat_scratch_unaligned_store() {141 %scratch = alloca i32, addrspace(5)142 %fptr = addrspacecast ptr addrspace(5) %scratch to ptr143 store volatile ptr %fptr, ptr addrspace(3) null144 store volatile i32 0, ptr %fptr, align 1145 ret void146}147 148; GCN-LABEL: flat_scratch_multidword_load_kernel:149; CIVI-HSA: flat_load_dword v150; CIVI-HSA: flat_load_dword v151; GFX9: flat_load_dwordx2152; GFX10PLUS: flat_load_{{dwordx2|b64}}153; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr154define amdgpu_kernel void @flat_scratch_multidword_load_kernel() {155 %scratch = alloca <2 x i32>, addrspace(5)156 %fptr = addrspacecast ptr addrspace(5) %scratch to ptr157 %ld = load volatile <2 x i32>, ptr %fptr158 ret void159}160;161; GCN-LABEL: flat_scratch_multidword_load_func:162; CIVI-HSA: flat_load_dword v163; CIVI-HSA: flat_load_dword v164; GFX9: flat_load_dwordx2165; GFX10PLUS: flat_load_{{dwordx2|b64}}166; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr167define <2 x i32> @flat_scratch_multidword_load_func(ptr %maybe.scratch) {168 %load = load <2 x i32>, ptr %maybe.scratch169 ret <2 x i32> %load170}171 172; GCN-LABEL: flat_scratch_multidword_store_kernel:173; CIVI-HSA: flat_store_dword v174; CIVI-HSA: flat_store_dword v175; GFX9: flat_store_dwordx2176; GFX10PLUS: flat_store_{{dwordx2|b64}}177; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr178define amdgpu_kernel void @flat_scratch_multidword_store_kernel() {179 %scratch = alloca <2 x i32>, addrspace(5)180 %fptr = addrspacecast ptr addrspace(5) %scratch to ptr181 store volatile <2 x i32> zeroinitializer, ptr %fptr182 ret void183}184 185; GCN-LABEL: flat_scratch_multidword_store_func:186; CIVI-HSA: flat_store_dword v187; CIVI-HSA: flat_store_dword v188; GFX9: flat_store_dwordx2189; GFX10PLUS: flat_store_{{dwordx2|b64}}190define void @flat_scratch_multidword_store_func(ptr %maybe.scratch) {191 store <2 x i32> zeroinitializer, ptr %maybe.scratch192 ret void193}194 195; GCN-LABEL: {{^}}store_flat_i8_max_offset:196; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}197; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}}198define amdgpu_kernel void @store_flat_i8_max_offset(ptr %fptr, i8 %x) #0 {199 %fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4095200 store volatile i8 %x, ptr %fptr.offset201 ret void202}203 204; GCN-LABEL: {{^}}store_flat_i8_max_offset_p1:205; GCN: flat_store_{{byte|b8}} v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{( dlc)?}}{{$}}206define amdgpu_kernel void @store_flat_i8_max_offset_p1(ptr %fptr, i8 %x) #0 {207 %fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4096208 store volatile i8 %x, ptr %fptr.offset209 ret void210}211 212; GCN-LABEL: {{^}}store_flat_i8_neg_offset:213; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}214 215; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s216; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1,217; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}218define amdgpu_kernel void @store_flat_i8_neg_offset(ptr %fptr, i8 %x) #0 {219 %fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 -2220 store volatile i8 %x, ptr %fptr.offset221 ret void222}223 224; GCN-LABEL: {{^}}load_flat_i8_max_offset:225; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}226; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc{{$}}227; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}228; GFX11-TRUE16: flat_load_d16_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc dlc{{$}}229; GFX11-FAKE16: flat_load_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc dlc{{$}}230define amdgpu_kernel void @load_flat_i8_max_offset(ptr %fptr) #0 {231 %fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4095232 %val = load volatile i8, ptr %fptr.offset233 ret void234}235 236; GCN-LABEL: {{^}}load_flat_i8_max_offset_p1:237; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}238; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}239; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}240; GFX11-TRUE16: flat_load_d16_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}241; GFX11-FAKE16: flat_load_u8 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}242define amdgpu_kernel void @load_flat_i8_max_offset_p1(ptr %fptr) #0 {243 %fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 4096244 %val = load volatile i8, ptr %fptr.offset245 ret void246}247 248; GCN-LABEL: {{^}}load_flat_i8_neg_offset:249; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}250 251; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s252; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1,253; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}254define amdgpu_kernel void @load_flat_i8_neg_offset(ptr %fptr) #0 {255 %fptr.offset = getelementptr inbounds i8, ptr %fptr, i64 -2256 %val = load volatile i8, ptr %fptr.offset257 ret void258}259 260attributes #0 = { nounwind }261attributes #1 = { nounwind convergent }262