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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN %s3 4; The first load produces address in a VGPR which is used in address calculation5; of the second load (one inside the loop). The value is uniform and the inner6; load correctly selected to use SADDR form, however the address is promoted to7; vector registers because it all starts with a VGPR produced by the entry block8; load.9;10; Check that we are changing SADDR form of a load to VADDR and do not have to use11; readfirstlane instructions to move address from VGPRs into SGPRs.12 13define amdgpu_kernel void @test_move_load_address_to_vgpr(ptr addrspace(1) nocapture %arg1, ptr nocapture %arg2) {14; GCN-LABEL: test_move_load_address_to_vgpr:15; GCN: ; %bb.0: ; %bb16; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 117; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x2418; GCN-NEXT: v_mov_b32_e32 v3, 019; GCN-NEXT: s_wait_kmcnt 0x020; GCN-NEXT: global_load_b32 v2, v3, s[0:1] scope:SCOPE_SYS21; GCN-NEXT: s_wait_loadcnt 0x022; GCN-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[2:3]23; GCN-NEXT: v_add_nc_u32_e32 v2, 0xffffff00, v224; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2)25; GCN-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]26; GCN-NEXT: .LBB0_1: ; %bb327; GCN-NEXT: ; =>This Inner Loop Header: Depth=128; GCN-NEXT: s_wait_dscnt 0x029; GCN-NEXT: flat_load_b32 v3, v[0:1] scope:SCOPE_SYS30; GCN-NEXT: s_wait_loadcnt 0x031; GCN-NEXT: v_add_nc_u64_e32 v[0:1], 4, v[0:1]32; GCN-NEXT: v_add_co_u32 v2, s0, v2, 133; GCN-NEXT: s_and_b32 vcc_lo, exec_lo, s034; GCN-NEXT: s_cbranch_vccz .LBB0_135; GCN-NEXT: ; %bb.2: ; %bb236; GCN-NEXT: s_endpgm37bb:38 %i2 = load volatile i32, ptr addrspace(1) %arg1, align 439 br label %bb340 41bb2: ; preds = %bb342 ret void43 44bb3: ; preds = %bb3, %bb45 %i = phi i32 [ %i2, %bb ], [ %i8, %bb3 ]46 %i4 = zext i32 %i to i6447 %i5 = getelementptr inbounds i32, ptr %arg2, i64 %i448 %i6 = load volatile i32, ptr %i5, align 449 %i8 = add nuw nsw i32 %i, 150 %i9 = icmp eq i32 %i8, 25651 br i1 %i9, label %bb2, label %bb352}53