brintos / llvm-project-archived public Read only

1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -mattr=+real-true16,-sramecc < %s | FileCheck -check-prefixes=GFX1250,GFX1250-NOECC,GFX1250-NOECC-SDAG-TRUE16 %s6; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -mattr=-real-true16,-sramecc < %s | FileCheck -check-prefixes=GFX1250,GFX1250-NOECC,GFX1250-NOECC-SDAG-FAKE16 %s7 8; Test using saddr addressing mode of flat_*load_* instructions.9 10; --------------------------------------------------------------------------------11; No vgpr offset, constants12; --------------------------------------------------------------------------------13 14; SGPR base only15define amdgpu_ps float @flat_load_saddr_i8_offset_0(ptr inreg %sbase) {16; GFX1250-LABEL: flat_load_saddr_i8_offset_0:17; GFX1250:       ; %bb.0:18; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 119; GFX1250-NEXT:    v_mov_b32_e32 v0, 020; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3]21; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x022; GFX1250-NEXT:    ; return to shader part epilog23  %load = load i8, ptr %sbase24  %zext = zext i8 %load to i3225  %to.vgpr = bitcast i32 %zext to float26  ret float %to.vgpr27}28 29; SGPR base with maximum gfx1250 immediate offset30define amdgpu_ps float @flat_load_saddr_i8_offset_8388607(ptr inreg %sbase) {31; GFX1250-LABEL: flat_load_saddr_i8_offset_8388607:32; GFX1250:       ; %bb.0:33; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 134; GFX1250-NEXT:    v_mov_b32_e32 v0, 035; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:838860736; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x037; GFX1250-NEXT:    ; return to shader part epilog38  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 838860739  %load = load i8, ptr %gep040  %zext = zext i8 %load to i3241  %to.vgpr = bitcast i32 %zext to float42  ret float %to.vgpr43}44 45; SGPR base with maximum gfx1250 immediate offset + 146define amdgpu_ps float @flat_load_saddr_i8_offset_8388608(ptr inreg %sbase) {47; GFX1250-LABEL: flat_load_saddr_i8_offset_8388608:48; GFX1250:       ; %bb.0:49; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 150; GFX1250-NEXT:    v_mov_b32_e32 v0, 0x80000051; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3]52; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x053; GFX1250-NEXT:    ; return to shader part epilog54  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 838860855  %load = load i8, ptr %gep056  %zext = zext i8 %load to i3257  %to.vgpr = bitcast i32 %zext to float58  ret float %to.vgpr59}60 61; SGPR base with maximum negative gfx1250 immediate offset62define amdgpu_ps float @flat_load_saddr_i8_offset_neg8388608(ptr inreg %sbase) {63; GFX1250-LABEL: flat_load_saddr_i8_offset_neg8388608:64; GFX1250:       ; %bb.0:65; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 166; GFX1250-NEXT:    v_mov_b32_e32 v0, 067; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-838860868; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x069; GFX1250-NEXT:    ; return to shader part epilog70  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -838860871  %load = load i8, ptr %gep072  %zext = zext i8 %load to i3273  %to.vgpr = bitcast i32 %zext to float74  ret float %to.vgpr75}76 77; SGPR base with maximum negative gfx1250 immediate offset -178define amdgpu_ps float @flat_load_saddr_i8_offset_neg8388609(ptr inreg %sbase) {79; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_neg8388609:80; GFX1250-SDAG:       ; %bb.0:81; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 182; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xff800000, s283; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)84; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s3, s085; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-186; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x087; GFX1250-SDAG-NEXT:    ; return to shader part epilog88;89; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_neg8388609:90; GFX1250-GISEL:       ; %bb.0:91; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 192; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, 0xff7fffff93; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, -194; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)95; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]96; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]97; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x098; GFX1250-GISEL-NEXT:    ; return to shader part epilog99;100; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg8388609:101; GFX1250-NOECC:       ; %bb.0:102; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1103; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, s0, 0xff800000, s2104; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)105; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s3, s0106; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:-1107; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0108; GFX1250-NOECC-NEXT:    ; return to shader part epilog109  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -8388609110  %load = load i8, ptr %gep0111  %zext = zext i8 %load to i32112  %to.vgpr = bitcast i32 %zext to float113  ret float %to.vgpr114}115 116define amdgpu_ps float @flat_load_saddr_i8_offset_0xFFFFFFFF(ptr inreg %sbase) {117; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_0xFFFFFFFF:118; GFX1250-SDAG:       ; %bb.0:119; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1120; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, s0, 0xff800000, s2121; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)122; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s3, s0123; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607124; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0125; GFX1250-SDAG-NEXT:    ; return to shader part epilog126;127; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_0xFFFFFFFF:128; GFX1250-GISEL:       ; %bb.0:129; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1130; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, -1131; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 0132; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)133; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]134; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]135; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0136; GFX1250-GISEL-NEXT:    ; return to shader part epilog137;138; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0xFFFFFFFF:139; GFX1250-NOECC:       ; %bb.0:140; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1141; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, s0, 0xff800000, s2142; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)143; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, s3, s0144; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607145; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0146; GFX1250-NOECC-NEXT:    ; return to shader part epilog147  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967295148  %load = load i8, ptr %gep0149  %zext = zext i8 %load to i32150  %to.vgpr = bitcast i32 %zext to float151  ret float %to.vgpr152}153 154define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000000(ptr inreg %sbase) {155; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_0x100000000:156; GFX1250-SDAG:       ; %bb.0:157; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1158; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 0159; GFX1250-SDAG-NEXT:    s_add_co_i32 s3, s3, 1160; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3]161; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0162; GFX1250-SDAG-NEXT:    ; return to shader part epilog163;164; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_0x100000000:165; GFX1250-GISEL:       ; %bb.0:166; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1167; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, 0168; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 1169; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)170; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]171; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]172; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0173; GFX1250-GISEL-NEXT:    ; return to shader part epilog174;175; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000000:176; GFX1250-NOECC:       ; %bb.0:177; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1178; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, 0179; GFX1250-NOECC-NEXT:    s_add_co_i32 s3, s3, 1180; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[2:3]181; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0182; GFX1250-NOECC-NEXT:    ; return to shader part epilog183  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967296184  %load = load i8, ptr %gep0185  %zext = zext i8 %load to i32186  %to.vgpr = bitcast i32 %zext to float187  ret float %to.vgpr188}189 190define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000001(ptr inreg %sbase) {191; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_0x100000001:192; GFX1250-SDAG:       ; %bb.0:193; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1194; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s2195; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)196; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 1, s3, s0197; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:1198; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0199; GFX1250-SDAG-NEXT:    ; return to shader part epilog200;201; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_0x100000001:202; GFX1250-GISEL:       ; %bb.0:203; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1204; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, 1205; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 1206; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)207; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]208; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]209; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0210; GFX1250-GISEL-NEXT:    ; return to shader part epilog211;212; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000001:213; GFX1250-NOECC:       ; %bb.0:214; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1215; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, s0, 0, s2216; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)217; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, 1, s3, s0218; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:1219; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0220; GFX1250-NOECC-NEXT:    ; return to shader part epilog221  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294967297222  %load = load i8, ptr %gep0223  %zext = zext i8 %load to i32224  %to.vgpr = bitcast i32 %zext to float225  ret float %to.vgpr226}227 228define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000FFF(ptr inreg %sbase) {229; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_0x100000FFF:230; GFX1250-SDAG:       ; %bb.0:231; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1232; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s2233; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)234; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 1, s3, s0235; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4095236; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0237; GFX1250-SDAG-NEXT:    ; return to shader part epilog238;239; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_0x100000FFF:240; GFX1250-GISEL:       ; %bb.0:241; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1242; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, 0xfff243; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 1244; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)245; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]246; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]247; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0248; GFX1250-GISEL-NEXT:    ; return to shader part epilog249;250; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100000FFF:251; GFX1250-NOECC:       ; %bb.0:252; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1253; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, s0, 0, s2254; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)255; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, 1, s3, s0256; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:4095257; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0258; GFX1250-NOECC-NEXT:    ; return to shader part epilog259  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294971391260  %load = load i8, ptr %gep0261  %zext = zext i8 %load to i32262  %to.vgpr = bitcast i32 %zext to float263  ret float %to.vgpr264}265 266define amdgpu_ps float @flat_load_saddr_i8_offset_0x100001000(ptr inreg %sbase) {267; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_0x100001000:268; GFX1250-SDAG:       ; %bb.0:269; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1270; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s2271; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)272; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 1, s3, s0273; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:4096274; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0275; GFX1250-SDAG-NEXT:    ; return to shader part epilog276;277; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_0x100001000:278; GFX1250-GISEL:       ; %bb.0:279; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1280; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, 0x1000281; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 1282; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)283; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]284; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]285; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0286; GFX1250-GISEL-NEXT:    ; return to shader part epilog287;288; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_0x100001000:289; GFX1250-NOECC:       ; %bb.0:290; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1291; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, s0, 0, s2292; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)293; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, 1, s3, s0294; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:4096295; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0296; GFX1250-NOECC-NEXT:    ; return to shader part epilog297  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 4294971392298  %load = load i8, ptr %gep0299  %zext = zext i8 %load to i32300  %to.vgpr = bitcast i32 %zext to float301  ret float %to.vgpr302}303 304define amdgpu_ps float @flat_load_saddr_i8_offset_neg0xFFFFFFFF(ptr inreg %sbase) {305; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_neg0xFFFFFFFF:306; GFX1250-SDAG:       ; %bb.0:307; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1308; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, s0, 0x800000, s2309; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)310; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s3, s0311; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-8388607312; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0313; GFX1250-SDAG-NEXT:    ; return to shader part epilog314;315; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_neg0xFFFFFFFF:316; GFX1250-GISEL:       ; %bb.0:317; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1318; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, 1319; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, -1320; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)321; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]322; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]323; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0324; GFX1250-GISEL-NEXT:    ; return to shader part epilog325;326; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg0xFFFFFFFF:327; GFX1250-NOECC:       ; %bb.0:328; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1329; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, s0, 0x800000, s2330; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)331; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s3, s0332; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:-8388607333; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0334; GFX1250-NOECC-NEXT:    ; return to shader part epilog335  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -4294967295336  %load = load i8, ptr %gep0337  %zext = zext i8 %load to i32338  %to.vgpr = bitcast i32 %zext to float339  ret float %to.vgpr340}341 342define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000000(ptr inreg %sbase) {343; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_neg0x100000000:344; GFX1250-SDAG:       ; %bb.0:345; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1346; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 0347; GFX1250-SDAG-NEXT:    s_add_co_i32 s3, s3, -1348; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3]349; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0350; GFX1250-SDAG-NEXT:    ; return to shader part epilog351;352; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_neg0x100000000:353; GFX1250-GISEL:       ; %bb.0:354; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1355; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, 0356; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, -1357; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)358; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]359; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]360; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0361; GFX1250-GISEL-NEXT:    ; return to shader part epilog362;363; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg0x100000000:364; GFX1250-NOECC:       ; %bb.0:365; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1366; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, 0367; GFX1250-NOECC-NEXT:    s_add_co_i32 s3, s3, -1368; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[2:3]369; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0370; GFX1250-NOECC-NEXT:    ; return to shader part epilog371  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -4294967296372  %load = load i8, ptr %gep0373  %zext = zext i8 %load to i32374  %to.vgpr = bitcast i32 %zext to float375  ret float %to.vgpr376}377 378define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000001(ptr inreg %sbase) {379; GFX1250-SDAG-LABEL: flat_load_saddr_i8_offset_neg0x100000001:380; GFX1250-SDAG:       ; %bb.0:381; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1382; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, s0, 0, s2383; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)384; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s3, s0385; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:-1386; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0387; GFX1250-SDAG-NEXT:    ; return to shader part epilog388;389; GFX1250-GISEL-LABEL: flat_load_saddr_i8_offset_neg0x100000001:390; GFX1250-GISEL:       ; %bb.0:391; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1392; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, -1393; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, -2394; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)395; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]396; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]397; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0398; GFX1250-GISEL-NEXT:    ; return to shader part epilog399;400; GFX1250-NOECC-LABEL: flat_load_saddr_i8_offset_neg0x100000001:401; GFX1250-NOECC:       ; %bb.0:402; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1403; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, s0, 0, s2404; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)405; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, -1, s3, s0406; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:-1407; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0408; GFX1250-NOECC-NEXT:    ; return to shader part epilog409  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -4294967297410  %load = load i8, ptr %gep0411  %zext = zext i8 %load to i32412  %to.vgpr = bitcast i32 %zext to float413  ret float %to.vgpr414}415 416; --------------------------------------------------------------------------------417; Basic addressing patterns418; --------------------------------------------------------------------------------419 420; Basic pattern, no immediate offset.421define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr(ptr inreg %sbase, i32 %voffset) {422; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr:423; GFX1250:       ; %bb.0:424; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1425; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3]426; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0427; GFX1250-NEXT:    ; return to shader part epilog428  %zext.offset = zext i32 %voffset to i64429  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset430  %load = load i8, ptr %gep0431  %zext = zext i8 %load to i32432  %to.vgpr = bitcast i32 %zext to float433  ret float %to.vgpr434}435 436; Maximum positive offset on gfx1250437define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607(ptr inreg %sbase, i32 %voffset) {438; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388607:439; GFX1250:       ; %bb.0:440; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1441; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:8388607442; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0443; GFX1250-NEXT:    ; return to shader part epilog444  %zext.offset = zext i32 %voffset to i64445  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset446  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 8388607447  %load = load i8, ptr %gep1448  %zext = zext i8 %load to i32449  %to.vgpr = bitcast i32 %zext to float450  ret float %to.vgpr451}452 453; Maximum positive offset on gfx1250 + 1454define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388608(ptr inreg %sbase, i32 %voffset) {455; GFX1250-SDAG-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388608:456; GFX1250-SDAG:       ; %bb.0:457; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1458; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, 0459; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)460; GFX1250-SDAG-NEXT:    v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]461; GFX1250-SDAG-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0462; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)463; GFX1250-SDAG-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo464; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1]465; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0466; GFX1250-SDAG-NEXT:    ; return to shader part epilog467;468; GFX1250-GISEL-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388608:469; GFX1250-GISEL:       ; %bb.0:470; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1471; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]472; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)473; GFX1250-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, v2, v0474; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo475; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)476; GFX1250-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0477; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo478; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]479; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0480; GFX1250-GISEL-NEXT:    ; return to shader part epilog481;482; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388608:483; GFX1250-NOECC:       ; %bb.0:484; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1485; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v1, 0486; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)487; GFX1250-NOECC-NEXT:    v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]488; GFX1250-NOECC-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800000, v0489; GFX1250-NOECC-NEXT:    s_delay_alu instid0(VALU_DEP_1)490; GFX1250-NOECC-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo491; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1]492; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0493; GFX1250-NOECC-NEXT:    ; return to shader part epilog494  %zext.offset = zext i32 %voffset to i64495  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset496  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 8388608497  %load = load i8, ptr %gep1498  %zext = zext i8 %load to i32499  %to.vgpr = bitcast i32 %zext to float500  ret float %to.vgpr501}502 503; Maximum negative offset on gfx1250504define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388608(ptr inreg %sbase, i32 %voffset) {505; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_offset_neg8388608:506; GFX1250:       ; %bb.0:507; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1508; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-8388608509; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0510; GFX1250-NEXT:    ; return to shader part epilog511  %zext.offset = zext i32 %voffset to i64512  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset513  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -8388608514  %load = load i8, ptr %gep1515  %zext = zext i8 %load to i32516  %to.vgpr = bitcast i32 %zext to float517  ret float %to.vgpr518}519 520; Maximum negative offset on gfx1250 - 1521define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388607(ptr inreg %sbase, i32 %voffset) {522; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_offset_neg8388607:523; GFX1250:       ; %bb.0:524; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1525; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-8388607526; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0527; GFX1250-NEXT:    ; return to shader part epilog528  %zext.offset = zext i32 %voffset to i64529  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset530  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -8388607531  %load = load i8, ptr %gep1532  %zext = zext i8 %load to i32533  %to.vgpr = bitcast i32 %zext to float534  ret float %to.vgpr535}536 537define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607_gep_order(ptr inreg %sbase, i32 %voffset) {538; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_offset_8388607_gep_order:539; GFX1250:       ; %bb.0:540; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1541; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:8388607542; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0543; GFX1250-NEXT:    ; return to shader part epilog544  %zext.offset = zext i32 %voffset to i64545  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 8388607546  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 %zext.offset547  %load = load i8, ptr %gep1548  %zext = zext i8 %load to i32549  %to.vgpr = bitcast i32 %zext to float550  ret float %to.vgpr551}552 553; pointer addressing done in integers554define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint(ptr inreg %sbase, i32 %voffset) {555; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint:556; GFX1250:       ; %bb.0:557; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1558; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3]559; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0560; GFX1250-NEXT:    ; return to shader part epilog561  %zext.offset = zext i32 %voffset to i64562  %sbase.as.int = ptrtoint ptr %sbase to i64563  %add = add i64 %sbase.as.int, %zext.offset564  %dirty.gep = inttoptr i64 %add to ptr565  %load = load i8, ptr %dirty.gep566  %zext = zext i8 %load to i32567  %to.vgpr = bitcast i32 %zext to float568  ret float %to.vgpr569}570 571; zext forced to LHS of addressing expression572define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add(ptr inreg %sbase, i32 %voffset) {573; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add:574; GFX1250:       ; %bb.0:575; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1576; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3]577; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0578; GFX1250-NEXT:    ; return to shader part epilog579  %zext.offset = zext i32 %voffset to i64580  %sbase.as.int = ptrtoint ptr %sbase to i64581  %add = add i64 %zext.offset, %sbase.as.int582  %dirty.gep = inttoptr i64 %add to ptr583  %load = load i8, ptr %dirty.gep584  %zext = zext i8 %load to i32585  %to.vgpr = bitcast i32 %zext to float586  ret float %to.vgpr587}588 589; zext forced to LHS of addressing expression, with immediate offset590define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0(ptr inreg %sbase, i32 %voffset) {591; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0:592; GFX1250:       ; %bb.0:593; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1594; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:128595; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0596; GFX1250-NEXT:    ; return to shader part epilog597  %zext.offset = zext i32 %voffset to i64598  %sbase.as.int = ptrtoint ptr %sbase to i64599  %add = add i64 %zext.offset, %sbase.as.int600  %add.immoffset = add i64 %add, 128601  %dirty.gep = inttoptr i64 %add.immoffset to ptr602  %load = load i8, ptr %dirty.gep603  %zext = zext i8 %load to i32604  %to.vgpr = bitcast i32 %zext to float605  ret float %to.vgpr606}607 608; zext forced to LHS of addressing expression, with immediate offset in non-canonical position609define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1(ptr inreg %sbase, i32 %voffset) {610; GFX1250-LABEL: flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1:611; GFX1250:       ; %bb.0:612; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1613; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:128614; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0615; GFX1250-NEXT:    ; return to shader part epilog616  %zext.offset = zext i32 %voffset to i64617  %sbase.as.int = ptrtoint ptr %sbase to i64618  %add.immoffset = add i64 %sbase.as.int, 128619  %add = add i64 %zext.offset, %add.immoffset620  %dirty.gep = inttoptr i64 %add to ptr621  %load = load i8, ptr %dirty.gep622  %zext = zext i8 %load to i32623  %to.vgpr = bitcast i32 %zext to float624  ret float %to.vgpr625}626 627; --------------------------------------------------------------------------------628; Uniformity edge cases629; --------------------------------------------------------------------------------630 631@ptr.in.lds = internal addrspace(3) global ptr undef632 633; Base pointer is uniform, but also in VGPRs634define amdgpu_ps float @flat_load_saddr_uniform_ptr_in_vgprs(i32 %voffset) {635; GFX1250-SDAG-LABEL: flat_load_saddr_uniform_ptr_in_vgprs:636; GFX1250-SDAG:       ; %bb.0:637; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1638; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, 0639; GFX1250-SDAG-NEXT:    ds_load_b64 v[2:3], v1640; GFX1250-SDAG-NEXT:    s_wait_dscnt 0x0641; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v2642; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v3643; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[0:1]644; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0645; GFX1250-SDAG-NEXT:    ; return to shader part epilog646;647; GFX1250-GISEL-LABEL: flat_load_saddr_uniform_ptr_in_vgprs:648; GFX1250-GISEL:       ; %bb.0:649; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1650; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v1, 0651; GFX1250-GISEL-NEXT:    ds_load_b64 v[2:3], v1652; GFX1250-GISEL-NEXT:    s_wait_dscnt 0x0653; GFX1250-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, v2, v0654; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)655; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo656; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]657; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0658; GFX1250-GISEL-NEXT:    ; return to shader part epilog659;660; GFX1250-NOECC-LABEL: flat_load_saddr_uniform_ptr_in_vgprs:661; GFX1250-NOECC:       ; %bb.0:662; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1663; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v1, 0664; GFX1250-NOECC-NEXT:    ds_load_b64 v[2:3], v1665; GFX1250-NOECC-NEXT:    s_wait_dscnt 0x0666; GFX1250-NOECC-NEXT:    v_readfirstlane_b32 s0, v2667; GFX1250-NOECC-NEXT:    v_readfirstlane_b32 s1, v3668; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[0:1]669; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0670; GFX1250-NOECC-NEXT:    ; return to shader part epilog671  %sbase = load ptr, ptr addrspace(3) @ptr.in.lds672  %zext.offset = zext i32 %voffset to i64673  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset674  %load = load i8, ptr %gep0675  %zext = zext i8 %load to i32676  %to.vgpr = bitcast i32 %zext to float677  ret float %to.vgpr678}679 680; Base pointer is uniform, but also in VGPRs, with imm offset681define amdgpu_ps float @flat_load_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset) {682; GFX1250-SDAG-LABEL: flat_load_saddr_uniform_ptr_in_vgprs_immoffset:683; GFX1250-SDAG:       ; %bb.0:684; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1685; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, 0686; GFX1250-SDAG-NEXT:    ds_load_b64 v[2:3], v1687; GFX1250-SDAG-NEXT:    s_wait_dscnt 0x0688; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v2689; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v3690; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[0:1] offset:42691; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0692; GFX1250-SDAG-NEXT:    ; return to shader part epilog693;694; GFX1250-GISEL-LABEL: flat_load_saddr_uniform_ptr_in_vgprs_immoffset:695; GFX1250-GISEL:       ; %bb.0:696; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1697; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v1, 0698; GFX1250-GISEL-NEXT:    ds_load_b64 v[2:3], v1699; GFX1250-GISEL-NEXT:    s_wait_dscnt 0x0700; GFX1250-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, v2, v0701; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)702; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo703; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:42704; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0705; GFX1250-GISEL-NEXT:    ; return to shader part epilog706;707; GFX1250-NOECC-LABEL: flat_load_saddr_uniform_ptr_in_vgprs_immoffset:708; GFX1250-NOECC:       ; %bb.0:709; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1710; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v1, 0711; GFX1250-NOECC-NEXT:    ds_load_b64 v[2:3], v1712; GFX1250-NOECC-NEXT:    s_wait_dscnt 0x0713; GFX1250-NOECC-NEXT:    v_readfirstlane_b32 s0, v2714; GFX1250-NOECC-NEXT:    v_readfirstlane_b32 s1, v3715; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[0:1] offset:42716; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0717; GFX1250-NOECC-NEXT:    ; return to shader part epilog718  %sbase = load ptr, ptr addrspace(3) @ptr.in.lds719  %zext.offset = zext i32 %voffset to i64720  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset721  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 42722  %load = load i8, ptr %gep1723  %zext = zext i8 %load to i32724  %to.vgpr = bitcast i32 %zext to float725  ret float %to.vgpr726}727 728; Both 64-bit base and 32-bit offset are scalar729define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset(ptr inreg %sbase, i32 inreg %soffset) {730; GFX1250-SDAG-LABEL: flat_load_saddr_i8_zext_uniform_offset:731; GFX1250-SDAG:       ; %bb.0:732; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1733; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, s4734; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3]735; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0736; GFX1250-SDAG-NEXT:    ; return to shader part epilog737;738; GFX1250-GISEL-LABEL: flat_load_saddr_i8_zext_uniform_offset:739; GFX1250-GISEL:       ; %bb.0:740; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1741; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, 0742; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, s4743; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 0744; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[0:1]745; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0746; GFX1250-GISEL-NEXT:    ; return to shader part epilog747;748; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_uniform_offset:749; GFX1250-NOECC:       ; %bb.0:750; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1751; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, s4752; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[2:3]753; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0754; GFX1250-NOECC-NEXT:    ; return to shader part epilog755  %zext.offset = zext i32 %soffset to i64756  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset757  %load = load i8, ptr %gep0758  %zext = zext i8 %load to i32759  %to.vgpr = bitcast i32 %zext to float760  ret float %to.vgpr761}762 763; Both 64-bit base and 32-bit offset are scalar, with immediate offset.764define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset_immoffset(ptr inreg %sbase, i32 inreg %soffset) {765; GFX1250-SDAG-LABEL: flat_load_saddr_i8_zext_uniform_offset_immoffset:766; GFX1250-SDAG:       ; %bb.0:767; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1768; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, s4769; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-24770; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0771; GFX1250-SDAG-NEXT:    ; return to shader part epilog772;773; GFX1250-GISEL-LABEL: flat_load_saddr_i8_zext_uniform_offset_immoffset:774; GFX1250-GISEL:       ; %bb.0:775; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1776; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, 0777; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, s4778; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 0779; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[0:1] offset:-24780; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0781; GFX1250-GISEL-NEXT:    ; return to shader part epilog782;783; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_uniform_offset_immoffset:784; GFX1250-NOECC:       ; %bb.0:785; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1786; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, s4787; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-24788; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0789; GFX1250-NOECC-NEXT:    ; return to shader part epilog790  %zext.offset = zext i32 %soffset to i64791  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset792  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -24793  %load = load i8, ptr %gep1794  %zext = zext i8 %load to i32795  %to.vgpr = bitcast i32 %zext to float796  ret float %to.vgpr797}798 799; Both components uniform, zext forced to LHS of addressing expression800define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(ptr inreg %sbase, i32 inreg %soffset) {801; GFX1250-SDAG-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add:802; GFX1250-SDAG:       ; %bb.0:803; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1804; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, s4805; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3]806; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0807; GFX1250-SDAG-NEXT:    ; return to shader part epilog808;809; GFX1250-GISEL-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add:810; GFX1250-GISEL:       ; %bb.0:811; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1812; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, 0813; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, s4814; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 0815; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[0:1]816; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0817; GFX1250-GISEL-NEXT:    ; return to shader part epilog818;819; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add:820; GFX1250-NOECC:       ; %bb.0:821; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1822; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, s4823; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[2:3]824; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0825; GFX1250-NOECC-NEXT:    ; return to shader part epilog826  %zext.offset = zext i32 %soffset to i64827  %sbase.as.int = ptrtoint ptr %sbase to i64828  %add = add i64 %zext.offset, %sbase.as.int829  %dirty.gep = inttoptr i64 %add to ptr830  %load = load i8, ptr %dirty.gep831  %zext = zext i8 %load to i32832  %to.vgpr = bitcast i32 %zext to float833  ret float %to.vgpr834}835 836; Both components uniform, zext forced to LHS of addressing expression, with immediate offset837define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0(ptr inreg %sbase, i32 inreg %soffset) {838; GFX1250-SDAG-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0:839; GFX1250-SDAG:       ; %bb.0:840; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1841; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, s4842; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:128843; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0844; GFX1250-SDAG-NEXT:    ; return to shader part epilog845;846; GFX1250-GISEL-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0:847; GFX1250-GISEL:       ; %bb.0:848; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1849; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, 0850; GFX1250-GISEL-NEXT:    s_add_co_u32 s0, s2, s4851; GFX1250-GISEL-NEXT:    s_add_co_ci_u32 s1, s3, 0852; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[0:1] offset:128853; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0854; GFX1250-GISEL-NEXT:    ; return to shader part epilog855;856; GFX1250-NOECC-LABEL: flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0:857; GFX1250-NOECC:       ; %bb.0:858; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1859; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, s4860; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:128861; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0862; GFX1250-NOECC-NEXT:    ; return to shader part epilog863  %zext.offset = zext i32 %soffset to i64864  %sbase.as.int = ptrtoint ptr %sbase to i64865  %add = add i64 %zext.offset, %sbase.as.int866  %add.immoffset = add i64 %add, 128867  %dirty.gep = inttoptr i64 %add.immoffset to ptr868  %load = load i8, ptr %dirty.gep869  %zext = zext i8 %load to i32870  %to.vgpr = bitcast i32 %zext to float871  ret float %to.vgpr872}873 874; divergent 64-bit base, 32-bit scalar offset.875define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32(ptr %vbase, i32 inreg %soffset) {876; GFX1250-SDAG-LABEL: flat_load_i8_vgpr64_sgpr32:877; GFX1250-SDAG:       ; %bb.0:878; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1879; GFX1250-SDAG-NEXT:    s_mov_b32 s3, 0880; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)881; GFX1250-SDAG-NEXT:    v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]882; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1]883; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0884; GFX1250-SDAG-NEXT:    ; return to shader part epilog885;886; GFX1250-GISEL-LABEL: flat_load_i8_vgpr64_sgpr32:887; GFX1250-GISEL:       ; %bb.0:888; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1889; GFX1250-GISEL-NEXT:    s_mov_b32 s3, 0890; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)891; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]892; GFX1250-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2893; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)894; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo895; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1]896; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0897; GFX1250-GISEL-NEXT:    ; return to shader part epilog898;899; GFX1250-NOECC-LABEL: flat_load_i8_vgpr64_sgpr32:900; GFX1250-NOECC:       ; %bb.0:901; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1902; GFX1250-NOECC-NEXT:    s_mov_b32 s3, 0903; GFX1250-NOECC-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)904; GFX1250-NOECC-NEXT:    v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]905; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1]906; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0907; GFX1250-NOECC-NEXT:    ; return to shader part epilog908  %zext.offset = zext i32 %soffset to i64909  %gep0 = getelementptr inbounds i8, ptr %vbase, i64 %zext.offset910  %load = load i8, ptr %gep0911  %zext = zext i8 %load to i32912  %to.vgpr = bitcast i32 %zext to float913  ret float %to.vgpr914}915 916; divergent 64-bit base, 32-bit scalar offset, with imm offset917define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32_offset_8388607(ptr %vbase, i32 inreg %soffset) {918; GFX1250-SDAG-LABEL: flat_load_i8_vgpr64_sgpr32_offset_8388607:919; GFX1250-SDAG:       ; %bb.0:920; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1921; GFX1250-SDAG-NEXT:    s_mov_b32 s3, 0922; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)923; GFX1250-SDAG-NEXT:    v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]924; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607925; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0926; GFX1250-SDAG-NEXT:    ; return to shader part epilog927;928; GFX1250-GISEL-LABEL: flat_load_i8_vgpr64_sgpr32_offset_8388607:929; GFX1250-GISEL:       ; %bb.0:930; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1931; GFX1250-GISEL-NEXT:    s_mov_b32 s3, 0932; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)933; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]934; GFX1250-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2935; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)936; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo937; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607938; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0939; GFX1250-GISEL-NEXT:    ; return to shader part epilog940;941; GFX1250-NOECC-LABEL: flat_load_i8_vgpr64_sgpr32_offset_8388607:942; GFX1250-NOECC:       ; %bb.0:943; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1944; GFX1250-NOECC-NEXT:    s_mov_b32 s3, 0945; GFX1250-NOECC-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)946; GFX1250-NOECC-NEXT:    v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]947; GFX1250-NOECC-NEXT:    flat_load_u8 v0, v[0:1] offset:8388607948; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x0949; GFX1250-NOECC-NEXT:    ; return to shader part epilog950  %zext.offset = zext i32 %soffset to i64951  %gep0 = getelementptr inbounds i8, ptr %vbase, i64 %zext.offset952  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 8388607953  %load = load i8, ptr %gep1954  %zext = zext i8 %load to i32955  %to.vgpr = bitcast i32 %zext to float956  ret float %to.vgpr957}958 959; --------------------------------------------------------------------------------960; Natural addressing shifts with restricted range961; --------------------------------------------------------------------------------962 963; Cannot push the shift into 32-bits, and cannot match.964define amdgpu_ps float @flat_load_saddr_f32_natural_addressing(ptr inreg %sbase, ptr %voffset.ptr) {965; GFX1250-LABEL: flat_load_saddr_f32_natural_addressing:966; GFX1250:       ; %bb.0:967; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1968; GFX1250-NEXT:    flat_load_b32 v0, v[0:1]969; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0970; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] scale_offset971; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0972; GFX1250-NEXT:    ; return to shader part epilog973  %voffset = load i32, ptr %voffset.ptr974  %zext.offset = zext i32 %voffset to i64975  %gep = getelementptr inbounds float, ptr %sbase, i64 %zext.offset976  %load = load float, ptr %gep977  ret float %load978}979 980; Cannot push the shift into 32-bits, with an immediate offset.981define amdgpu_ps float @flat_load_saddr_f32_natural_addressing_immoffset(ptr inreg %sbase, ptr %voffset.ptr) {982; GFX1250-LABEL: flat_load_saddr_f32_natural_addressing_immoffset:983; GFX1250:       ; %bb.0:984; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1985; GFX1250-NEXT:    flat_load_b32 v0, v[0:1]986; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0987; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:128988; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0989; GFX1250-NEXT:    ; return to shader part epilog990  %voffset = load i32, ptr %voffset.ptr991  %zext.offset = zext i32 %voffset to i64992  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset993  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 128994  %load = load float, ptr %gep1995  ret float %load996}997 998; Range is sufficiently restricted to push the shift into 32-bits.999define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range(ptr inreg %sbase, ptr %voffset.ptr) {1000; GFX1250-LABEL: flat_load_f32_saddr_zext_vgpr_range:1001; GFX1250:       ; %bb.0:1002; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11003; GFX1250-NEXT:    flat_load_b32 v0, v[0:1]1004; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01005; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] scale_offset1006; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01007; GFX1250-NEXT:    ; return to shader part epilog1008  %voffset = load i32, ptr %voffset.ptr, !range !0, !noundef !{}1009  %zext.offset = zext i32 %voffset to i641010  %gep = getelementptr inbounds float, ptr %sbase, i64 %zext.offset1011  %load = load float, ptr %gep1012  ret float %load1013}1014 1015; Range is sufficiently restricted to push the shift into 32-bits, with an imm offset1016define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range_imm_offset(ptr inreg %sbase, ptr %voffset.ptr) {1017; GFX1250-LABEL: flat_load_f32_saddr_zext_vgpr_range_imm_offset:1018; GFX1250:       ; %bb.0:1019; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11020; GFX1250-NEXT:    flat_load_b32 v0, v[0:1]1021; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01022; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:400 scale_offset1023; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01024; GFX1250-NEXT:    ; return to shader part epilog1025  %voffset = load i32, ptr %voffset.ptr, !range !0, !noundef !{}1026  %zext.offset = zext i32 %voffset to i641027  %gep0 = getelementptr inbounds float, ptr %sbase, i64 %zext.offset1028  %gep1 = getelementptr inbounds float, ptr %gep0, i64 1001029  %load = load float, ptr %gep11030  ret float %load1031}1032 1033; Range is 1 beyond the limit where we can move the shift into 32-bits.1034define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range_too_large(ptr inreg %sbase, ptr %voffset.ptr) {1035; GFX1250-LABEL: flat_load_f32_saddr_zext_vgpr_range_too_large:1036; GFX1250:       ; %bb.0:1037; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11038; GFX1250-NEXT:    flat_load_b32 v0, v[0:1]1039; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01040; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] scale_offset1041; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01042; GFX1250-NEXT:    ; return to shader part epilog1043  %voffset = load i32, ptr %voffset.ptr, !range !1, !noundef !{}1044  %zext.offset = zext i32 %voffset to i641045  %gep = getelementptr inbounds float, ptr %sbase, i64 %zext.offset1046  %load = load float, ptr %gep1047  ret float %load1048}1049 1050; --------------------------------------------------------------------------------1051; Stress various type loads1052; --------------------------------------------------------------------------------1053 1054define amdgpu_ps half @flat_load_saddr_i16(ptr inreg %sbase, i32 %voffset) {1055; GFX1250-SDAG-LABEL: flat_load_saddr_i16:1056; GFX1250-SDAG:       ; %bb.0:1057; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11058; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]1059; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x01060; GFX1250-SDAG-NEXT:    ; return to shader part epilog1061;1062; GFX1250-GISEL-LABEL: flat_load_saddr_i16:1063; GFX1250-GISEL:       ; %bb.0:1064; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11065; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]1066; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x01067; GFX1250-GISEL-NEXT:    ; return to shader part epilog1068;1069; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16:1070; GFX1250-NOECC-SDAG-TRUE16:       ; %bb.0:1071; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11072; GFX1250-NOECC-SDAG-TRUE16-NEXT:    flat_load_d16_b16 v0, v0, s[2:3]1073; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01074; GFX1250-NOECC-SDAG-TRUE16-NEXT:    ; return to shader part epilog1075;1076; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16:1077; GFX1250-NOECC-SDAG-FAKE16:       ; %bb.0:1078; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11079; GFX1250-NOECC-SDAG-FAKE16-NEXT:    flat_load_u16 v0, v0, s[2:3]1080; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01081; GFX1250-NOECC-SDAG-FAKE16-NEXT:    ; return to shader part epilog1082  %zext.offset = zext i32 %voffset to i641083  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1084  %load = load i16, ptr %gep01085  %cast.load = bitcast i16 %load to half1086  ret half %cast.load1087}1088 1089define amdgpu_ps half @flat_load_saddr_i16_immneg128(ptr inreg %sbase, i32 %voffset) {1090; GFX1250-SDAG-LABEL: flat_load_saddr_i16_immneg128:1091; GFX1250-SDAG:       ; %bb.0:1092; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11093; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1281094; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x01095; GFX1250-SDAG-NEXT:    ; return to shader part epilog1096;1097; GFX1250-GISEL-LABEL: flat_load_saddr_i16_immneg128:1098; GFX1250-GISEL:       ; %bb.0:1099; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11100; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1281101; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x01102; GFX1250-GISEL-NEXT:    ; return to shader part epilog1103;1104; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_immneg128:1105; GFX1250-NOECC-SDAG-TRUE16:       ; %bb.0:1106; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11107; GFX1250-NOECC-SDAG-TRUE16-NEXT:    flat_load_d16_b16 v0, v0, s[2:3] offset:-1281108; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01109; GFX1250-NOECC-SDAG-TRUE16-NEXT:    ; return to shader part epilog1110;1111; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_immneg128:1112; GFX1250-NOECC-SDAG-FAKE16:       ; %bb.0:1113; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11114; GFX1250-NOECC-SDAG-FAKE16-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1281115; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01116; GFX1250-NOECC-SDAG-FAKE16-NEXT:    ; return to shader part epilog1117  %zext.offset = zext i32 %voffset to i641118  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1119  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281120  %load = load i16, ptr %gep11121  %cast.load = bitcast i16 %load to half1122  ret half %cast.load1123}1124 1125define amdgpu_ps half @flat_load_saddr_f16(ptr inreg %sbase, i32 %voffset) {1126; GFX1250-SDAG-LABEL: flat_load_saddr_f16:1127; GFX1250-SDAG:       ; %bb.0:1128; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11129; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]1130; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x01131; GFX1250-SDAG-NEXT:    ; return to shader part epilog1132;1133; GFX1250-GISEL-LABEL: flat_load_saddr_f16:1134; GFX1250-GISEL:       ; %bb.0:1135; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11136; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]1137; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x01138; GFX1250-GISEL-NEXT:    ; return to shader part epilog1139;1140; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_f16:1141; GFX1250-NOECC-SDAG-TRUE16:       ; %bb.0:1142; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11143; GFX1250-NOECC-SDAG-TRUE16-NEXT:    flat_load_d16_b16 v0, v0, s[2:3]1144; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01145; GFX1250-NOECC-SDAG-TRUE16-NEXT:    ; return to shader part epilog1146;1147; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_f16:1148; GFX1250-NOECC-SDAG-FAKE16:       ; %bb.0:1149; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11150; GFX1250-NOECC-SDAG-FAKE16-NEXT:    flat_load_u16 v0, v0, s[2:3]1151; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01152; GFX1250-NOECC-SDAG-FAKE16-NEXT:    ; return to shader part epilog1153  %zext.offset = zext i32 %voffset to i641154  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1155  %load = load half, ptr %gep01156  ret half %load1157}1158 1159define amdgpu_ps half @flat_load_saddr_f16_immneg128(ptr inreg %sbase, i32 %voffset) {1160; GFX1250-SDAG-LABEL: flat_load_saddr_f16_immneg128:1161; GFX1250-SDAG:       ; %bb.0:1162; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11163; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1281164; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x01165; GFX1250-SDAG-NEXT:    ; return to shader part epilog1166;1167; GFX1250-GISEL-LABEL: flat_load_saddr_f16_immneg128:1168; GFX1250-GISEL:       ; %bb.0:1169; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11170; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1281171; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x01172; GFX1250-GISEL-NEXT:    ; return to shader part epilog1173;1174; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_f16_immneg128:1175; GFX1250-NOECC-SDAG-TRUE16:       ; %bb.0:1176; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11177; GFX1250-NOECC-SDAG-TRUE16-NEXT:    flat_load_d16_b16 v0, v0, s[2:3] offset:-1281178; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01179; GFX1250-NOECC-SDAG-TRUE16-NEXT:    ; return to shader part epilog1180;1181; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_f16_immneg128:1182; GFX1250-NOECC-SDAG-FAKE16:       ; %bb.0:1183; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11184; GFX1250-NOECC-SDAG-FAKE16-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1281185; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01186; GFX1250-NOECC-SDAG-FAKE16-NEXT:    ; return to shader part epilog1187  %zext.offset = zext i32 %voffset to i641188  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1189  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281190  %load = load half, ptr %gep11191  ret half %load1192}1193 1194define amdgpu_ps float @flat_load_saddr_i32(ptr inreg %sbase, i32 %voffset) {1195; GFX1250-LABEL: flat_load_saddr_i32:1196; GFX1250:       ; %bb.0:1197; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11198; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3]1199; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01200; GFX1250-NEXT:    ; return to shader part epilog1201  %zext.offset = zext i32 %voffset to i641202  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1203  %load = load i32, ptr %gep01204  %cast.load = bitcast i32 %load to float1205  ret float %cast.load1206}1207 1208define amdgpu_ps float @flat_load_saddr_i32_immneg128(ptr inreg %sbase, i32 %voffset) {1209; GFX1250-LABEL: flat_load_saddr_i32_immneg128:1210; GFX1250:       ; %bb.0:1211; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11212; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:-1281213; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01214; GFX1250-NEXT:    ; return to shader part epilog1215  %zext.offset = zext i32 %voffset to i641216  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1217  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281218  %load = load i32, ptr %gep11219  %cast.load = bitcast i32 %load to float1220  ret float %cast.load1221}1222 1223define amdgpu_ps float @flat_load_saddr_f32(ptr inreg %sbase, i32 %voffset) {1224; GFX1250-LABEL: flat_load_saddr_f32:1225; GFX1250:       ; %bb.0:1226; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11227; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3]1228; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01229; GFX1250-NEXT:    ; return to shader part epilog1230  %zext.offset = zext i32 %voffset to i641231  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1232  %load = load float, ptr %gep01233  ret float %load1234}1235 1236define amdgpu_ps float @flat_load_saddr_f32_immneg128(ptr inreg %sbase, i32 %voffset) {1237; GFX1250-LABEL: flat_load_saddr_f32_immneg128:1238; GFX1250:       ; %bb.0:1239; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11240; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:-1281241; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01242; GFX1250-NEXT:    ; return to shader part epilog1243  %zext.offset = zext i32 %voffset to i641244  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1245  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281246  %load = load float, ptr %gep11247  ret float %load1248}1249 1250define amdgpu_ps <2 x half> @flat_load_saddr_v2i16(ptr inreg %sbase, i32 %voffset) {1251; GFX1250-LABEL: flat_load_saddr_v2i16:1252; GFX1250:       ; %bb.0:1253; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11254; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3]1255; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01256; GFX1250-NEXT:    ; return to shader part epilog1257  %zext.offset = zext i32 %voffset to i641258  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1259  %load = load <2 x i16>, ptr %gep01260  %cast.load = bitcast <2 x i16> %load to <2 x half>1261  ret <2 x half> %cast.load1262}1263 1264define amdgpu_ps <2 x half> @flat_load_saddr_v2i16_immneg128(ptr inreg %sbase, i32 %voffset) {1265; GFX1250-LABEL: flat_load_saddr_v2i16_immneg128:1266; GFX1250:       ; %bb.0:1267; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11268; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:-1281269; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01270; GFX1250-NEXT:    ; return to shader part epilog1271  %zext.offset = zext i32 %voffset to i641272  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1273  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281274  %load = load <2 x i16>, ptr %gep11275  %cast.load = bitcast <2 x i16> %load to <2 x half>1276  ret <2 x half> %cast.load1277}1278 1279define amdgpu_ps <2 x half> @flat_load_saddr_v2f16(ptr inreg %sbase, i32 %voffset) {1280; GFX1250-LABEL: flat_load_saddr_v2f16:1281; GFX1250:       ; %bb.0:1282; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11283; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3]1284; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01285; GFX1250-NEXT:    ; return to shader part epilog1286  %zext.offset = zext i32 %voffset to i641287  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1288  %load = load <2 x half>, ptr %gep01289  ret <2 x half> %load1290}1291 1292define amdgpu_ps <2 x half> @flat_load_saddr_v2f16_immneg128(ptr inreg %sbase, i32 %voffset) {1293; GFX1250-LABEL: flat_load_saddr_v2f16_immneg128:1294; GFX1250:       ; %bb.0:1295; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11296; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:-1281297; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01298; GFX1250-NEXT:    ; return to shader part epilog1299  %zext.offset = zext i32 %voffset to i641300  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1301  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281302  %load = load <2 x half>, ptr %gep11303  ret <2 x half> %load1304}1305 1306define amdgpu_ps <2 x half> @flat_load_saddr_p3(ptr inreg %sbase, i32 %voffset) {1307; GFX1250-LABEL: flat_load_saddr_p3:1308; GFX1250:       ; %bb.0:1309; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11310; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3]1311; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01312; GFX1250-NEXT:    ; return to shader part epilog1313  %zext.offset = zext i32 %voffset to i641314  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1315  %load = load ptr addrspace(3), ptr %gep01316  %cast.load0 = ptrtoint ptr addrspace(3) %load to i321317  %cast.load1 = bitcast i32 %cast.load0 to <2 x half>1318  ret <2 x half> %cast.load11319}1320 1321define amdgpu_ps <2 x half> @flat_load_saddr_p3_immneg128(ptr inreg %sbase, i32 %voffset) {1322; GFX1250-LABEL: flat_load_saddr_p3_immneg128:1323; GFX1250:       ; %bb.0:1324; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11325; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:-1281326; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01327; GFX1250-NEXT:    ; return to shader part epilog1328  %zext.offset = zext i32 %voffset to i641329  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1330  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281331  %load = load ptr addrspace(3), ptr %gep11332  %cast.load0 = ptrtoint ptr addrspace(3) %load to i321333  %cast.load1 = bitcast i32 %cast.load0 to <2 x half>1334  ret <2 x half> %cast.load11335}1336 1337define amdgpu_ps <2 x float> @flat_load_saddr_f64(ptr inreg %sbase, i32 %voffset) {1338; GFX1250-LABEL: flat_load_saddr_f64:1339; GFX1250:       ; %bb.0:1340; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11341; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3]1342; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01343; GFX1250-NEXT:    ; return to shader part epilog1344  %zext.offset = zext i32 %voffset to i641345  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1346  %load = load double, ptr %gep01347  %cast.load = bitcast double %load to <2 x float>1348  ret <2 x float> %cast.load1349}1350 1351define amdgpu_ps <2 x float> @flat_load_saddr_f64_immneg128(ptr inreg %sbase, i32 %voffset) {1352; GFX1250-LABEL: flat_load_saddr_f64_immneg128:1353; GFX1250:       ; %bb.0:1354; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11355; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-1281356; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01357; GFX1250-NEXT:    ; return to shader part epilog1358  %zext.offset = zext i32 %voffset to i641359  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1360  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281361  %load = load double, ptr %gep11362  %cast.load = bitcast double %load to <2 x float>1363  ret <2 x float> %cast.load1364}1365 1366define amdgpu_ps <2 x float> @flat_load_saddr_i64(ptr inreg %sbase, i32 %voffset) {1367; GFX1250-LABEL: flat_load_saddr_i64:1368; GFX1250:       ; %bb.0:1369; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11370; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3]1371; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01372; GFX1250-NEXT:    ; return to shader part epilog1373  %zext.offset = zext i32 %voffset to i641374  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1375  %load = load i64, ptr %gep01376  %cast.load = bitcast i64 %load to <2 x float>1377  ret <2 x float> %cast.load1378}1379 1380define amdgpu_ps <2 x float> @flat_load_saddr_i64_immneg128(ptr inreg %sbase, i32 %voffset) {1381; GFX1250-LABEL: flat_load_saddr_i64_immneg128:1382; GFX1250:       ; %bb.0:1383; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11384; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-1281385; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01386; GFX1250-NEXT:    ; return to shader part epilog1387  %zext.offset = zext i32 %voffset to i641388  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1389  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281390  %load = load i64, ptr %gep11391  %cast.load = bitcast i64 %load to <2 x float>1392  ret <2 x float> %cast.load1393}1394 1395define amdgpu_ps <2 x float> @flat_load_saddr_v2f32(ptr inreg %sbase, i32 %voffset) {1396; GFX1250-LABEL: flat_load_saddr_v2f32:1397; GFX1250:       ; %bb.0:1398; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11399; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3]1400; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01401; GFX1250-NEXT:    ; return to shader part epilog1402  %zext.offset = zext i32 %voffset to i641403  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1404  %load = load <2 x float>, ptr %gep01405  ret <2 x float> %load1406}1407 1408define amdgpu_ps <2 x float> @flat_load_saddr_v2f32_immneg128(ptr inreg %sbase, i32 %voffset) {1409; GFX1250-LABEL: flat_load_saddr_v2f32_immneg128:1410; GFX1250:       ; %bb.0:1411; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11412; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-1281413; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01414; GFX1250-NEXT:    ; return to shader part epilog1415  %zext.offset = zext i32 %voffset to i641416  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1417  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281418  %load = load <2 x float>, ptr %gep11419  ret <2 x float> %load1420}1421 1422define amdgpu_ps <2 x float> @flat_load_saddr_v2i32(ptr inreg %sbase, i32 %voffset) {1423; GFX1250-LABEL: flat_load_saddr_v2i32:1424; GFX1250:       ; %bb.0:1425; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11426; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3]1427; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01428; GFX1250-NEXT:    ; return to shader part epilog1429  %zext.offset = zext i32 %voffset to i641430  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1431  %load = load <2 x i32>, ptr %gep01432  %cast.load = bitcast <2 x i32> %load to <2 x float>1433  ret <2 x float> %cast.load1434}1435 1436define amdgpu_ps <2 x float> @flat_load_saddr_v2i32_immneg128(ptr inreg %sbase, i32 %voffset) {1437; GFX1250-LABEL: flat_load_saddr_v2i32_immneg128:1438; GFX1250:       ; %bb.0:1439; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11440; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-1281441; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01442; GFX1250-NEXT:    ; return to shader part epilog1443  %zext.offset = zext i32 %voffset to i641444  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1445  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281446  %load = load <2 x i32>, ptr %gep11447  %cast.load = bitcast <2 x i32> %load to <2 x float>1448  ret <2 x float> %cast.load1449}1450 1451define amdgpu_ps <2 x float> @flat_load_saddr_v4i16(ptr inreg %sbase, i32 %voffset) {1452; GFX1250-LABEL: flat_load_saddr_v4i16:1453; GFX1250:       ; %bb.0:1454; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11455; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3]1456; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01457; GFX1250-NEXT:    ; return to shader part epilog1458  %zext.offset = zext i32 %voffset to i641459  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1460  %load = load <4 x i16>, ptr %gep01461  %cast.load = bitcast <4 x i16> %load to <2 x float>1462  ret <2 x float> %cast.load1463}1464 1465define amdgpu_ps <2 x float> @flat_load_saddr_v4i16_immneg128(ptr inreg %sbase, i32 %voffset) {1466; GFX1250-LABEL: flat_load_saddr_v4i16_immneg128:1467; GFX1250:       ; %bb.0:1468; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11469; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-1281470; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01471; GFX1250-NEXT:    ; return to shader part epilog1472  %zext.offset = zext i32 %voffset to i641473  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1474  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281475  %load = load <4 x i16>, ptr %gep11476  %cast.load = bitcast <4 x i16> %load to <2 x float>1477  ret <2 x float> %cast.load1478}1479 1480define amdgpu_ps <2 x float> @flat_load_saddr_v4f16(ptr inreg %sbase, i32 %voffset) {1481; GFX1250-LABEL: flat_load_saddr_v4f16:1482; GFX1250:       ; %bb.0:1483; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11484; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3]1485; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01486; GFX1250-NEXT:    ; return to shader part epilog1487  %zext.offset = zext i32 %voffset to i641488  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1489  %load = load <4 x half>, ptr %gep01490  %cast.load = bitcast <4 x half> %load to <2 x float>1491  ret <2 x float> %cast.load1492}1493 1494define amdgpu_ps <2 x float> @flat_load_saddr_v4f16_immneg128(ptr inreg %sbase, i32 %voffset) {1495; GFX1250-LABEL: flat_load_saddr_v4f16_immneg128:1496; GFX1250:       ; %bb.0:1497; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11498; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-1281499; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01500; GFX1250-NEXT:    ; return to shader part epilog1501  %zext.offset = zext i32 %voffset to i641502  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1503  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281504  %load = load <4 x half>, ptr %gep11505  %cast.load = bitcast <4 x half> %load to <2 x float>1506  ret <2 x float> %cast.load1507}1508 1509define amdgpu_ps <2 x float> @flat_load_saddr_p1(ptr inreg %sbase, i32 %voffset) {1510; GFX1250-LABEL: flat_load_saddr_p1:1511; GFX1250:       ; %bb.0:1512; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11513; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3]1514; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01515; GFX1250-NEXT:    ; return to shader part epilog1516  %zext.offset = zext i32 %voffset to i641517  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1518  %load = load ptr, ptr %gep01519  %cast.load0 = ptrtoint ptr %load to i641520  %cast.load1 = bitcast i64 %cast.load0 to <2 x float>1521  ret <2 x float> %cast.load11522}1523 1524define amdgpu_ps <2 x float> @flat_load_saddr_p1_immneg128(ptr inreg %sbase, i32 %voffset) {1525; GFX1250-LABEL: flat_load_saddr_p1_immneg128:1526; GFX1250:       ; %bb.0:1527; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11528; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-1281529; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01530; GFX1250-NEXT:    ; return to shader part epilog1531  %zext.offset = zext i32 %voffset to i641532  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1533  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281534  %load = load ptr, ptr %gep11535  %cast.load0 = ptrtoint ptr %load to i641536  %cast.load1 = bitcast i64 %cast.load0 to <2 x float>1537  ret <2 x float> %cast.load11538}1539 1540define amdgpu_ps <3 x float> @flat_load_saddr_v3f32(ptr inreg %sbase, i32 %voffset) {1541; GFX1250-LABEL: flat_load_saddr_v3f32:1542; GFX1250:       ; %bb.0:1543; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11544; GFX1250-NEXT:    flat_load_b96 v[0:2], v0, s[2:3]1545; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01546; GFX1250-NEXT:    ; return to shader part epilog1547  %zext.offset = zext i32 %voffset to i641548  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1549  %load = load <3 x float>, ptr %gep01550  ret <3 x float> %load1551}1552 1553define amdgpu_ps <3 x float> @flat_load_saddr_v3f32_immneg128(ptr inreg %sbase, i32 %voffset) {1554; GFX1250-LABEL: flat_load_saddr_v3f32_immneg128:1555; GFX1250:       ; %bb.0:1556; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11557; GFX1250-NEXT:    flat_load_b96 v[0:2], v0, s[2:3] offset:-1281558; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01559; GFX1250-NEXT:    ; return to shader part epilog1560  %zext.offset = zext i32 %voffset to i641561  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1562  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281563  %load = load <3 x float>, ptr %gep11564  ret <3 x float> %load1565}1566 1567define amdgpu_ps <3 x float> @flat_load_saddr_v3i32(ptr inreg %sbase, i32 %voffset) {1568; GFX1250-LABEL: flat_load_saddr_v3i32:1569; GFX1250:       ; %bb.0:1570; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11571; GFX1250-NEXT:    flat_load_b96 v[0:2], v0, s[2:3]1572; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01573; GFX1250-NEXT:    ; return to shader part epilog1574  %zext.offset = zext i32 %voffset to i641575  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1576  %load = load <3 x i32>, ptr %gep01577  %cast.load = bitcast <3 x i32> %load to <3 x float>1578  ret <3 x float> %cast.load1579}1580 1581define amdgpu_ps <3 x float> @flat_load_saddr_v3i32_immneg128(ptr inreg %sbase, i32 %voffset) {1582; GFX1250-LABEL: flat_load_saddr_v3i32_immneg128:1583; GFX1250:       ; %bb.0:1584; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11585; GFX1250-NEXT:    flat_load_b96 v[0:2], v0, s[2:3] offset:-1281586; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01587; GFX1250-NEXT:    ; return to shader part epilog1588  %zext.offset = zext i32 %voffset to i641589  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1590  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281591  %load = load <3 x i32>, ptr %gep11592  %cast.load = bitcast <3 x i32> %load to <3 x float>1593  ret <3 x float> %cast.load1594}1595 1596define amdgpu_ps <6 x half> @flat_load_saddr_v6f16(ptr inreg %sbase, i32 %voffset) {1597; GFX1250-LABEL: flat_load_saddr_v6f16:1598; GFX1250:       ; %bb.0:1599; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11600; GFX1250-NEXT:    flat_load_b96 v[0:2], v0, s[2:3]1601; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01602; GFX1250-NEXT:    ; return to shader part epilog1603  %zext.offset = zext i32 %voffset to i641604  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1605  %load = load <6 x half>, ptr %gep01606  ret <6 x half> %load1607}1608 1609define amdgpu_ps <6 x half> @flat_load_saddr_v6f16_immneg128(ptr inreg %sbase, i32 %voffset) {1610; GFX1250-LABEL: flat_load_saddr_v6f16_immneg128:1611; GFX1250:       ; %bb.0:1612; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11613; GFX1250-NEXT:    flat_load_b96 v[0:2], v0, s[2:3] offset:-1281614; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01615; GFX1250-NEXT:    ; return to shader part epilog1616  %zext.offset = zext i32 %voffset to i641617  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1618  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281619  %load = load <6 x half>, ptr %gep11620  ret <6 x half> %load1621}1622 1623define amdgpu_ps <4 x float> @flat_load_saddr_v4f32(ptr inreg %sbase, i32 %voffset) {1624; GFX1250-LABEL: flat_load_saddr_v4f32:1625; GFX1250:       ; %bb.0:1626; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11627; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3]1628; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01629; GFX1250-NEXT:    ; return to shader part epilog1630  %zext.offset = zext i32 %voffset to i641631  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1632  %load = load <4 x float>, ptr %gep01633  ret <4 x float> %load1634}1635 1636define amdgpu_ps <4 x float> @flat_load_saddr_v4f32_immneg128(ptr inreg %sbase, i32 %voffset) {1637; GFX1250-LABEL: flat_load_saddr_v4f32_immneg128:1638; GFX1250:       ; %bb.0:1639; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11640; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3] offset:-1281641; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01642; GFX1250-NEXT:    ; return to shader part epilog1643  %zext.offset = zext i32 %voffset to i641644  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1645  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281646  %load = load <4 x float>, ptr %gep11647  ret <4 x float> %load1648}1649 1650define amdgpu_ps <4 x float> @flat_load_saddr_v4i32(ptr inreg %sbase, i32 %voffset) {1651; GFX1250-LABEL: flat_load_saddr_v4i32:1652; GFX1250:       ; %bb.0:1653; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11654; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3]1655; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01656; GFX1250-NEXT:    ; return to shader part epilog1657  %zext.offset = zext i32 %voffset to i641658  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1659  %load = load <4 x i32>, ptr %gep01660  %cast.load = bitcast <4 x i32> %load to <4 x float>1661  ret <4 x float> %cast.load1662}1663 1664define amdgpu_ps <4 x float> @flat_load_saddr_v4i32_immneg128(ptr inreg %sbase, i32 %voffset) {1665; GFX1250-LABEL: flat_load_saddr_v4i32_immneg128:1666; GFX1250:       ; %bb.0:1667; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11668; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3] offset:-1281669; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01670; GFX1250-NEXT:    ; return to shader part epilog1671  %zext.offset = zext i32 %voffset to i641672  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1673  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281674  %load = load <4 x i32>, ptr %gep11675  %cast.load = bitcast <4 x i32> %load to <4 x float>1676  ret <4 x float> %cast.load1677}1678 1679define amdgpu_ps <4 x float> @flat_load_saddr_v2i64(ptr inreg %sbase, i32 %voffset) {1680; GFX1250-LABEL: flat_load_saddr_v2i64:1681; GFX1250:       ; %bb.0:1682; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11683; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3]1684; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01685; GFX1250-NEXT:    ; return to shader part epilog1686  %zext.offset = zext i32 %voffset to i641687  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1688  %load = load <2 x i64>, ptr %gep01689  %cast.load = bitcast <2 x i64> %load to <4 x float>1690  ret <4 x float> %cast.load1691}1692 1693define amdgpu_ps <4 x float> @flat_load_saddr_v2i64_immneg128(ptr inreg %sbase, i32 %voffset) {1694; GFX1250-LABEL: flat_load_saddr_v2i64_immneg128:1695; GFX1250:       ; %bb.0:1696; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11697; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3] offset:-1281698; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01699; GFX1250-NEXT:    ; return to shader part epilog1700  %zext.offset = zext i32 %voffset to i641701  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1702  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281703  %load = load <2 x i64>, ptr %gep11704  %cast.load = bitcast <2 x i64> %load to <4 x float>1705  ret <4 x float> %cast.load1706}1707 1708define amdgpu_ps <4 x float> @flat_load_saddr_i128(ptr inreg %sbase, i32 %voffset) {1709; GFX1250-LABEL: flat_load_saddr_i128:1710; GFX1250:       ; %bb.0:1711; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11712; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3]1713; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01714; GFX1250-NEXT:    ; return to shader part epilog1715  %zext.offset = zext i32 %voffset to i641716  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1717  %load = load i128, ptr %gep01718  %cast.load = bitcast i128 %load to <4 x float>1719  ret <4 x float> %cast.load1720}1721 1722define amdgpu_ps <4 x float> @flat_load_saddr_i128_immneg128(ptr inreg %sbase, i32 %voffset) {1723; GFX1250-LABEL: flat_load_saddr_i128_immneg128:1724; GFX1250:       ; %bb.0:1725; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11726; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3] offset:-1281727; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01728; GFX1250-NEXT:    ; return to shader part epilog1729  %zext.offset = zext i32 %voffset to i641730  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1731  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281732  %load = load i128, ptr %gep11733  %cast.load = bitcast i128 %load to <4 x float>1734  ret <4 x float> %cast.load1735}1736 1737define amdgpu_ps <4 x float> @flat_load_saddr_v2p1(ptr inreg %sbase, i32 %voffset) {1738; GFX1250-LABEL: flat_load_saddr_v2p1:1739; GFX1250:       ; %bb.0:1740; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11741; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3]1742; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01743; GFX1250-NEXT:    ; return to shader part epilog1744  %zext.offset = zext i32 %voffset to i641745  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1746  %load = load <2 x ptr>, ptr %gep01747  %cast.load0 = ptrtoint <2 x ptr> %load to <2 x i64>1748  %cast.load1 = bitcast <2 x i64> %cast.load0 to <4 x float>1749  ret <4 x float> %cast.load11750}1751 1752define amdgpu_ps <4 x float> @flat_load_saddr_v2p1_immneg128(ptr inreg %sbase, i32 %voffset) {1753; GFX1250-LABEL: flat_load_saddr_v2p1_immneg128:1754; GFX1250:       ; %bb.0:1755; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11756; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3] offset:-1281757; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01758; GFX1250-NEXT:    ; return to shader part epilog1759  %zext.offset = zext i32 %voffset to i641760  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1761  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281762  %load = load <2 x ptr>, ptr %gep11763  %cast.load0 = ptrtoint <2 x ptr> %load to <2 x i64>1764  %cast.load1 = bitcast <2 x i64> %cast.load0 to <4 x float>1765  ret <4 x float> %cast.load11766}1767 1768define amdgpu_ps <4 x float> @flat_load_saddr_v4p3(ptr inreg %sbase, i32 %voffset) {1769; GFX1250-LABEL: flat_load_saddr_v4p3:1770; GFX1250:       ; %bb.0:1771; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11772; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3]1773; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01774; GFX1250-NEXT:    ; return to shader part epilog1775  %zext.offset = zext i32 %voffset to i641776  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1777  %load = load <4 x ptr addrspace(3)>, ptr %gep01778  %cast.load0 = ptrtoint <4 x ptr addrspace(3)> %load to <4 x i32>1779  %cast.load1 = bitcast <4 x i32> %cast.load0 to <4 x float>1780  ret <4 x float> %cast.load11781}1782 1783define amdgpu_ps <4 x float> @flat_load_saddr_v4p3_immneg128(ptr inreg %sbase, i32 %voffset) {1784; GFX1250-LABEL: flat_load_saddr_v4p3_immneg128:1785; GFX1250:       ; %bb.0:1786; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11787; GFX1250-NEXT:    flat_load_b128 v[0:3], v0, s[2:3] offset:-1281788; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01789; GFX1250-NEXT:    ; return to shader part epilog1790  %zext.offset = zext i32 %voffset to i641791  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1792  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281793  %load = load <4 x ptr addrspace(3)>, ptr %gep11794  %cast.load0 = ptrtoint <4 x ptr addrspace(3)> %load to <4 x i32>1795  %cast.load1 = bitcast <4 x i32> %cast.load0 to <4 x float>1796  ret <4 x float> %cast.load11797}1798 1799; --------------------------------------------------------------------------------1800; Extending loads1801; --------------------------------------------------------------------------------1802 1803define amdgpu_ps float @flat_sextload_saddr_i8(ptr inreg %sbase, i32 %voffset) {1804; GFX1250-LABEL: flat_sextload_saddr_i8:1805; GFX1250:       ; %bb.0:1806; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11807; GFX1250-NEXT:    flat_load_i8 v0, v0, s[2:3]1808; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01809; GFX1250-NEXT:    ; return to shader part epilog1810  %zext.offset = zext i32 %voffset to i641811  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1812  %load = load i8, ptr %gep01813  %sextload = sext i8 %load to i321814  %cast.load = bitcast i32 %sextload to float1815  ret float %cast.load1816}1817 1818define amdgpu_ps float @flat_sextload_saddr_i8_immneg128(ptr inreg %sbase, i32 %voffset) {1819; GFX1250-LABEL: flat_sextload_saddr_i8_immneg128:1820; GFX1250:       ; %bb.0:1821; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11822; GFX1250-NEXT:    flat_load_i8 v0, v0, s[2:3] offset:-1281823; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01824; GFX1250-NEXT:    ; return to shader part epilog1825  %zext.offset = zext i32 %voffset to i641826  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1827  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281828  %load = load i8, ptr %gep11829  %sextload = sext i8 %load to i321830  %cast.load = bitcast i32 %sextload to float1831  ret float %cast.load1832}1833 1834define amdgpu_ps float @flat_sextload_saddr_i16(ptr inreg %sbase, i32 %voffset) {1835; GFX1250-LABEL: flat_sextload_saddr_i16:1836; GFX1250:       ; %bb.0:1837; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11838; GFX1250-NEXT:    flat_load_i16 v0, v0, s[2:3]1839; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01840; GFX1250-NEXT:    ; return to shader part epilog1841  %zext.offset = zext i32 %voffset to i641842  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1843  %load = load i16, ptr %gep01844  %sextload = sext i16 %load to i321845  %cast.load = bitcast i32 %sextload to float1846  ret float %cast.load1847}1848 1849define amdgpu_ps float @flat_sextload_saddr_i16_immneg128(ptr inreg %sbase, i32 %voffset) {1850; GFX1250-LABEL: flat_sextload_saddr_i16_immneg128:1851; GFX1250:       ; %bb.0:1852; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11853; GFX1250-NEXT:    flat_load_i16 v0, v0, s[2:3] offset:-1281854; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01855; GFX1250-NEXT:    ; return to shader part epilog1856  %zext.offset = zext i32 %voffset to i641857  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1858  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281859  %load = load i16, ptr %gep11860  %sextload = sext i16 %load to i321861  %cast.load = bitcast i32 %sextload to float1862  ret float %cast.load1863}1864 1865define amdgpu_ps float @flat_zextload_saddr_i8(ptr inreg %sbase, i32 %voffset) {1866; GFX1250-LABEL: flat_zextload_saddr_i8:1867; GFX1250:       ; %bb.0:1868; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11869; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3]1870; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01871; GFX1250-NEXT:    ; return to shader part epilog1872  %zext.offset = zext i32 %voffset to i641873  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1874  %load = load i8, ptr %gep01875  %zextload = zext i8 %load to i321876  %cast.load = bitcast i32 %zextload to float1877  ret float %cast.load1878}1879 1880define amdgpu_ps float @flat_zextload_saddr_i8_immneg128(ptr inreg %sbase, i32 %voffset) {1881; GFX1250-LABEL: flat_zextload_saddr_i8_immneg128:1882; GFX1250:       ; %bb.0:1883; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11884; GFX1250-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-1281885; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01886; GFX1250-NEXT:    ; return to shader part epilog1887  %zext.offset = zext i32 %voffset to i641888  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1889  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281890  %load = load i8, ptr %gep11891  %zextload = zext i8 %load to i321892  %cast.load = bitcast i32 %zextload to float1893  ret float %cast.load1894}1895 1896define amdgpu_ps float @flat_zextload_saddr_i16(ptr inreg %sbase, i32 %voffset) {1897; GFX1250-LABEL: flat_zextload_saddr_i16:1898; GFX1250:       ; %bb.0:1899; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11900; GFX1250-NEXT:    flat_load_u16 v0, v0, s[2:3]1901; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01902; GFX1250-NEXT:    ; return to shader part epilog1903  %zext.offset = zext i32 %voffset to i641904  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1905  %load = load i16, ptr %gep01906  %zextload = zext i16 %load to i321907  %cast.load = bitcast i32 %zextload to float1908  ret float %cast.load1909}1910 1911define amdgpu_ps float @flat_zextload_saddr_i16_immneg128(ptr inreg %sbase, i32 %voffset) {1912; GFX1250-LABEL: flat_zextload_saddr_i16_immneg128:1913; GFX1250:       ; %bb.0:1914; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11915; GFX1250-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1281916; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01917; GFX1250-NEXT:    ; return to shader part epilog1918  %zext.offset = zext i32 %voffset to i641919  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1920  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281921  %load = load i16, ptr %gep11922  %zextload = zext i16 %load to i321923  %cast.load = bitcast i32 %zextload to float1924  ret float %cast.load1925}1926 1927; --------------------------------------------------------------------------------1928; Atomic load1929; --------------------------------------------------------------------------------1930 1931define amdgpu_ps float @atomic_flat_load_saddr_i32(ptr inreg %sbase, i32 %voffset) {1932; GFX1250-LABEL: atomic_flat_load_saddr_i32:1933; GFX1250:       ; %bb.0:1934; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11935; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] scope:SCOPE_SYS1936; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01937; GFX1250-NEXT:    global_inv scope:SCOPE_SYS1938; GFX1250-NEXT:    s_wait_loadcnt 0x01939; GFX1250-NEXT:    ; return to shader part epilog1940  %zext.offset = zext i32 %voffset to i641941  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1942  %load = load atomic i32, ptr %gep0 seq_cst, align 41943  %cast.load = bitcast i32 %load to float1944  ret float %cast.load1945}1946 1947define amdgpu_ps float @atomic_flat_load_saddr_i32_immneg128(ptr inreg %sbase, i32 %voffset) {1948; GFX1250-LABEL: atomic_flat_load_saddr_i32_immneg128:1949; GFX1250:       ; %bb.0:1950; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11951; GFX1250-NEXT:    flat_load_b32 v0, v0, s[2:3] offset:-128 scope:SCOPE_SYS1952; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01953; GFX1250-NEXT:    global_inv scope:SCOPE_SYS1954; GFX1250-NEXT:    s_wait_loadcnt 0x01955; GFX1250-NEXT:    ; return to shader part epilog1956  %zext.offset = zext i32 %voffset to i641957  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1958  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281959  %load = load atomic i32, ptr %gep1 seq_cst, align 41960  %cast.load = bitcast i32 %load to float1961  ret float %cast.load1962}1963 1964define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64(ptr inreg %sbase, i32 %voffset) {1965; GFX1250-LABEL: atomic_flat_load_saddr_i64:1966; GFX1250:       ; %bb.0:1967; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11968; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] scope:SCOPE_SYS1969; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01970; GFX1250-NEXT:    global_inv scope:SCOPE_SYS1971; GFX1250-NEXT:    s_wait_loadcnt 0x01972; GFX1250-NEXT:    ; return to shader part epilog1973  %zext.offset = zext i32 %voffset to i641974  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1975  %load = load atomic i64, ptr %gep0 seq_cst, align 81976  %cast.load = bitcast i64 %load to <2 x float>1977  ret <2 x float> %cast.load1978}1979 1980define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64_immneg128(ptr inreg %sbase, i32 %voffset) {1981; GFX1250-LABEL: atomic_flat_load_saddr_i64_immneg128:1982; GFX1250:       ; %bb.0:1983; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11984; GFX1250-NEXT:    flat_load_b64 v[0:1], v0, s[2:3] offset:-128 scope:SCOPE_SYS1985; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x01986; GFX1250-NEXT:    global_inv scope:SCOPE_SYS1987; GFX1250-NEXT:    s_wait_loadcnt 0x01988; GFX1250-NEXT:    ; return to shader part epilog1989  %zext.offset = zext i32 %voffset to i641990  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset1991  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1281992  %load = load atomic i64, ptr %gep1 seq_cst, align 81993  %cast.load = bitcast i64 %load to <2 x float>1994  ret <2 x float> %cast.load1995}1996 1997; --------------------------------------------------------------------------------1998; D16 load (low 16)1999; --------------------------------------------------------------------------------2000 2001define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase, i32 %voffset) {2002; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_undef_hi:2003; GFX1250-SDAG:       ; %bb.0:2004; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12005; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]2006; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02007; GFX1250-SDAG-NEXT:    ; return to shader part epilog2008;2009; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_undef_hi:2010; GFX1250-GISEL:       ; %bb.0:2011; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12012; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]2013; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02014; GFX1250-GISEL-NEXT:    ; return to shader part epilog2015;2016; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_undef_hi:2017; GFX1250-NOECC:       ; %bb.0:2018; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12019; GFX1250-NOECC-NEXT:    flat_load_d16_b16 v0, v0, s[2:3]2020; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02021; GFX1250-NOECC-NEXT:    ; return to shader part epilog2022  %zext.offset = zext i32 %voffset to i642023  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2024  %load = load i16, ptr %gep02025  %build = insertelement <2 x i16> undef, i16 %load, i32 02026  %cast = bitcast <2 x i16> %build to <2 x half>2027  ret <2 x half> %cast2028}2029 2030define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi_immneg128(ptr inreg %sbase, i32 %voffset) {2031; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:2032; GFX1250-SDAG:       ; %bb.0:2033; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12034; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282035; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02036; GFX1250-SDAG-NEXT:    ; return to shader part epilog2037;2038; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:2039; GFX1250-GISEL:       ; %bb.0:2040; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12041; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282042; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02043; GFX1250-GISEL-NEXT:    ; return to shader part epilog2044;2045; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_undef_hi_immneg128:2046; GFX1250-NOECC:       ; %bb.0:2047; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12048; GFX1250-NOECC-NEXT:    flat_load_d16_b16 v0, v0, s[2:3] offset:-1282049; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02050; GFX1250-NOECC-NEXT:    ; return to shader part epilog2051  %zext.offset = zext i32 %voffset to i642052  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2053  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282054  %load = load i16, ptr %gep12055  %build = insertelement <2 x i16> undef, i16 %load, i32 02056  %cast = bitcast <2 x i16> %build to <2 x half>2057  ret <2 x half> %cast2058}2059 2060define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi(ptr inreg %sbase, i32 %voffset) {2061; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_zero_hi:2062; GFX1250-SDAG:       ; %bb.0:2063; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12064; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]2065; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02066; GFX1250-SDAG-NEXT:    v_and_b32_e32 v0, 0xffff, v02067; GFX1250-SDAG-NEXT:    ; return to shader part epilog2068;2069; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_zero_hi:2070; GFX1250-GISEL:       ; %bb.0:2071; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12072; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]2073; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02074; GFX1250-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v02075; GFX1250-GISEL-NEXT:    ; return to shader part epilog2076;2077; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zero_hi:2078; GFX1250-NOECC:       ; %bb.0:2079; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12080; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v1, 02081; GFX1250-NOECC-NEXT:    flat_load_d16_b16 v1, v0, s[2:3]2082; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02083; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12084; GFX1250-NOECC-NEXT:    ; return to shader part epilog2085  %zext.offset = zext i32 %voffset to i642086  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2087  %load = load i16, ptr %gep02088  %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 02089  %cast = bitcast <2 x i16> %build to <2 x half>2090  ret <2 x half> %cast2091}2092 2093define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi_immneg128(ptr inreg %sbase, i32 %voffset) {2094; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_zero_hi_immneg128:2095; GFX1250-SDAG:       ; %bb.0:2096; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12097; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282098; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02099; GFX1250-SDAG-NEXT:    v_and_b32_e32 v0, 0xffff, v02100; GFX1250-SDAG-NEXT:    ; return to shader part epilog2101;2102; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_zero_hi_immneg128:2103; GFX1250-GISEL:       ; %bb.0:2104; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12105; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282106; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02107; GFX1250-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v02108; GFX1250-GISEL-NEXT:    ; return to shader part epilog2109;2110; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zero_hi_immneg128:2111; GFX1250-NOECC:       ; %bb.0:2112; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12113; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v1, 02114; GFX1250-NOECC-NEXT:    flat_load_d16_b16 v1, v0, s[2:3] offset:-1282115; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02116; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12117; GFX1250-NOECC-NEXT:    ; return to shader part epilog2118  %zext.offset = zext i32 %voffset to i642119  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2120  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282121  %load = load i16, ptr %gep12122  %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 02123  %cast = bitcast <2 x i16> %build to <2 x half>2124  ret <2 x half> %cast2125}2126 2127define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2128; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_reg_hi:2129; GFX1250-SDAG:       ; %bb.0:2130; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12131; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]2132; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02133; GFX1250-SDAG-NEXT:    v_bfi_b32 v0, 0xffff, v0, v12134; GFX1250-SDAG-NEXT:    ; return to shader part epilog2135;2136; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_reg_hi:2137; GFX1250-GISEL:       ; %bb.0:2138; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12139; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]2140; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02141; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff0000, v1, v02142; GFX1250-GISEL-NEXT:    ; return to shader part epilog2143;2144; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_reg_hi:2145; GFX1250-NOECC:       ; %bb.0:2146; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12147; GFX1250-NOECC-NEXT:    flat_load_d16_b16 v1, v0, s[2:3]2148; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02149; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12150; GFX1250-NOECC-NEXT:    ; return to shader part epilog2151  %zext.offset = zext i32 %voffset to i642152  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2153  %load = load i16, ptr %gep02154  %build = insertelement <2 x i16> %reg, i16 %load, i32 02155  %cast = bitcast <2 x i16> %build to <2 x half>2156  ret <2 x half> %cast2157}2158 2159define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi_immneg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2160; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_reg_hi_immneg128:2161; GFX1250-SDAG:       ; %bb.0:2162; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12163; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282164; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02165; GFX1250-SDAG-NEXT:    v_bfi_b32 v0, 0xffff, v0, v12166; GFX1250-SDAG-NEXT:    ; return to shader part epilog2167;2168; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_reg_hi_immneg128:2169; GFX1250-GISEL:       ; %bb.0:2170; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12171; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282172; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02173; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff0000, v1, v02174; GFX1250-GISEL-NEXT:    ; return to shader part epilog2175;2176; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_reg_hi_immneg128:2177; GFX1250-NOECC:       ; %bb.0:2178; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12179; GFX1250-NOECC-NEXT:    flat_load_d16_b16 v1, v0, s[2:3] offset:-1282180; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02181; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12182; GFX1250-NOECC-NEXT:    ; return to shader part epilog2183  %zext.offset = zext i32 %voffset to i642184  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2185  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282186  %load = load i16, ptr %gep12187  %build = insertelement <2 x i16> %reg, i16 %load, i32 02188  %cast = bitcast <2 x i16> %build to <2 x half>2189  ret <2 x half> %cast2190}2191 2192define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2193; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi:2194; GFX1250-SDAG:       ; %bb.0:2195; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12196; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3]2197; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02198; GFX1250-SDAG-NEXT:    v_bfi_b32 v0, 0xffff, v0, v12199; GFX1250-SDAG-NEXT:    ; return to shader part epilog2200;2201; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi:2202; GFX1250-GISEL:       ; %bb.0:2203; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12204; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[2:3]2205; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02206; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff0000, v1, v02207; GFX1250-GISEL-NEXT:    ; return to shader part epilog2208;2209; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi:2210; GFX1250-NOECC:       ; %bb.0:2211; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12212; GFX1250-NOECC-NEXT:    flat_load_d16_u8 v1, v0, s[2:3]2213; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02214; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12215; GFX1250-NOECC-NEXT:    ; return to shader part epilog2216  %zext.offset = zext i32 %voffset to i642217  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2218  %load = load i8, ptr %gep02219  %zext.load = zext i8 %load to i162220  %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 02221  %cast = bitcast <2 x i16> %build to <2 x half>2222  ret <2 x half> %cast2223}2224 2225define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2226; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128:2227; GFX1250-SDAG:       ; %bb.0:2228; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12229; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-1282230; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02231; GFX1250-SDAG-NEXT:    v_bfi_b32 v0, 0xffff, v0, v12232; GFX1250-SDAG-NEXT:    ; return to shader part epilog2233;2234; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128:2235; GFX1250-GISEL:       ; %bb.0:2236; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12237; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-1282238; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02239; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff0000, v1, v02240; GFX1250-GISEL-NEXT:    ; return to shader part epilog2241;2242; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128:2243; GFX1250-NOECC:       ; %bb.0:2244; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12245; GFX1250-NOECC-NEXT:    flat_load_d16_u8 v1, v0, s[2:3] offset:-1282246; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02247; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12248; GFX1250-NOECC-NEXT:    ; return to shader part epilog2249  %zext.offset = zext i32 %voffset to i642250  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2251  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282252  %load = load i8, ptr %gep12253  %zext.load = zext i8 %load to i162254  %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 02255  %cast = bitcast <2 x i16> %build to <2 x half>2256  ret <2 x half> %cast2257}2258 2259define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2260; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi:2261; GFX1250-SDAG:       ; %bb.0:2262; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12263; GFX1250-SDAG-NEXT:    flat_load_i8 v0, v0, s[2:3]2264; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02265; GFX1250-SDAG-NEXT:    v_bfi_b32 v0, 0xffff, v0, v12266; GFX1250-SDAG-NEXT:    ; return to shader part epilog2267;2268; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi:2269; GFX1250-GISEL:       ; %bb.0:2270; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12271; GFX1250-GISEL-NEXT:    flat_load_i8 v0, v0, s[2:3]2272; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02273; GFX1250-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v02274; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)2275; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff0000, v1, v02276; GFX1250-GISEL-NEXT:    ; return to shader part epilog2277;2278; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi:2279; GFX1250-NOECC:       ; %bb.0:2280; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12281; GFX1250-NOECC-NEXT:    flat_load_d16_i8 v1, v0, s[2:3]2282; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02283; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12284; GFX1250-NOECC-NEXT:    ; return to shader part epilog2285  %zext.offset = zext i32 %voffset to i642286  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2287  %load = load i8, ptr %gep02288  %sext.load = sext i8 %load to i162289  %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 02290  %cast = bitcast <2 x i16> %build to <2 x half>2291  ret <2 x half> %cast2292}2293 2294define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2295; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128:2296; GFX1250-SDAG:       ; %bb.0:2297; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12298; GFX1250-SDAG-NEXT:    flat_load_i8 v0, v0, s[2:3] offset:-1282299; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02300; GFX1250-SDAG-NEXT:    v_bfi_b32 v0, 0xffff, v0, v12301; GFX1250-SDAG-NEXT:    ; return to shader part epilog2302;2303; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128:2304; GFX1250-GISEL:       ; %bb.0:2305; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12306; GFX1250-GISEL-NEXT:    flat_load_i8 v0, v0, s[2:3] offset:-1282307; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02308; GFX1250-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v02309; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)2310; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff0000, v1, v02311; GFX1250-GISEL-NEXT:    ; return to shader part epilog2312;2313; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128:2314; GFX1250-NOECC:       ; %bb.0:2315; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12316; GFX1250-NOECC-NEXT:    flat_load_d16_i8 v1, v0, s[2:3] offset:-1282317; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02318; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12319; GFX1250-NOECC-NEXT:    ; return to shader part epilog2320  %zext.offset = zext i32 %voffset to i642321  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2322  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282323  %load = load i8, ptr %gep12324  %sext.load = sext i8 %load to i162325  %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 02326  %cast = bitcast <2 x i16> %build to <2 x half>2327  ret <2 x half> %cast2328}2329 2330; --------------------------------------------------------------------------------2331; D16 hi load (hi16)2332; --------------------------------------------------------------------------------2333 2334define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase, i32 %voffset) {2335; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_undef_hi:2336; GFX1250-SDAG:       ; %bb.0:2337; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12338; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]2339; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02340; GFX1250-SDAG-NEXT:    v_lshlrev_b32_e32 v0, 16, v02341; GFX1250-SDAG-NEXT:    ; return to shader part epilog2342;2343; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_undef_hi:2344; GFX1250-GISEL:       ; %bb.0:2345; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12346; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]2347; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02348; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02349; GFX1250-GISEL-NEXT:    ; return to shader part epilog2350;2351; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_undef_hi:2352; GFX1250-NOECC:       ; %bb.0:2353; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12354; GFX1250-NOECC-NEXT:    flat_load_d16_hi_b16 v0, v0, s[2:3]2355; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02356; GFX1250-NOECC-NEXT:    ; return to shader part epilog2357  %zext.offset = zext i32 %voffset to i642358  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2359  %load = load i16, ptr %gep02360  %build = insertelement <2 x i16> undef, i16 %load, i32 12361  %cast = bitcast <2 x i16> %build to <2 x half>2362  ret <2 x half> %cast2363}2364 2365define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr inreg %sbase, i32 %voffset) {2366; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_undef_hi_immneg128:2367; GFX1250-SDAG:       ; %bb.0:2368; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12369; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282370; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02371; GFX1250-SDAG-NEXT:    v_lshlrev_b32_e32 v0, 16, v02372; GFX1250-SDAG-NEXT:    ; return to shader part epilog2373;2374; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_undef_hi_immneg128:2375; GFX1250-GISEL:       ; %bb.0:2376; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12377; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282378; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02379; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02380; GFX1250-GISEL-NEXT:    ; return to shader part epilog2381;2382; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_undef_hi_immneg128:2383; GFX1250-NOECC:       ; %bb.0:2384; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12385; GFX1250-NOECC-NEXT:    flat_load_d16_hi_b16 v0, v0, s[2:3] offset:-1282386; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02387; GFX1250-NOECC-NEXT:    ; return to shader part epilog2388  %zext.offset = zext i32 %voffset to i642389  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2390  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282391  %load = load i16, ptr %gep12392  %build = insertelement <2 x i16> undef, i16 %load, i32 12393  %cast = bitcast <2 x i16> %build to <2 x half>2394  ret <2 x half> %cast2395}2396 2397define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi(ptr inreg %sbase, i32 %voffset) {2398; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_zero_hi:2399; GFX1250-SDAG:       ; %bb.0:2400; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12401; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]2402; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02403; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, 0, 0x50401002404; GFX1250-SDAG-NEXT:    ; return to shader part epilog2405;2406; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_zero_hi:2407; GFX1250-GISEL:       ; %bb.0:2408; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12409; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]2410; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02411; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02412; GFX1250-GISEL-NEXT:    ; return to shader part epilog2413;2414; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi:2415; GFX1250-NOECC-SDAG-TRUE16:       ; %bb.0:2416; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12417; GFX1250-NOECC-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, 02418; GFX1250-NOECC-SDAG-TRUE16-NEXT:    flat_load_d16_hi_b16 v1, v0, s[2:3]2419; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x02420; GFX1250-NOECC-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, v12421; GFX1250-NOECC-SDAG-TRUE16-NEXT:    ; return to shader part epilog2422;2423; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi:2424; GFX1250-NOECC-SDAG-FAKE16:       ; %bb.0:2425; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12426; GFX1250-NOECC-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 02427; GFX1250-NOECC-SDAG-FAKE16-NEXT:    flat_load_d16_hi_b16 v1, v0, s[2:3]2428; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x02429; GFX1250-NOECC-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, v12430; GFX1250-NOECC-SDAG-FAKE16-NEXT:    ; return to shader part epilog2431  %zext.offset = zext i32 %voffset to i642432  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2433  %load = load i16, ptr %gep02434  %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 12435  %cast = bitcast <2 x i16> %build to <2 x half>2436  ret <2 x half> %cast2437}2438 2439define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi_immneg128(ptr inreg %sbase, i32 %voffset) {2440; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_zero_hi_immneg128:2441; GFX1250-SDAG:       ; %bb.0:2442; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12443; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282444; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02445; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, 0, 0x50401002446; GFX1250-SDAG-NEXT:    ; return to shader part epilog2447;2448; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_zero_hi_immneg128:2449; GFX1250-GISEL:       ; %bb.0:2450; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12451; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282452; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02453; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02454; GFX1250-GISEL-NEXT:    ; return to shader part epilog2455;2456; GFX1250-NOECC-SDAG-TRUE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi_immneg128:2457; GFX1250-NOECC-SDAG-TRUE16:       ; %bb.0:2458; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12459; GFX1250-NOECC-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v1.l, 02460; GFX1250-NOECC-SDAG-TRUE16-NEXT:    flat_load_d16_hi_b16 v1, v0, s[2:3] offset:-1282461; GFX1250-NOECC-SDAG-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x02462; GFX1250-NOECC-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v0, v12463; GFX1250-NOECC-SDAG-TRUE16-NEXT:    ; return to shader part epilog2464;2465; GFX1250-NOECC-SDAG-FAKE16-LABEL: flat_load_saddr_i16_d16hi_zero_hi_immneg128:2466; GFX1250-NOECC-SDAG-FAKE16:       ; %bb.0:2467; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12468; GFX1250-NOECC-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, 02469; GFX1250-NOECC-SDAG-FAKE16-NEXT:    flat_load_d16_hi_b16 v1, v0, s[2:3] offset:-1282470; GFX1250-NOECC-SDAG-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x02471; GFX1250-NOECC-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, v12472; GFX1250-NOECC-SDAG-FAKE16-NEXT:    ; return to shader part epilog2473  %zext.offset = zext i32 %voffset to i642474  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2475  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282476  %load = load i16, ptr %gep12477  %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 12478  %cast = bitcast <2 x i16> %build to <2 x half>2479  ret <2 x half> %cast2480}2481 2482define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2483; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_reg_hi:2484; GFX1250-SDAG:       ; %bb.0:2485; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12486; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3]2487; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02488; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, v1, 0x50401002489; GFX1250-SDAG-NEXT:    ; return to shader part epilog2490;2491; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_reg_hi:2492; GFX1250-GISEL:       ; %bb.0:2493; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12494; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3]2495; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02496; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02497; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)2498; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff, v1, v02499; GFX1250-GISEL-NEXT:    ; return to shader part epilog2500;2501; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_reg_hi:2502; GFX1250-NOECC:       ; %bb.0:2503; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12504; GFX1250-NOECC-NEXT:    flat_load_d16_hi_b16 v1, v0, s[2:3]2505; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02506; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12507; GFX1250-NOECC-NEXT:    ; return to shader part epilog2508  %zext.offset = zext i32 %voffset to i642509  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2510  %load = load i16, ptr %gep02511  %build = insertelement <2 x i16> %reg, i16 %load, i32 12512  %cast = bitcast <2 x i16> %build to <2 x half>2513  ret <2 x half> %cast2514}2515 2516define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi_immneg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2517; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_reg_hi_immneg128:2518; GFX1250-SDAG:       ; %bb.0:2519; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12520; GFX1250-SDAG-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282521; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02522; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, v1, 0x50401002523; GFX1250-SDAG-NEXT:    ; return to shader part epilog2524;2525; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_reg_hi_immneg128:2526; GFX1250-GISEL:       ; %bb.0:2527; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12528; GFX1250-GISEL-NEXT:    flat_load_u16 v0, v0, s[2:3] offset:-1282529; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02530; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02531; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)2532; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff, v1, v02533; GFX1250-GISEL-NEXT:    ; return to shader part epilog2534;2535; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_reg_hi_immneg128:2536; GFX1250-NOECC:       ; %bb.0:2537; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12538; GFX1250-NOECC-NEXT:    flat_load_d16_hi_b16 v1, v0, s[2:3] offset:-1282539; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02540; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12541; GFX1250-NOECC-NEXT:    ; return to shader part epilog2542  %zext.offset = zext i32 %voffset to i642543  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2544  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282545  %load = load i16, ptr %gep12546  %build = insertelement <2 x i16> %reg, i16 %load, i32 12547  %cast = bitcast <2 x i16> %build to <2 x half>2548  ret <2 x half> %cast2549}2550 2551define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2552; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi:2553; GFX1250-SDAG:       ; %bb.0:2554; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12555; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3]2556; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02557; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, v1, 0x50401002558; GFX1250-SDAG-NEXT:    ; return to shader part epilog2559;2560; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi:2561; GFX1250-GISEL:       ; %bb.0:2562; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12563; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[2:3]2564; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02565; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02566; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)2567; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff, v1, v02568; GFX1250-GISEL-NEXT:    ; return to shader part epilog2569;2570; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi:2571; GFX1250-NOECC:       ; %bb.0:2572; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12573; GFX1250-NOECC-NEXT:    flat_load_d16_hi_u8 v1, v0, s[2:3]2574; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02575; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12576; GFX1250-NOECC-NEXT:    ; return to shader part epilog2577  %zext.offset = zext i32 %voffset to i642578  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2579  %load = load i8, ptr %gep02580  %zext.load = zext i8 %load to i162581  %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 12582  %cast = bitcast <2 x i16> %build to <2 x half>2583  ret <2 x half> %cast2584}2585 2586define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2587; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:2588; GFX1250-SDAG:       ; %bb.0:2589; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12590; GFX1250-SDAG-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-1282591; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02592; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, v1, 0x50401002593; GFX1250-SDAG-NEXT:    ; return to shader part epilog2594;2595; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:2596; GFX1250-GISEL:       ; %bb.0:2597; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12598; GFX1250-GISEL-NEXT:    flat_load_u8 v0, v0, s[2:3] offset:-1282599; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02600; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02601; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)2602; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff, v1, v02603; GFX1250-GISEL-NEXT:    ; return to shader part epilog2604;2605; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128:2606; GFX1250-NOECC:       ; %bb.0:2607; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12608; GFX1250-NOECC-NEXT:    flat_load_d16_hi_u8 v1, v0, s[2:3] offset:-1282609; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02610; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12611; GFX1250-NOECC-NEXT:    ; return to shader part epilog2612  %zext.offset = zext i32 %voffset to i642613  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2614  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282615  %load = load i8, ptr %gep12616  %zext.load = zext i8 %load to i162617  %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 12618  %cast = bitcast <2 x i16> %build to <2 x half>2619  ret <2 x half> %cast2620}2621 2622define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2623; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi:2624; GFX1250-SDAG:       ; %bb.0:2625; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12626; GFX1250-SDAG-NEXT:    flat_load_i8 v0, v0, s[2:3]2627; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02628; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, v1, 0x50401002629; GFX1250-SDAG-NEXT:    ; return to shader part epilog2630;2631; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi:2632; GFX1250-GISEL:       ; %bb.0:2633; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12634; GFX1250-GISEL-NEXT:    flat_load_i8 v0, v0, s[2:3]2635; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02636; GFX1250-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v02637; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2638; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02639; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff, v1, v02640; GFX1250-GISEL-NEXT:    ; return to shader part epilog2641;2642; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi:2643; GFX1250-NOECC:       ; %bb.0:2644; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12645; GFX1250-NOECC-NEXT:    flat_load_d16_hi_i8 v1, v0, s[2:3]2646; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02647; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12648; GFX1250-NOECC-NEXT:    ; return to shader part epilog2649  %zext.offset = zext i32 %voffset to i642650  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2651  %load = load i8, ptr %gep02652  %sext.load = sext i8 %load to i162653  %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 12654  %cast = bitcast <2 x i16> %build to <2 x half>2655  ret <2 x half> %cast2656}2657 2658define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %reg) {2659; GFX1250-SDAG-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:2660; GFX1250-SDAG:       ; %bb.0:2661; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12662; GFX1250-SDAG-NEXT:    flat_load_i8 v0, v0, s[2:3] offset:-1282663; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02664; GFX1250-SDAG-NEXT:    v_perm_b32 v0, v0, v1, 0x50401002665; GFX1250-SDAG-NEXT:    ; return to shader part epilog2666;2667; GFX1250-GISEL-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:2668; GFX1250-GISEL:       ; %bb.0:2669; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12670; GFX1250-GISEL-NEXT:    flat_load_i8 v0, v0, s[2:3] offset:-1282671; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02672; GFX1250-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v02673; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2674; GFX1250-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 16, v02675; GFX1250-GISEL-NEXT:    v_and_or_b32 v0, 0xffff, v1, v02676; GFX1250-GISEL-NEXT:    ; return to shader part epilog2677;2678; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128:2679; GFX1250-NOECC:       ; %bb.0:2680; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12681; GFX1250-NOECC-NEXT:    flat_load_d16_hi_i8 v1, v0, s[2:3] offset:-1282682; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02683; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, v12684; GFX1250-NOECC-NEXT:    ; return to shader part epilog2685  %zext.offset = zext i32 %voffset to i642686  %gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset2687  %gep1 = getelementptr inbounds i8, ptr %gep0, i64 -1282688  %load = load i8, ptr %gep12689  %sext.load = sext i8 %load to i162690  %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 12691  %cast = bitcast <2 x i16> %build to <2 x half>2692  ret <2 x half> %cast2693}2694 2695; --------------------------------------------------------------------------------2696; or-with-constant as add2697; --------------------------------------------------------------------------------2698 2699; Check add-as-or with split 64-bit or.2700define amdgpu_ps float @flat_load_saddr_i8_offset_or_i64_imm_offset_16(ptr addrspace(6) inreg %sbase, i32 %idx) {2701; GFX1250-LABEL: flat_load_saddr_i8_offset_or_i64_imm_offset_16:2702; GFX1250:       ; %bb.0:2703; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12704; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_bitop2_b32 v0, 16, v0 bitop3:0x542705; GFX1250-NEXT:    flat_load_u8 v0, v[0:1]2706; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x02707; GFX1250-NEXT:    ; return to shader part epilog2708  %zext.idx = zext i32 %idx to i642709  %or = or i64 %zext.idx, 162710  %addr = inttoptr i64 %or to ptr2711  %load = load i8, ptr %addr2712  %zext = zext i8 %load to i322713  %to.vgpr = bitcast i32 %zext to float2714  ret float %to.vgpr2715}2716 2717define amdgpu_ps float @flat_load_saddr_i8_offset_or_i64_imm_offset_4160(ptr addrspace(6) inreg %sbase, i32 %idx) {2718; GFX1250-LABEL: flat_load_saddr_i8_offset_or_i64_imm_offset_4160:2719; GFX1250:       ; %bb.0:2720; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12721; GFX1250-NEXT:    v_or_b32_e32 v0, 0x1040, v02722; GFX1250-NEXT:    v_mov_b32_e32 v1, 02723; GFX1250-NEXT:    flat_load_u8 v0, v[0:1]2724; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x02725; GFX1250-NEXT:    ; return to shader part epilog2726  %zext.idx = zext i32 %idx to i642727  %or = or i64 %zext.idx, 41602728  %addr = inttoptr i64 %or to ptr2729  %load = load i8, ptr %addr2730  %zext = zext i8 %load to i322731  %to.vgpr = bitcast i32 %zext to float2732  ret float %to.vgpr2733}2734 2735; --------------------------------------------------------------------------------2736; Full 64-bit scalar add.2737; --------------------------------------------------------------------------------2738 2739define amdgpu_ps void @flat_addr_64bit_lsr_iv(ptr inreg %arg) {2740; GFX1250-SDAG-LABEL: flat_addr_64bit_lsr_iv:2741; GFX1250-SDAG:       ; %bb.0: ; %bb2742; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12743; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 02744; GFX1250-SDAG-NEXT:    s_mov_b64 s[0:1], 02745; GFX1250-SDAG-NEXT:  .LBB116_1: ; %bb32746; GFX1250-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=12747; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2748; GFX1250-SDAG-NEXT:    s_add_nc_u64 s[4:5], s[2:3], s[0:1]2749; GFX1250-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], 42750; GFX1250-SDAG-NEXT:    s_wait_dscnt 0x02751; GFX1250-SDAG-NEXT:    flat_load_b32 v1, v0, s[4:5] scope:SCOPE_SYS2752; GFX1250-SDAG-NEXT:    s_wait_loadcnt 0x02753; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s0, 0x4002754; GFX1250-SDAG-NEXT:    s_cbranch_scc0 .LBB116_12755; GFX1250-SDAG-NEXT:  ; %bb.2: ; %bb22756; GFX1250-SDAG-NEXT:    s_endpgm2757;2758; GFX1250-GISEL-LABEL: flat_addr_64bit_lsr_iv:2759; GFX1250-GISEL:       ; %bb.0: ; %bb2760; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12761; GFX1250-GISEL-NEXT:    s_mov_b64 s[0:1], 02762; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[2:3]2763; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]2764; GFX1250-GISEL-NEXT:  .LBB116_1: ; %bb32765; GFX1250-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=12766; GFX1250-GISEL-NEXT:    s_wait_dscnt 0x02767; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2768; GFX1250-GISEL-NEXT:    v_add_co_u32 v4, vcc_lo, v0, v22769; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo2770; GFX1250-GISEL-NEXT:    v_add_nc_u64_e32 v[2:3], 4, v[2:3]2771; GFX1250-GISEL-NEXT:    flat_load_b32 v4, v[4:5] scope:SCOPE_SYS2772; GFX1250-GISEL-NEXT:    s_wait_loadcnt 0x02773; GFX1250-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x400, v22774; GFX1250-GISEL-NEXT:    s_cbranch_vccz .LBB116_12775; GFX1250-GISEL-NEXT:  ; %bb.2: ; %bb22776; GFX1250-GISEL-NEXT:    s_endpgm2777;2778; GFX1250-NOECC-LABEL: flat_addr_64bit_lsr_iv:2779; GFX1250-NOECC:       ; %bb.0: ; %bb2780; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12781; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, 02782; GFX1250-NOECC-NEXT:    s_mov_b64 s[0:1], 02783; GFX1250-NOECC-NEXT:  .LBB116_1: ; %bb32784; GFX1250-NOECC-NEXT:    ; =>This Inner Loop Header: Depth=12785; GFX1250-NOECC-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2786; GFX1250-NOECC-NEXT:    s_add_nc_u64 s[4:5], s[2:3], s[0:1]2787; GFX1250-NOECC-NEXT:    s_add_nc_u64 s[0:1], s[0:1], 42788; GFX1250-NOECC-NEXT:    s_wait_dscnt 0x02789; GFX1250-NOECC-NEXT:    flat_load_b32 v1, v0, s[4:5] scope:SCOPE_SYS2790; GFX1250-NOECC-NEXT:    s_wait_loadcnt 0x02791; GFX1250-NOECC-NEXT:    s_cmp_eq_u32 s0, 0x4002792; GFX1250-NOECC-NEXT:    s_cbranch_scc0 .LBB116_12793; GFX1250-NOECC-NEXT:  ; %bb.2: ; %bb22794; GFX1250-NOECC-NEXT:    s_endpgm2795bb:2796  br label %bb32797 2798bb2:                                              ; preds = %bb32799  ret void2800 2801bb3:                                              ; preds = %bb3, %bb2802  %i = phi i32 [ 0, %bb ], [ %i8, %bb3 ]2803  %i4 = zext i32 %i to i642804  %i5 = getelementptr inbounds float, ptr %arg, i64 %i42805  %i6 = load volatile float, ptr %i5, align 42806  %i8 = add nuw nsw i32 %i, 12807  %i9 = icmp eq i32 %i8, 2562808  br i1 %i9, label %bb2, label %bb32809}2810 2811; Make sure we only have a single zero vaddr initialization.2812 2813define amdgpu_ps void @flat_addr_64bit_lsr_iv_multiload(ptr inreg %arg, ptr inreg %arg.1) {2814; GFX1250-SDAG-LABEL: flat_addr_64bit_lsr_iv_multiload:2815; GFX1250-SDAG:       ; %bb.0: ; %bb2816; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12817; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 02818; GFX1250-SDAG-NEXT:    s_mov_b64 s[0:1], 02819; GFX1250-SDAG-NEXT:  .LBB117_1: ; %bb32820; GFX1250-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=12821; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2822; GFX1250-SDAG-NEXT:    s_add_nc_u64 s[4:5], s[2:3], s[0:1]2823; GFX1250-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], 42824; GFX1250-SDAG-NEXT:    s_wait_dscnt 0x02825; GFX1250-SDAG-NEXT:    flat_load_b32 v1, v0, s[4:5] scope:SCOPE_SYS2826; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x02827; GFX1250-SDAG-NEXT:    flat_load_b32 v1, v0, s[4:5] scope:SCOPE_SYS2828; GFX1250-SDAG-NEXT:    s_wait_loadcnt 0x02829; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s0, 0x4002830; GFX1250-SDAG-NEXT:    ; kill: killed $sgpr4_sgpr52831; GFX1250-SDAG-NEXT:    s_cbranch_scc0 .LBB117_12832; GFX1250-SDAG-NEXT:  ; %bb.2: ; %bb22833; GFX1250-SDAG-NEXT:    s_endpgm2834;2835; GFX1250-GISEL-LABEL: flat_addr_64bit_lsr_iv_multiload:2836; GFX1250-GISEL:       ; %bb.0: ; %bb2837; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12838; GFX1250-GISEL-NEXT:    s_mov_b64 s[0:1], 02839; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[2:3]2840; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]2841; GFX1250-GISEL-NEXT:  .LBB117_1: ; %bb32842; GFX1250-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=12843; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2844; GFX1250-GISEL-NEXT:    v_add_co_u32 v4, vcc_lo, v0, v22845; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo2846; GFX1250-GISEL-NEXT:    v_add_nc_u64_e32 v[2:3], 4, v[2:3]2847; GFX1250-GISEL-NEXT:    ; kill: killed $vgpr4 killed $vgpr52848; GFX1250-GISEL-NEXT:    s_wait_dscnt 0x02849; GFX1250-GISEL-NEXT:    flat_load_b32 v6, v[4:5] scope:SCOPE_SYS2850; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x02851; GFX1250-GISEL-NEXT:    flat_load_b32 v6, v[4:5] scope:SCOPE_SYS2852; GFX1250-GISEL-NEXT:    s_wait_loadcnt 0x02853; GFX1250-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x400, v22854; GFX1250-GISEL-NEXT:    s_cbranch_vccz .LBB117_12855; GFX1250-GISEL-NEXT:  ; %bb.2: ; %bb22856; GFX1250-GISEL-NEXT:    s_endpgm2857;2858; GFX1250-NOECC-LABEL: flat_addr_64bit_lsr_iv_multiload:2859; GFX1250-NOECC:       ; %bb.0: ; %bb2860; GFX1250-NOECC-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12861; GFX1250-NOECC-NEXT:    v_mov_b32_e32 v0, 02862; GFX1250-NOECC-NEXT:    s_mov_b64 s[0:1], 02863; GFX1250-NOECC-NEXT:  .LBB117_1: ; %bb32864; GFX1250-NOECC-NEXT:    ; =>This Inner Loop Header: Depth=12865; GFX1250-NOECC-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2866; GFX1250-NOECC-NEXT:    s_add_nc_u64 s[4:5], s[2:3], s[0:1]2867; GFX1250-NOECC-NEXT:    s_add_nc_u64 s[0:1], s[0:1], 42868; GFX1250-NOECC-NEXT:    s_wait_dscnt 0x02869; GFX1250-NOECC-NEXT:    flat_load_b32 v1, v0, s[4:5] scope:SCOPE_SYS2870; GFX1250-NOECC-NEXT:    s_wait_loadcnt_dscnt 0x02871; GFX1250-NOECC-NEXT:    flat_load_b32 v1, v0, s[4:5] scope:SCOPE_SYS2872; GFX1250-NOECC-NEXT:    s_wait_loadcnt 0x02873; GFX1250-NOECC-NEXT:    s_cmp_eq_u32 s0, 0x4002874; GFX1250-NOECC-NEXT:    ; kill: killed $sgpr4_sgpr52875; GFX1250-NOECC-NEXT:    s_cbranch_scc0 .LBB117_12876; GFX1250-NOECC-NEXT:  ; %bb.2: ; %bb22877; GFX1250-NOECC-NEXT:    s_endpgm2878bb:2879  br label %bb32880 2881bb2:                                              ; preds = %bb32882  ret void2883 2884bb3:                                              ; preds = %bb3, %bb2885  %i = phi i32 [ 0, %bb ], [ %i8, %bb3 ]2886  %i4 = zext i32 %i to i642887  %i5 = getelementptr inbounds float, ptr %arg, i64 %i42888  %i6 = load volatile float, ptr %i5, align 42889  %i5.1 = getelementptr inbounds float, ptr %arg.1, i64 %i42890  %i6.1 = load volatile float, ptr %i5, align 42891  %i8 = add nuw nsw i32 %i, 12892  %i9 = icmp eq i32 %i8, 2562893  br i1 %i9, label %bb2, label %bb32894}2895 2896!0 = !{i32 0, i32 1073741824} ; (1 << 30)2897!1 = !{i32 0, i32 1073741825} ; (1 << 30) + 12898