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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-NOFMA,TAHITI %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-NOFMA,VERDE %s4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-FMA %s5; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-NOFMA %s6; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FMA %s7 8; Note: The SI-FMA conversions of type x * (y + 1) --> x * y + x would be9; beneficial even without fp32 denormals, but they do require no-infs-fp-math10; for correctness.11 12declare i32 @llvm.amdgcn.workitem.id.x() #013declare double @llvm.fabs.f64(double) #014declare double @llvm.fma.f64(double, double, double) #015declare float @llvm.fma.f32(float, float, float) #016declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #017 18; (fadd (fmul x, y), z) -> (fma x, y, z)19define amdgpu_kernel void @combine_to_fma_f64_0(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {20; SI-LABEL: combine_to_fma_f64_0:21; SI: ; %bb.0:22; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x923; SI-NEXT: s_mov_b32 s7, 0xf00024; SI-NEXT: s_mov_b32 s6, 025; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v026; SI-NEXT: v_mov_b32_e32 v1, 027; SI-NEXT: s_waitcnt lgkmcnt(0)28; SI-NEXT: s_mov_b64 s[4:5], s[2:3]29; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc30; SI-NEXT: s_waitcnt vmcnt(0)31; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc32; SI-NEXT: s_waitcnt vmcnt(0)33; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc34; SI-NEXT: s_waitcnt vmcnt(0)35; SI-NEXT: s_mov_b64 s[2:3], s[6:7]36; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]37; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr6438; SI-NEXT: s_endpgm39;40; GFX11-LABEL: combine_to_fma_f64_0:41; GFX11: ; %bb.0:42; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2443; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v044; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)45; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v046; GFX11-NEXT: s_waitcnt lgkmcnt(0)47; GFX11-NEXT: global_load_b64 v[0:1], v6, s[2:3] glc dlc48; GFX11-NEXT: s_waitcnt vmcnt(0)49; GFX11-NEXT: global_load_b64 v[2:3], v6, s[2:3] offset:8 glc dlc50; GFX11-NEXT: s_waitcnt vmcnt(0)51; GFX11-NEXT: global_load_b64 v[4:5], v6, s[2:3] offset:16 glc dlc52; GFX11-NEXT: s_waitcnt vmcnt(0)53; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]54; GFX11-NEXT: global_store_b64 v6, v[0:1], s[0:1]55; GFX11-NEXT: s_endpgm56 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #057 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid58 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 159 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 260 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid61 62 %a = load volatile double, ptr addrspace(1) %gep.063 %b = load volatile double, ptr addrspace(1) %gep.164 %c = load volatile double, ptr addrspace(1) %gep.265 66 %mul = fmul contract double %a, %b67 %fma = fadd contract double %mul, %c68 store double %fma, ptr addrspace(1) %gep.out69 ret void70}71 72; (fadd (fmul x, y), z) -> (fma x, y, z)73define amdgpu_kernel void @combine_to_fma_f64_0_2use(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {74; SI-LABEL: combine_to_fma_f64_0_2use:75; SI: ; %bb.0:76; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x977; SI-NEXT: s_mov_b32 s7, 0xf00078; SI-NEXT: s_mov_b32 s6, 079; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v080; SI-NEXT: v_mov_b32_e32 v1, 081; SI-NEXT: s_waitcnt lgkmcnt(0)82; SI-NEXT: s_mov_b64 s[4:5], s[2:3]83; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc84; SI-NEXT: s_waitcnt vmcnt(0)85; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc86; SI-NEXT: s_waitcnt vmcnt(0)87; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc88; SI-NEXT: s_waitcnt vmcnt(0)89; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc90; SI-NEXT: s_waitcnt vmcnt(0)91; SI-NEXT: s_mov_b64 s[2:3], s[6:7]92; SI-NEXT: v_fma_f64 v[6:7], v[2:3], v[4:5], v[6:7]93; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[8:9]94; SI-NEXT: buffer_store_dwordx2 v[6:7], v[0:1], s[0:3], 0 addr6495; SI-NEXT: s_waitcnt vmcnt(0)96; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 offset:897; SI-NEXT: s_waitcnt vmcnt(0)98; SI-NEXT: s_endpgm99;100; GFX11-LABEL: combine_to_fma_f64_0_2use:101; GFX11: ; %bb.0:102; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24103; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0104; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)105; GFX11-NEXT: v_lshlrev_b32_e32 v8, 3, v0106; GFX11-NEXT: s_waitcnt lgkmcnt(0)107; GFX11-NEXT: global_load_b64 v[0:1], v8, s[2:3] glc dlc108; GFX11-NEXT: s_waitcnt vmcnt(0)109; GFX11-NEXT: global_load_b64 v[2:3], v8, s[2:3] offset:8 glc dlc110; GFX11-NEXT: s_waitcnt vmcnt(0)111; GFX11-NEXT: global_load_b64 v[4:5], v8, s[2:3] offset:16 glc dlc112; GFX11-NEXT: s_waitcnt vmcnt(0)113; GFX11-NEXT: global_load_b64 v[6:7], v8, s[2:3] offset:24 glc dlc114; GFX11-NEXT: s_waitcnt vmcnt(0)115; GFX11-NEXT: v_fma_f64 v[4:5], v[0:1], v[2:3], v[4:5]116; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[6:7]117; GFX11-NEXT: global_store_b64 v8, v[4:5], s[0:1] dlc118; GFX11-NEXT: s_waitcnt_vscnt null, 0x0119; GFX11-NEXT: global_store_b64 v8, v[0:1], s[0:1] offset:8 dlc120; GFX11-NEXT: s_waitcnt_vscnt null, 0x0121; GFX11-NEXT: s_endpgm122 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0123 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid124 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1125 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2126 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3127 %gep.out.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid128 %gep.out.1 = getelementptr double, ptr addrspace(1) %gep.out.0, i32 1129 130 %a = load volatile double, ptr addrspace(1) %gep.0131 %b = load volatile double, ptr addrspace(1) %gep.1132 %c = load volatile double, ptr addrspace(1) %gep.2133 %d = load volatile double, ptr addrspace(1) %gep.3134 135 %mul = fmul contract double %a, %b136 %fma0 = fadd contract double %mul, %c137 %fma1 = fadd contract double %mul, %d138 store volatile double %fma0, ptr addrspace(1) %gep.out.0139 store volatile double %fma1, ptr addrspace(1) %gep.out.1140 ret void141}142 143; (fadd x, (fmul y, z)) -> (fma y, z, x)144define amdgpu_kernel void @combine_to_fma_f64_1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {145; SI-LABEL: combine_to_fma_f64_1:146; SI: ; %bb.0:147; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9148; SI-NEXT: s_mov_b32 s7, 0xf000149; SI-NEXT: s_mov_b32 s6, 0150; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0151; SI-NEXT: v_mov_b32_e32 v1, 0152; SI-NEXT: s_waitcnt lgkmcnt(0)153; SI-NEXT: s_mov_b64 s[4:5], s[2:3]154; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc155; SI-NEXT: s_waitcnt vmcnt(0)156; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc157; SI-NEXT: s_waitcnt vmcnt(0)158; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc159; SI-NEXT: s_waitcnt vmcnt(0)160; SI-NEXT: s_mov_b64 s[2:3], s[6:7]161; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]162; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64163; SI-NEXT: s_endpgm164;165; GFX11-LABEL: combine_to_fma_f64_1:166; GFX11: ; %bb.0:167; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24168; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0169; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)170; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v0171; GFX11-NEXT: s_waitcnt lgkmcnt(0)172; GFX11-NEXT: global_load_b64 v[0:1], v6, s[2:3] glc dlc173; GFX11-NEXT: s_waitcnt vmcnt(0)174; GFX11-NEXT: global_load_b64 v[2:3], v6, s[2:3] offset:8 glc dlc175; GFX11-NEXT: s_waitcnt vmcnt(0)176; GFX11-NEXT: global_load_b64 v[4:5], v6, s[2:3] offset:16 glc dlc177; GFX11-NEXT: s_waitcnt vmcnt(0)178; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]179; GFX11-NEXT: global_store_b64 v6, v[0:1], s[0:1]180; GFX11-NEXT: s_endpgm181 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0182 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid183 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1184 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2185 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid186 187 %a = load volatile double, ptr addrspace(1) %gep.0188 %b = load volatile double, ptr addrspace(1) %gep.1189 %c = load volatile double, ptr addrspace(1) %gep.2190 191 %mul = fmul contract double %a, %b192 %fma = fadd contract double %c, %mul193 store double %fma, ptr addrspace(1) %gep.out194 ret void195}196 197; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))198define amdgpu_kernel void @combine_to_fma_fsub_0_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {199; SI-LABEL: combine_to_fma_fsub_0_f64:200; SI: ; %bb.0:201; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9202; SI-NEXT: s_mov_b32 s7, 0xf000203; SI-NEXT: s_mov_b32 s6, 0204; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0205; SI-NEXT: v_mov_b32_e32 v1, 0206; SI-NEXT: s_waitcnt lgkmcnt(0)207; SI-NEXT: s_mov_b64 s[4:5], s[2:3]208; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc209; SI-NEXT: s_waitcnt vmcnt(0)210; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc211; SI-NEXT: s_waitcnt vmcnt(0)212; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc213; SI-NEXT: s_waitcnt vmcnt(0)214; SI-NEXT: s_mov_b64 s[2:3], s[6:7]215; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -v[6:7]216; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64217; SI-NEXT: s_endpgm218;219; GFX11-LABEL: combine_to_fma_fsub_0_f64:220; GFX11: ; %bb.0:221; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24222; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0223; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)224; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v0225; GFX11-NEXT: s_waitcnt lgkmcnt(0)226; GFX11-NEXT: global_load_b64 v[0:1], v6, s[2:3] glc dlc227; GFX11-NEXT: s_waitcnt vmcnt(0)228; GFX11-NEXT: global_load_b64 v[2:3], v6, s[2:3] offset:8 glc dlc229; GFX11-NEXT: s_waitcnt vmcnt(0)230; GFX11-NEXT: global_load_b64 v[4:5], v6, s[2:3] offset:16 glc dlc231; GFX11-NEXT: s_waitcnt vmcnt(0)232; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[4:5]233; GFX11-NEXT: global_store_b64 v6, v[0:1], s[0:1]234; GFX11-NEXT: s_endpgm235 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0236 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid237 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1238 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2239 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid240 241 %a = load volatile double, ptr addrspace(1) %gep.0242 %b = load volatile double, ptr addrspace(1) %gep.1243 %c = load volatile double, ptr addrspace(1) %gep.2244 245 %mul = fmul contract double %a, %b246 %fma = fsub contract double %mul, %c247 store double %fma, ptr addrspace(1) %gep.out248 ret void249}250 251; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))252define amdgpu_kernel void @combine_to_fma_fsub_f64_0_2use(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {253; SI-LABEL: combine_to_fma_fsub_f64_0_2use:254; SI: ; %bb.0:255; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9256; SI-NEXT: s_mov_b32 s7, 0xf000257; SI-NEXT: s_mov_b32 s6, 0258; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0259; SI-NEXT: v_mov_b32_e32 v1, 0260; SI-NEXT: s_waitcnt lgkmcnt(0)261; SI-NEXT: s_mov_b64 s[4:5], s[2:3]262; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc263; SI-NEXT: s_waitcnt vmcnt(0)264; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc265; SI-NEXT: s_waitcnt vmcnt(0)266; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc267; SI-NEXT: s_waitcnt vmcnt(0)268; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc269; SI-NEXT: s_waitcnt vmcnt(0)270; SI-NEXT: s_mov_b64 s[2:3], s[6:7]271; SI-NEXT: v_fma_f64 v[6:7], v[2:3], v[4:5], -v[6:7]272; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -v[8:9]273; SI-NEXT: buffer_store_dwordx2 v[6:7], v[0:1], s[0:3], 0 addr64274; SI-NEXT: s_waitcnt vmcnt(0)275; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 offset:8276; SI-NEXT: s_waitcnt vmcnt(0)277; SI-NEXT: s_endpgm278;279; GFX11-LABEL: combine_to_fma_fsub_f64_0_2use:280; GFX11: ; %bb.0:281; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24282; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0283; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)284; GFX11-NEXT: v_lshlrev_b32_e32 v8, 3, v0285; GFX11-NEXT: s_waitcnt lgkmcnt(0)286; GFX11-NEXT: global_load_b64 v[0:1], v8, s[2:3] glc dlc287; GFX11-NEXT: s_waitcnt vmcnt(0)288; GFX11-NEXT: global_load_b64 v[2:3], v8, s[2:3] offset:8 glc dlc289; GFX11-NEXT: s_waitcnt vmcnt(0)290; GFX11-NEXT: global_load_b64 v[4:5], v8, s[2:3] offset:16 glc dlc291; GFX11-NEXT: s_waitcnt vmcnt(0)292; GFX11-NEXT: global_load_b64 v[6:7], v8, s[2:3] offset:24 glc dlc293; GFX11-NEXT: s_waitcnt vmcnt(0)294; GFX11-NEXT: v_fma_f64 v[4:5], v[0:1], v[2:3], -v[4:5]295; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[6:7]296; GFX11-NEXT: global_store_b64 v8, v[4:5], s[0:1] dlc297; GFX11-NEXT: s_waitcnt_vscnt null, 0x0298; GFX11-NEXT: global_store_b64 v8, v[0:1], s[0:1] offset:8 dlc299; GFX11-NEXT: s_waitcnt_vscnt null, 0x0300; GFX11-NEXT: s_endpgm301 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0302 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid303 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1304 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2305 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3306 %gep.out.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid307 %gep.out.1 = getelementptr double, ptr addrspace(1) %gep.out.0, i32 1308 309 %a = load volatile double, ptr addrspace(1) %gep.0310 %b = load volatile double, ptr addrspace(1) %gep.1311 %c = load volatile double, ptr addrspace(1) %gep.2312 %d = load volatile double, ptr addrspace(1) %gep.3313 314 %mul = fmul contract double %a, %b315 %fma0 = fsub contract double %mul, %c316 %fma1 = fsub contract double %mul, %d317 store volatile double %fma0, ptr addrspace(1) %gep.out.0318 store volatile double %fma1, ptr addrspace(1) %gep.out.1319 ret void320}321 322; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)323define amdgpu_kernel void @combine_to_fma_fsub_1_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {324; SI-LABEL: combine_to_fma_fsub_1_f64:325; SI: ; %bb.0:326; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9327; SI-NEXT: s_mov_b32 s7, 0xf000328; SI-NEXT: s_mov_b32 s6, 0329; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0330; SI-NEXT: v_mov_b32_e32 v1, 0331; SI-NEXT: s_waitcnt lgkmcnt(0)332; SI-NEXT: s_mov_b64 s[4:5], s[2:3]333; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc334; SI-NEXT: s_waitcnt vmcnt(0)335; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc336; SI-NEXT: s_waitcnt vmcnt(0)337; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc338; SI-NEXT: s_waitcnt vmcnt(0)339; SI-NEXT: s_mov_b64 s[2:3], s[6:7]340; SI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[4:5], v[6:7]341; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64342; SI-NEXT: s_endpgm343;344; GFX11-LABEL: combine_to_fma_fsub_1_f64:345; GFX11: ; %bb.0:346; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24347; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0348; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)349; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v0350; GFX11-NEXT: s_waitcnt lgkmcnt(0)351; GFX11-NEXT: global_load_b64 v[0:1], v6, s[2:3] glc dlc352; GFX11-NEXT: s_waitcnt vmcnt(0)353; GFX11-NEXT: global_load_b64 v[2:3], v6, s[2:3] offset:8 glc dlc354; GFX11-NEXT: s_waitcnt vmcnt(0)355; GFX11-NEXT: global_load_b64 v[4:5], v6, s[2:3] offset:16 glc dlc356; GFX11-NEXT: s_waitcnt vmcnt(0)357; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], v[4:5]358; GFX11-NEXT: global_store_b64 v6, v[0:1], s[0:1]359; GFX11-NEXT: s_endpgm360 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0361 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid362 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1363 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2364 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid365 366 %a = load volatile double, ptr addrspace(1) %gep.0367 %b = load volatile double, ptr addrspace(1) %gep.1368 %c = load volatile double, ptr addrspace(1) %gep.2369 370 %mul = fmul contract double %a, %b371 %fma = fsub contract double %c, %mul372 store double %fma, ptr addrspace(1) %gep.out373 ret void374}375 376; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)377define amdgpu_kernel void @combine_to_fma_fsub_1_f64_2use(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {378; SI-LABEL: combine_to_fma_fsub_1_f64_2use:379; SI: ; %bb.0:380; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9381; SI-NEXT: s_mov_b32 s7, 0xf000382; SI-NEXT: s_mov_b32 s6, 0383; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0384; SI-NEXT: v_mov_b32_e32 v1, 0385; SI-NEXT: s_waitcnt lgkmcnt(0)386; SI-NEXT: s_mov_b64 s[4:5], s[2:3]387; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc388; SI-NEXT: s_waitcnt vmcnt(0)389; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc390; SI-NEXT: s_waitcnt vmcnt(0)391; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc392; SI-NEXT: s_waitcnt vmcnt(0)393; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc394; SI-NEXT: s_waitcnt vmcnt(0)395; SI-NEXT: s_mov_b64 s[2:3], s[6:7]396; SI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], v[6:7]397; SI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[4:5], v[8:9]398; SI-NEXT: buffer_store_dwordx2 v[6:7], v[0:1], s[0:3], 0 addr64399; SI-NEXT: s_waitcnt vmcnt(0)400; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 offset:8401; SI-NEXT: s_waitcnt vmcnt(0)402; SI-NEXT: s_endpgm403;404; GFX11-LABEL: combine_to_fma_fsub_1_f64_2use:405; GFX11: ; %bb.0:406; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24407; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0408; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)409; GFX11-NEXT: v_lshlrev_b32_e32 v8, 3, v0410; GFX11-NEXT: s_waitcnt lgkmcnt(0)411; GFX11-NEXT: global_load_b64 v[0:1], v8, s[2:3] glc dlc412; GFX11-NEXT: s_waitcnt vmcnt(0)413; GFX11-NEXT: global_load_b64 v[2:3], v8, s[2:3] offset:8 glc dlc414; GFX11-NEXT: s_waitcnt vmcnt(0)415; GFX11-NEXT: global_load_b64 v[4:5], v8, s[2:3] offset:16 glc dlc416; GFX11-NEXT: s_waitcnt vmcnt(0)417; GFX11-NEXT: global_load_b64 v[6:7], v8, s[2:3] offset:24 glc dlc418; GFX11-NEXT: s_waitcnt vmcnt(0)419; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], v[4:5]420; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], v[6:7]421; GFX11-NEXT: global_store_b64 v8, v[4:5], s[0:1] dlc422; GFX11-NEXT: s_waitcnt_vscnt null, 0x0423; GFX11-NEXT: global_store_b64 v8, v[0:1], s[0:1] offset:8 dlc424; GFX11-NEXT: s_waitcnt_vscnt null, 0x0425; GFX11-NEXT: s_endpgm426 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0427 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid428 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1429 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2430 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3431 %gep.out.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid432 %gep.out.1 = getelementptr double, ptr addrspace(1) %gep.out.0, i32 1433 434 %a = load volatile double, ptr addrspace(1) %gep.0435 %b = load volatile double, ptr addrspace(1) %gep.1436 %c = load volatile double, ptr addrspace(1) %gep.2437 %d = load volatile double, ptr addrspace(1) %gep.3438 439 %mul = fmul contract double %a, %b440 %fma0 = fsub contract double %c, %mul441 %fma1 = fsub contract double %d, %mul442 store volatile double %fma0, ptr addrspace(1) %gep.out.0443 store volatile double %fma1, ptr addrspace(1) %gep.out.1444 ret void445}446 447; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))448define amdgpu_kernel void @combine_to_fma_fsub_2_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {449; SI-LABEL: combine_to_fma_fsub_2_f64:450; SI: ; %bb.0:451; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9452; SI-NEXT: s_mov_b32 s7, 0xf000453; SI-NEXT: s_mov_b32 s6, 0454; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0455; SI-NEXT: v_mov_b32_e32 v1, 0456; SI-NEXT: s_waitcnt lgkmcnt(0)457; SI-NEXT: s_mov_b64 s[4:5], s[2:3]458; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc459; SI-NEXT: s_waitcnt vmcnt(0)460; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc461; SI-NEXT: s_waitcnt vmcnt(0)462; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc463; SI-NEXT: s_waitcnt vmcnt(0)464; SI-NEXT: s_mov_b64 s[2:3], s[6:7]465; SI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[4:5], -v[6:7]466; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64467; SI-NEXT: s_endpgm468;469; GFX11-LABEL: combine_to_fma_fsub_2_f64:470; GFX11: ; %bb.0:471; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24472; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0473; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)474; GFX11-NEXT: v_lshlrev_b32_e32 v6, 3, v0475; GFX11-NEXT: s_waitcnt lgkmcnt(0)476; GFX11-NEXT: global_load_b64 v[0:1], v6, s[2:3] glc dlc477; GFX11-NEXT: s_waitcnt vmcnt(0)478; GFX11-NEXT: global_load_b64 v[2:3], v6, s[2:3] offset:8 glc dlc479; GFX11-NEXT: s_waitcnt vmcnt(0)480; GFX11-NEXT: global_load_b64 v[4:5], v6, s[2:3] offset:16 glc dlc481; GFX11-NEXT: s_waitcnt vmcnt(0)482; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], -v[4:5]483; GFX11-NEXT: global_store_b64 v6, v[0:1], s[0:1]484; GFX11-NEXT: s_endpgm485 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0486 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid487 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1488 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2489 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid490 491 %a = load volatile double, ptr addrspace(1) %gep.0492 %b = load volatile double, ptr addrspace(1) %gep.1493 %c = load volatile double, ptr addrspace(1) %gep.2494 495 %mul = fmul contract double %a, %b496 %mul.neg = fsub contract double -0.0, %mul497 %fma = fsub contract double %mul.neg, %c498 499 store double %fma, ptr addrspace(1) %gep.out500 ret void501}502 503; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))504define amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_neg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {505; SI-LABEL: combine_to_fma_fsub_2_f64_2uses_neg:506; SI: ; %bb.0:507; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9508; SI-NEXT: s_mov_b32 s7, 0xf000509; SI-NEXT: s_mov_b32 s6, 0510; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0511; SI-NEXT: v_mov_b32_e32 v1, 0512; SI-NEXT: s_waitcnt lgkmcnt(0)513; SI-NEXT: s_mov_b64 s[4:5], s[2:3]514; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc515; SI-NEXT: s_waitcnt vmcnt(0)516; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc517; SI-NEXT: s_waitcnt vmcnt(0)518; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc519; SI-NEXT: s_waitcnt vmcnt(0)520; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc521; SI-NEXT: s_waitcnt vmcnt(0)522; SI-NEXT: s_mov_b64 s[2:3], s[6:7]523; SI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], -v[6:7]524; SI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[4:5], -v[8:9]525; SI-NEXT: buffer_store_dwordx2 v[6:7], v[0:1], s[0:3], 0 addr64526; SI-NEXT: s_waitcnt vmcnt(0)527; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 offset:8528; SI-NEXT: s_waitcnt vmcnt(0)529; SI-NEXT: s_endpgm530;531; GFX11-LABEL: combine_to_fma_fsub_2_f64_2uses_neg:532; GFX11: ; %bb.0:533; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24534; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0535; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)536; GFX11-NEXT: v_lshlrev_b32_e32 v8, 3, v0537; GFX11-NEXT: s_waitcnt lgkmcnt(0)538; GFX11-NEXT: global_load_b64 v[0:1], v8, s[2:3] glc dlc539; GFX11-NEXT: s_waitcnt vmcnt(0)540; GFX11-NEXT: global_load_b64 v[2:3], v8, s[2:3] offset:8 glc dlc541; GFX11-NEXT: s_waitcnt vmcnt(0)542; GFX11-NEXT: global_load_b64 v[4:5], v8, s[2:3] offset:16 glc dlc543; GFX11-NEXT: s_waitcnt vmcnt(0)544; GFX11-NEXT: global_load_b64 v[6:7], v8, s[2:3] offset:24 glc dlc545; GFX11-NEXT: s_waitcnt vmcnt(0)546; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], -v[4:5]547; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], -v[6:7]548; GFX11-NEXT: global_store_b64 v8, v[4:5], s[0:1] dlc549; GFX11-NEXT: s_waitcnt_vscnt null, 0x0550; GFX11-NEXT: global_store_b64 v8, v[0:1], s[0:1] offset:8 dlc551; GFX11-NEXT: s_waitcnt_vscnt null, 0x0552; GFX11-NEXT: s_endpgm553 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0554 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid555 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1556 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2557 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3558 %gep.out.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid559 %gep.out.1 = getelementptr double, ptr addrspace(1) %gep.out.0, i32 1560 561 %a = load volatile double, ptr addrspace(1) %gep.0562 %b = load volatile double, ptr addrspace(1) %gep.1563 %c = load volatile double, ptr addrspace(1) %gep.2564 %d = load volatile double, ptr addrspace(1) %gep.3565 566 %mul = fmul contract double %a, %b567 %mul.neg = fsub contract double -0.0, %mul568 %fma0 = fsub contract double %mul.neg, %c569 %fma1 = fsub contract double %mul.neg, %d570 571 store volatile double %fma0, ptr addrspace(1) %gep.out.0572 store volatile double %fma1, ptr addrspace(1) %gep.out.1573 ret void574}575 576; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))577define amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_mul(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {578; SI-LABEL: combine_to_fma_fsub_2_f64_2uses_mul:579; SI: ; %bb.0:580; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9581; SI-NEXT: s_mov_b32 s7, 0xf000582; SI-NEXT: s_mov_b32 s6, 0583; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0584; SI-NEXT: v_mov_b32_e32 v1, 0585; SI-NEXT: s_waitcnt lgkmcnt(0)586; SI-NEXT: s_mov_b64 s[4:5], s[2:3]587; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc588; SI-NEXT: s_waitcnt vmcnt(0)589; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc590; SI-NEXT: s_waitcnt vmcnt(0)591; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc592; SI-NEXT: s_waitcnt vmcnt(0)593; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc594; SI-NEXT: s_waitcnt vmcnt(0)595; SI-NEXT: s_mov_b64 s[2:3], s[6:7]596; SI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], -v[6:7]597; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -v[8:9]598; SI-NEXT: buffer_store_dwordx2 v[6:7], v[0:1], s[0:3], 0 addr64599; SI-NEXT: s_waitcnt vmcnt(0)600; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 offset:8601; SI-NEXT: s_waitcnt vmcnt(0)602; SI-NEXT: s_endpgm603;604; GFX11-LABEL: combine_to_fma_fsub_2_f64_2uses_mul:605; GFX11: ; %bb.0:606; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24607; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0608; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)609; GFX11-NEXT: v_lshlrev_b32_e32 v8, 3, v0610; GFX11-NEXT: s_waitcnt lgkmcnt(0)611; GFX11-NEXT: global_load_b64 v[0:1], v8, s[2:3] glc dlc612; GFX11-NEXT: s_waitcnt vmcnt(0)613; GFX11-NEXT: global_load_b64 v[2:3], v8, s[2:3] offset:8 glc dlc614; GFX11-NEXT: s_waitcnt vmcnt(0)615; GFX11-NEXT: global_load_b64 v[4:5], v8, s[2:3] offset:16 glc dlc616; GFX11-NEXT: s_waitcnt vmcnt(0)617; GFX11-NEXT: global_load_b64 v[6:7], v8, s[2:3] offset:24 glc dlc618; GFX11-NEXT: s_waitcnt vmcnt(0)619; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], -v[4:5]620; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[6:7]621; GFX11-NEXT: global_store_b64 v8, v[4:5], s[0:1] dlc622; GFX11-NEXT: s_waitcnt_vscnt null, 0x0623; GFX11-NEXT: global_store_b64 v8, v[0:1], s[0:1] offset:8 dlc624; GFX11-NEXT: s_waitcnt_vscnt null, 0x0625; GFX11-NEXT: s_endpgm626 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0627 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid628 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1629 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2630 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3631 %gep.out.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid632 %gep.out.1 = getelementptr double, ptr addrspace(1) %gep.out.0, i32 1633 634 %a = load volatile double, ptr addrspace(1) %gep.0635 %b = load volatile double, ptr addrspace(1) %gep.1636 %c = load volatile double, ptr addrspace(1) %gep.2637 %d = load volatile double, ptr addrspace(1) %gep.3638 639 %mul = fmul contract double %a, %b640 %mul.neg = fsub contract double -0.0, %mul641 %fma0 = fsub contract double %mul.neg, %c642 %fma1 = fsub contract double %mul, %d643 644 store volatile double %fma0, ptr addrspace(1) %gep.out.0645 store volatile double %fma1, ptr addrspace(1) %gep.out.1646 ret void647}648 649; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))650define amdgpu_kernel void @aggressive_combine_to_fma_fsub_0_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {651; SI-LABEL: aggressive_combine_to_fma_fsub_0_f64:652; SI: ; %bb.0:653; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9654; SI-NEXT: s_mov_b32 s7, 0xf000655; SI-NEXT: s_mov_b32 s6, 0656; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0657; SI-NEXT: v_mov_b32_e32 v1, 0658; SI-NEXT: s_waitcnt lgkmcnt(0)659; SI-NEXT: s_mov_b64 s[4:5], s[2:3]660; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc661; SI-NEXT: s_waitcnt vmcnt(0)662; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc663; SI-NEXT: s_waitcnt vmcnt(0)664; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc665; SI-NEXT: s_waitcnt vmcnt(0)666; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc667; SI-NEXT: s_waitcnt vmcnt(0)668; SI-NEXT: buffer_load_dwordx2 v[10:11], v[0:1], s[4:7], 0 addr64 offset:32 glc669; SI-NEXT: s_waitcnt vmcnt(0)670; SI-NEXT: s_mov_b64 s[2:3], s[6:7]671; SI-NEXT: v_fma_f64 v[6:7], v[8:9], v[10:11], -v[6:7]672; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]673; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64674; SI-NEXT: s_endpgm675;676; GFX11-LABEL: aggressive_combine_to_fma_fsub_0_f64:677; GFX11: ; %bb.0:678; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24679; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0680; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)681; GFX11-NEXT: v_lshlrev_b32_e32 v10, 3, v0682; GFX11-NEXT: s_waitcnt lgkmcnt(0)683; GFX11-NEXT: global_load_b64 v[0:1], v10, s[2:3] glc dlc684; GFX11-NEXT: s_waitcnt vmcnt(0)685; GFX11-NEXT: global_load_b64 v[2:3], v10, s[2:3] offset:8 glc dlc686; GFX11-NEXT: s_waitcnt vmcnt(0)687; GFX11-NEXT: global_load_b64 v[4:5], v10, s[2:3] offset:16 glc dlc688; GFX11-NEXT: s_waitcnt vmcnt(0)689; GFX11-NEXT: global_load_b64 v[6:7], v10, s[2:3] offset:24 glc dlc690; GFX11-NEXT: s_waitcnt vmcnt(0)691; GFX11-NEXT: global_load_b64 v[8:9], v10, s[2:3] offset:32 glc dlc692; GFX11-NEXT: s_waitcnt vmcnt(0)693; GFX11-NEXT: v_fma_f64 v[4:5], v[6:7], v[8:9], -v[4:5]694; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)695; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]696; GFX11-NEXT: global_store_b64 v10, v[0:1], s[0:1]697; GFX11-NEXT: s_endpgm698 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0699 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid700 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1701 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2702 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3703 %gep.4 = getelementptr double, ptr addrspace(1) %gep.0, i32 4704 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid705 706 %x = load volatile double, ptr addrspace(1) %gep.0707 %y = load volatile double, ptr addrspace(1) %gep.1708 %z = load volatile double, ptr addrspace(1) %gep.2709 %u = load volatile double, ptr addrspace(1) %gep.3710 %v = load volatile double, ptr addrspace(1) %gep.4711 712 %tmp0 = fmul contract fast double %u, %v713 %tmp1 = call contract fast double @llvm.fma.f64(double %x, double %y, double %tmp0) #0714 %tmp2 = fsub contract fast double %tmp1, %z715 716 store double %tmp2, ptr addrspace(1) %gep.out717 ret void718}719 720define amdgpu_kernel void @no_aggressive_combine_to_fma_fsub_0_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {721; SI-LABEL: no_aggressive_combine_to_fma_fsub_0_f64:722; SI: ; %bb.0:723; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9724; SI-NEXT: s_mov_b32 s7, 0xf000725; SI-NEXT: s_mov_b32 s6, 0726; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0727; SI-NEXT: v_mov_b32_e32 v1, 0728; SI-NEXT: s_waitcnt lgkmcnt(0)729; SI-NEXT: s_mov_b64 s[4:5], s[2:3]730; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc731; SI-NEXT: s_waitcnt vmcnt(0)732; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc733; SI-NEXT: s_waitcnt vmcnt(0)734; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc735; SI-NEXT: s_waitcnt vmcnt(0)736; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc737; SI-NEXT: s_waitcnt vmcnt(0)738; SI-NEXT: buffer_load_dwordx2 v[10:11], v[0:1], s[4:7], 0 addr64 offset:32 glc739; SI-NEXT: s_waitcnt vmcnt(0)740; SI-NEXT: s_mov_b64 s[2:3], s[6:7]741; SI-NEXT: v_mul_f64 v[8:9], v[8:9], v[10:11]742; SI-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[8:9]743; SI-NEXT: v_add_f64 v[2:3], v[2:3], -v[6:7]744; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64745; SI-NEXT: s_endpgm746;747; GFX11-LABEL: no_aggressive_combine_to_fma_fsub_0_f64:748; GFX11: ; %bb.0:749; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24750; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0751; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)752; GFX11-NEXT: v_lshlrev_b32_e32 v10, 3, v0753; GFX11-NEXT: s_waitcnt lgkmcnt(0)754; GFX11-NEXT: global_load_b64 v[0:1], v10, s[2:3] glc dlc755; GFX11-NEXT: s_waitcnt vmcnt(0)756; GFX11-NEXT: global_load_b64 v[2:3], v10, s[2:3] offset:8 glc dlc757; GFX11-NEXT: s_waitcnt vmcnt(0)758; GFX11-NEXT: global_load_b64 v[4:5], v10, s[2:3] offset:16 glc dlc759; GFX11-NEXT: s_waitcnt vmcnt(0)760; GFX11-NEXT: global_load_b64 v[6:7], v10, s[2:3] offset:24 glc dlc761; GFX11-NEXT: s_waitcnt vmcnt(0)762; GFX11-NEXT: global_load_b64 v[8:9], v10, s[2:3] offset:32 glc dlc763; GFX11-NEXT: s_waitcnt vmcnt(0)764; GFX11-NEXT: v_mul_f64 v[6:7], v[6:7], v[8:9]765; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)766; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[6:7]767; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], -v[4:5]768; GFX11-NEXT: global_store_b64 v10, v[0:1], s[0:1]769; GFX11-NEXT: s_endpgm770 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0771 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid772 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1773 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2774 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3775 %gep.4 = getelementptr double, ptr addrspace(1) %gep.0, i32 4776 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid777 778 %x = load volatile double, ptr addrspace(1) %gep.0779 %y = load volatile double, ptr addrspace(1) %gep.1780 %z = load volatile double, ptr addrspace(1) %gep.2781 %u = load volatile double, ptr addrspace(1) %gep.3782 %v = load volatile double, ptr addrspace(1) %gep.4783 784 %tmp0 = fmul double %u, %v785 %tmp1 = call double @llvm.fma.f64(double %x, double %y, double %tmp0) #0786 %tmp2 = fsub double %tmp1, %z787 788 store double %tmp2, ptr addrspace(1) %gep.out789 ret void790}791 792; fold (fsub x, (fma y, z, (fmul u, v)))793; -> (fma (fneg y), z, (fma (fneg u), v, x))794define amdgpu_kernel void @aggressive_combine_to_fma_fsub_1_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {795; SI-LABEL: aggressive_combine_to_fma_fsub_1_f64:796; SI: ; %bb.0:797; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9798; SI-NEXT: s_mov_b32 s7, 0xf000799; SI-NEXT: s_mov_b32 s6, 0800; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0801; SI-NEXT: v_mov_b32_e32 v1, 0802; SI-NEXT: s_waitcnt lgkmcnt(0)803; SI-NEXT: s_mov_b64 s[4:5], s[2:3]804; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc805; SI-NEXT: s_waitcnt vmcnt(0)806; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc807; SI-NEXT: s_waitcnt vmcnt(0)808; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc809; SI-NEXT: s_waitcnt vmcnt(0)810; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc811; SI-NEXT: s_waitcnt vmcnt(0)812; SI-NEXT: buffer_load_dwordx2 v[10:11], v[0:1], s[4:7], 0 addr64 offset:32 glc813; SI-NEXT: s_waitcnt vmcnt(0)814; SI-NEXT: s_mov_b64 s[2:3], s[6:7]815; SI-NEXT: v_fma_f64 v[2:3], -v[8:9], v[10:11], v[2:3]816; SI-NEXT: v_fma_f64 v[2:3], -v[4:5], v[6:7], v[2:3]817; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64818; SI-NEXT: s_endpgm819;820; GFX11-LABEL: aggressive_combine_to_fma_fsub_1_f64:821; GFX11: ; %bb.0:822; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24823; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0824; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)825; GFX11-NEXT: v_lshlrev_b32_e32 v10, 3, v0826; GFX11-NEXT: s_waitcnt lgkmcnt(0)827; GFX11-NEXT: global_load_b64 v[0:1], v10, s[2:3] glc dlc828; GFX11-NEXT: s_waitcnt vmcnt(0)829; GFX11-NEXT: global_load_b64 v[2:3], v10, s[2:3] offset:8 glc dlc830; GFX11-NEXT: s_waitcnt vmcnt(0)831; GFX11-NEXT: global_load_b64 v[4:5], v10, s[2:3] offset:16 glc dlc832; GFX11-NEXT: s_waitcnt vmcnt(0)833; GFX11-NEXT: global_load_b64 v[6:7], v10, s[2:3] offset:24 glc dlc834; GFX11-NEXT: s_waitcnt vmcnt(0)835; GFX11-NEXT: global_load_b64 v[8:9], v10, s[2:3] offset:32 glc dlc836; GFX11-NEXT: s_waitcnt vmcnt(0)837; GFX11-NEXT: v_fma_f64 v[0:1], -v[6:7], v[8:9], v[0:1]838; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)839; GFX11-NEXT: v_fma_f64 v[0:1], -v[2:3], v[4:5], v[0:1]840; GFX11-NEXT: global_store_b64 v10, v[0:1], s[0:1]841; GFX11-NEXT: s_endpgm842 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0843 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid844 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1845 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2846 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3847 %gep.4 = getelementptr double, ptr addrspace(1) %gep.0, i32 4848 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid849 850 %x = load volatile double, ptr addrspace(1) %gep.0851 %y = load volatile double, ptr addrspace(1) %gep.1852 %z = load volatile double, ptr addrspace(1) %gep.2853 %u = load volatile double, ptr addrspace(1) %gep.3854 %v = load volatile double, ptr addrspace(1) %gep.4855 856 ; nsz flag is needed since this combine may change sign of zero857 %tmp0 = fmul contract reassoc nsz double %u, %v858 %tmp1 = call contract reassoc nsz double @llvm.fma.f64(double %y, double %z, double %tmp0) #0859 %tmp2 = fsub contract reassoc nsz double %x, %tmp1860 861 store double %tmp2, ptr addrspace(1) %gep.out862 ret void863}864define amdgpu_kernel void @no_aggressive_combine_to_fma_fsub_1_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #1 {865; SI-LABEL: no_aggressive_combine_to_fma_fsub_1_f64:866; SI: ; %bb.0:867; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9868; SI-NEXT: s_mov_b32 s7, 0xf000869; SI-NEXT: s_mov_b32 s6, 0870; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0871; SI-NEXT: v_mov_b32_e32 v1, 0872; SI-NEXT: s_waitcnt lgkmcnt(0)873; SI-NEXT: s_mov_b64 s[4:5], s[2:3]874; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 glc875; SI-NEXT: s_waitcnt vmcnt(0)876; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 offset:8 glc877; SI-NEXT: s_waitcnt vmcnt(0)878; SI-NEXT: buffer_load_dwordx2 v[6:7], v[0:1], s[4:7], 0 addr64 offset:16 glc879; SI-NEXT: s_waitcnt vmcnt(0)880; SI-NEXT: buffer_load_dwordx2 v[8:9], v[0:1], s[4:7], 0 addr64 offset:24 glc881; SI-NEXT: s_waitcnt vmcnt(0)882; SI-NEXT: buffer_load_dwordx2 v[10:11], v[0:1], s[4:7], 0 addr64 offset:32 glc883; SI-NEXT: s_waitcnt vmcnt(0)884; SI-NEXT: s_mov_b64 s[2:3], s[6:7]885; SI-NEXT: v_mul_f64 v[8:9], v[8:9], v[10:11]886; SI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[8:9]887; SI-NEXT: v_add_f64 v[2:3], v[2:3], -v[4:5]888; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64889; SI-NEXT: s_endpgm890;891; GFX11-LABEL: no_aggressive_combine_to_fma_fsub_1_f64:892; GFX11: ; %bb.0:893; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24894; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0895; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)896; GFX11-NEXT: v_lshlrev_b32_e32 v10, 3, v0897; GFX11-NEXT: s_waitcnt lgkmcnt(0)898; GFX11-NEXT: global_load_b64 v[0:1], v10, s[2:3] glc dlc899; GFX11-NEXT: s_waitcnt vmcnt(0)900; GFX11-NEXT: global_load_b64 v[2:3], v10, s[2:3] offset:8 glc dlc901; GFX11-NEXT: s_waitcnt vmcnt(0)902; GFX11-NEXT: global_load_b64 v[4:5], v10, s[2:3] offset:16 glc dlc903; GFX11-NEXT: s_waitcnt vmcnt(0)904; GFX11-NEXT: global_load_b64 v[6:7], v10, s[2:3] offset:24 glc dlc905; GFX11-NEXT: s_waitcnt vmcnt(0)906; GFX11-NEXT: global_load_b64 v[8:9], v10, s[2:3] offset:32 glc dlc907; GFX11-NEXT: s_waitcnt vmcnt(0)908; GFX11-NEXT: v_mul_f64 v[6:7], v[6:7], v[8:9]909; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)910; GFX11-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]911; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]912; GFX11-NEXT: global_store_b64 v10, v[0:1], s[0:1]913; GFX11-NEXT: s_endpgm914 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0915 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid916 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1917 %gep.2 = getelementptr double, ptr addrspace(1) %gep.0, i32 2918 %gep.3 = getelementptr double, ptr addrspace(1) %gep.0, i32 3919 %gep.4 = getelementptr double, ptr addrspace(1) %gep.0, i32 4920 %gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid921 922 %x = load volatile double, ptr addrspace(1) %gep.0923 %y = load volatile double, ptr addrspace(1) %gep.1924 %z = load volatile double, ptr addrspace(1) %gep.2925 %u = load volatile double, ptr addrspace(1) %gep.3926 %v = load volatile double, ptr addrspace(1) %gep.4927 928 ; nsz flag is needed since this combine may change sign of zero929 %tmp0 = fmul nsz double %u, %v930 %tmp1 = call nsz double @llvm.fma.f64(double %y, double %z, double %tmp0) #0931 %tmp2 = fsub nsz double %x, %tmp1932 933 store double %tmp2, ptr addrspace(1) %gep.out934 ret void935}936 937;938; Patterns (+ fneg variants): mul(add(1.0,x),y), mul(sub(1.0,x),y), mul(sub(x,1.0),y)939;940 941define amdgpu_kernel void @test_f32_mul_add_x_one_y(ptr addrspace(1) %out,942; SI-LABEL: test_f32_mul_add_x_one_y:943; SI: ; %bb.0:944; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9945; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd946; SI-NEXT: s_mov_b32 s7, 0xf000947; SI-NEXT: s_mov_b32 s6, -1948; SI-NEXT: s_mov_b32 s14, s6949; SI-NEXT: s_waitcnt lgkmcnt(0)950; SI-NEXT: s_mov_b32 s12, s2951; SI-NEXT: s_mov_b32 s13, s3952; SI-NEXT: s_mov_b32 s15, s7953; SI-NEXT: s_mov_b32 s10, s6954; SI-NEXT: s_mov_b32 s11, s7955; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc956; SI-NEXT: s_waitcnt vmcnt(0)957; SI-NEXT: buffer_load_dword v1, off, s[8:11], 0 glc958; SI-NEXT: s_waitcnt vmcnt(0)959; SI-NEXT: s_mov_b32 s4, s0960; SI-NEXT: s_mov_b32 s5, s1961; SI-NEXT: v_add_f32_e32 v0, 1.0, v0962; SI-NEXT: v_mul_f32_e32 v0, v0, v1963; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0964; SI-NEXT: s_endpgm965;966; GFX11-LABEL: test_f32_mul_add_x_one_y:967; GFX11: ; %bb.0:968; GFX11-NEXT: s_clause 0x1969; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24970; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34971; GFX11-NEXT: v_mov_b32_e32 v0, 0972; GFX11-NEXT: s_waitcnt lgkmcnt(0)973; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc974; GFX11-NEXT: s_waitcnt vmcnt(0)975; GFX11-NEXT: global_load_b32 v2, v0, s[4:5] glc dlc976; GFX11-NEXT: s_waitcnt vmcnt(0)977; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1978; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)979; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2980; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]981; GFX11-NEXT: s_endpgm982 ptr addrspace(1) %in1,983 ptr addrspace(1) %in2) {984 %x = load volatile float, ptr addrspace(1) %in1985 %y = load volatile float, ptr addrspace(1) %in2986 %a = fadd contract float %x, 1.0987 %m = fmul contract float %a, %y988 store float %m, ptr addrspace(1) %out989 ret void990}991 992define amdgpu_kernel void @test_f32_mul_add_x_one_y_ninf(ptr addrspace(1) %out,993; SI-NOFMA-LABEL: test_f32_mul_add_x_one_y_ninf:994; SI-NOFMA: ; %bb.0:995; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9996; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd997; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf000998; SI-NOFMA-NEXT: s_mov_b32 s6, -1999; SI-NOFMA-NEXT: s_mov_b32 s14, s61000; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)1001; SI-NOFMA-NEXT: s_mov_b32 s12, s21002; SI-NOFMA-NEXT: s_mov_b32 s13, s31003; SI-NOFMA-NEXT: s_mov_b32 s15, s71004; SI-NOFMA-NEXT: s_mov_b32 s10, s61005; SI-NOFMA-NEXT: s_mov_b32 s11, s71006; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc1007; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1008; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 0 glc1009; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1010; SI-NOFMA-NEXT: s_mov_b32 s4, s01011; SI-NOFMA-NEXT: s_mov_b32 s5, s11012; SI-NOFMA-NEXT: v_mac_f32_e32 v1, v0, v11013; SI-NOFMA-NEXT: buffer_store_dword v1, off, s[4:7], 01014; SI-NOFMA-NEXT: s_endpgm1015;1016; SI-FMA-LABEL: test_f32_mul_add_x_one_y_ninf:1017; SI-FMA: ; %bb.0:1018; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91019; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1020; SI-FMA-NEXT: s_mov_b32 s7, 0xf0001021; SI-FMA-NEXT: s_mov_b32 s6, -11022; SI-FMA-NEXT: s_mov_b32 s14, s61023; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)1024; SI-FMA-NEXT: s_mov_b32 s12, s21025; SI-FMA-NEXT: s_mov_b32 s13, s31026; SI-FMA-NEXT: s_mov_b32 s15, s71027; SI-FMA-NEXT: s_mov_b32 s10, s61028; SI-FMA-NEXT: s_mov_b32 s11, s71029; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc1030; SI-FMA-NEXT: s_waitcnt vmcnt(0)1031; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 0 glc1032; SI-FMA-NEXT: s_waitcnt vmcnt(0)1033; SI-FMA-NEXT: s_mov_b32 s4, s01034; SI-FMA-NEXT: s_mov_b32 s5, s11035; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, v11036; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 01037; SI-FMA-NEXT: s_endpgm1038;1039; GFX11-LABEL: test_f32_mul_add_x_one_y_ninf:1040; GFX11: ; %bb.0:1041; GFX11-NEXT: s_clause 0x11042; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241043; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341044; GFX11-NEXT: v_mov_b32_e32 v0, 01045; GFX11-NEXT: s_waitcnt lgkmcnt(0)1046; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc1047; GFX11-NEXT: s_waitcnt vmcnt(0)1048; GFX11-NEXT: global_load_b32 v2, v0, s[4:5] glc dlc1049; GFX11-NEXT: s_waitcnt vmcnt(0)1050; GFX11-NEXT: v_fmac_f32_e32 v2, v1, v21051; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]1052; GFX11-NEXT: s_endpgm1053 ptr addrspace(1) %in1,1054 ptr addrspace(1) %in2) {1055 %x = load volatile float, ptr addrspace(1) %in11056 %y = load volatile float, ptr addrspace(1) %in21057 %a = fadd contract ninf float %x, 1.01058 %m = fmul contract ninf float %a, %y1059 store float %m, ptr addrspace(1) %out1060 ret void1061}1062 1063define amdgpu_kernel void @test_f32_mul_y_add_x_one(ptr addrspace(1) %out,1064; SI-LABEL: test_f32_mul_y_add_x_one:1065; SI: ; %bb.0:1066; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91067; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1068; SI-NEXT: s_mov_b32 s7, 0xf0001069; SI-NEXT: s_mov_b32 s6, -11070; SI-NEXT: s_mov_b32 s14, s61071; SI-NEXT: s_waitcnt lgkmcnt(0)1072; SI-NEXT: s_mov_b32 s12, s21073; SI-NEXT: s_mov_b32 s13, s31074; SI-NEXT: s_mov_b32 s15, s71075; SI-NEXT: s_mov_b32 s10, s61076; SI-NEXT: s_mov_b32 s11, s71077; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc1078; SI-NEXT: s_waitcnt vmcnt(0)1079; SI-NEXT: buffer_load_dword v1, off, s[8:11], 0 glc1080; SI-NEXT: s_waitcnt vmcnt(0)1081; SI-NEXT: s_mov_b32 s4, s01082; SI-NEXT: s_mov_b32 s5, s11083; SI-NEXT: v_add_f32_e32 v0, 1.0, v01084; SI-NEXT: v_mul_f32_e32 v0, v1, v01085; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01086; SI-NEXT: s_endpgm1087;1088; GFX11-LABEL: test_f32_mul_y_add_x_one:1089; GFX11: ; %bb.0:1090; GFX11-NEXT: s_clause 0x11091; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241092; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341093; GFX11-NEXT: v_mov_b32_e32 v0, 01094; GFX11-NEXT: s_waitcnt lgkmcnt(0)1095; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc1096; GFX11-NEXT: s_waitcnt vmcnt(0)1097; GFX11-NEXT: global_load_b32 v2, v0, s[4:5] glc dlc1098; GFX11-NEXT: s_waitcnt vmcnt(0)1099; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v11100; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1101; GFX11-NEXT: v_mul_f32_e32 v1, v2, v11102; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1103; GFX11-NEXT: s_endpgm1104 ptr addrspace(1) %in1,1105 ptr addrspace(1) %in2) {1106 %x = load volatile float, ptr addrspace(1) %in11107 %y = load volatile float, ptr addrspace(1) %in21108 %a = fadd contract float %x, 1.01109 %m = fmul contract float %y, %a1110 store float %m, ptr addrspace(1) %out1111 ret void1112}1113 1114define amdgpu_kernel void @test_f32_mul_y_add_x_one_ninf(ptr addrspace(1) %out,1115; SI-NOFMA-LABEL: test_f32_mul_y_add_x_one_ninf:1116; SI-NOFMA: ; %bb.0:1117; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91118; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1119; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0001120; SI-NOFMA-NEXT: s_mov_b32 s6, -11121; SI-NOFMA-NEXT: s_mov_b32 s14, s61122; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)1123; SI-NOFMA-NEXT: s_mov_b32 s12, s21124; SI-NOFMA-NEXT: s_mov_b32 s13, s31125; SI-NOFMA-NEXT: s_mov_b32 s15, s71126; SI-NOFMA-NEXT: s_mov_b32 s10, s61127; SI-NOFMA-NEXT: s_mov_b32 s11, s71128; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc1129; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1130; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 0 glc1131; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1132; SI-NOFMA-NEXT: s_mov_b32 s4, s01133; SI-NOFMA-NEXT: s_mov_b32 s5, s11134; SI-NOFMA-NEXT: v_mac_f32_e32 v1, v0, v11135; SI-NOFMA-NEXT: buffer_store_dword v1, off, s[4:7], 01136; SI-NOFMA-NEXT: s_endpgm1137;1138; SI-FMA-LABEL: test_f32_mul_y_add_x_one_ninf:1139; SI-FMA: ; %bb.0:1140; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91141; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1142; SI-FMA-NEXT: s_mov_b32 s7, 0xf0001143; SI-FMA-NEXT: s_mov_b32 s6, -11144; SI-FMA-NEXT: s_mov_b32 s14, s61145; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)1146; SI-FMA-NEXT: s_mov_b32 s12, s21147; SI-FMA-NEXT: s_mov_b32 s13, s31148; SI-FMA-NEXT: s_mov_b32 s15, s71149; SI-FMA-NEXT: s_mov_b32 s10, s61150; SI-FMA-NEXT: s_mov_b32 s11, s71151; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 0 glc1152; SI-FMA-NEXT: s_waitcnt vmcnt(0)1153; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 0 glc1154; SI-FMA-NEXT: s_waitcnt vmcnt(0)1155; SI-FMA-NEXT: s_mov_b32 s4, s01156; SI-FMA-NEXT: s_mov_b32 s5, s11157; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, v11158; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 01159; SI-FMA-NEXT: s_endpgm1160;1161; GFX11-LABEL: test_f32_mul_y_add_x_one_ninf:1162; GFX11: ; %bb.0:1163; GFX11-NEXT: s_clause 0x11164; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241165; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341166; GFX11-NEXT: v_mov_b32_e32 v0, 01167; GFX11-NEXT: s_waitcnt lgkmcnt(0)1168; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc1169; GFX11-NEXT: s_waitcnt vmcnt(0)1170; GFX11-NEXT: global_load_b32 v2, v0, s[4:5] glc dlc1171; GFX11-NEXT: s_waitcnt vmcnt(0)1172; GFX11-NEXT: v_fmac_f32_e32 v2, v1, v21173; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]1174; GFX11-NEXT: s_endpgm1175 ptr addrspace(1) %in1,1176 ptr addrspace(1) %in2) {1177 %x = load volatile float, ptr addrspace(1) %in11178 %y = load volatile float, ptr addrspace(1) %in21179 %a = fadd contract ninf float %x, 1.01180 %m = fmul contract ninf float %y, %a1181 store float %m, ptr addrspace(1) %out1182 ret void1183}1184 1185define amdgpu_kernel void @test_f32_mul_add_x_negone_y(ptr addrspace(1) %out,1186; SI-LABEL: test_f32_mul_add_x_negone_y:1187; SI: ; %bb.0:1188; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91189; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1190; SI-NEXT: s_mov_b32 s7, 0xf0001191; SI-NEXT: s_mov_b32 s6, -11192; SI-NEXT: s_mov_b32 s14, s61193; SI-NEXT: s_waitcnt lgkmcnt(0)1194; SI-NEXT: s_mov_b32 s12, s21195; SI-NEXT: s_mov_b32 s13, s31196; SI-NEXT: s_mov_b32 s15, s71197; SI-NEXT: s_mov_b32 s10, s61198; SI-NEXT: s_mov_b32 s11, s71199; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01200; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01201; SI-NEXT: s_mov_b32 s4, s01202; SI-NEXT: s_mov_b32 s5, s11203; SI-NEXT: s_waitcnt vmcnt(1)1204; SI-NEXT: v_add_f32_e32 v0, -1.0, v01205; SI-NEXT: s_waitcnt vmcnt(0)1206; SI-NEXT: v_mul_f32_e32 v0, v0, v11207; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01208; SI-NEXT: s_endpgm1209;1210; GFX11-LABEL: test_f32_mul_add_x_negone_y:1211; GFX11: ; %bb.0:1212; GFX11-NEXT: s_clause 0x11213; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241214; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341215; GFX11-NEXT: v_mov_b32_e32 v0, 01216; GFX11-NEXT: s_waitcnt lgkmcnt(0)1217; GFX11-NEXT: s_clause 0x11218; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1219; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1220; GFX11-NEXT: s_waitcnt vmcnt(1)1221; GFX11-NEXT: v_add_f32_e32 v1, -1.0, v11222; GFX11-NEXT: s_waitcnt vmcnt(0)1223; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1224; GFX11-NEXT: v_mul_f32_e32 v1, v1, v21225; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1226; GFX11-NEXT: s_endpgm1227 ptr addrspace(1) %in1,1228 ptr addrspace(1) %in2) {1229 %x = load float, ptr addrspace(1) %in11230 %y = load float, ptr addrspace(1) %in21231 %a = fadd contract float %x, -1.01232 %m = fmul contract float %a, %y1233 store float %m, ptr addrspace(1) %out1234 ret void1235}1236 1237define amdgpu_kernel void @test_f32_mul_add_x_negone_y_ninf(ptr addrspace(1) %out,1238; SI-NOFMA-LABEL: test_f32_mul_add_x_negone_y_ninf:1239; SI-NOFMA: ; %bb.0:1240; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91241; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1242; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0001243; SI-NOFMA-NEXT: s_mov_b32 s6, -11244; SI-NOFMA-NEXT: s_mov_b32 s14, s61245; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)1246; SI-NOFMA-NEXT: s_mov_b32 s12, s21247; SI-NOFMA-NEXT: s_mov_b32 s13, s31248; SI-NOFMA-NEXT: s_mov_b32 s15, s71249; SI-NOFMA-NEXT: s_mov_b32 s10, s61250; SI-NOFMA-NEXT: s_mov_b32 s11, s71251; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 01252; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 01253; SI-NOFMA-NEXT: s_mov_b32 s4, s01254; SI-NOFMA-NEXT: s_mov_b32 s5, s11255; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1256; SI-NOFMA-NEXT: v_mad_f32 v0, v0, v1, -v11257; SI-NOFMA-NEXT: buffer_store_dword v0, off, s[4:7], 01258; SI-NOFMA-NEXT: s_endpgm1259;1260; SI-FMA-LABEL: test_f32_mul_add_x_negone_y_ninf:1261; SI-FMA: ; %bb.0:1262; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91263; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1264; SI-FMA-NEXT: s_mov_b32 s7, 0xf0001265; SI-FMA-NEXT: s_mov_b32 s6, -11266; SI-FMA-NEXT: s_mov_b32 s14, s61267; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)1268; SI-FMA-NEXT: s_mov_b32 s12, s21269; SI-FMA-NEXT: s_mov_b32 s13, s31270; SI-FMA-NEXT: s_mov_b32 s15, s71271; SI-FMA-NEXT: s_mov_b32 s10, s61272; SI-FMA-NEXT: s_mov_b32 s11, s71273; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 01274; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 01275; SI-FMA-NEXT: s_mov_b32 s4, s01276; SI-FMA-NEXT: s_mov_b32 s5, s11277; SI-FMA-NEXT: s_waitcnt vmcnt(0)1278; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, -v11279; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 01280; SI-FMA-NEXT: s_endpgm1281;1282; GFX11-LABEL: test_f32_mul_add_x_negone_y_ninf:1283; GFX11: ; %bb.0:1284; GFX11-NEXT: s_clause 0x11285; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241286; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341287; GFX11-NEXT: v_mov_b32_e32 v0, 01288; GFX11-NEXT: s_waitcnt lgkmcnt(0)1289; GFX11-NEXT: s_clause 0x11290; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1291; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1292; GFX11-NEXT: s_waitcnt vmcnt(0)1293; GFX11-NEXT: v_fma_f32 v1, v1, v2, -v21294; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1295; GFX11-NEXT: s_endpgm1296 ptr addrspace(1) %in1,1297 ptr addrspace(1) %in2) {1298 %x = load float, ptr addrspace(1) %in11299 %y = load float, ptr addrspace(1) %in21300 %a = fadd contract ninf float %x, -1.01301 %m = fmul contract ninf float %a, %y1302 store float %m, ptr addrspace(1) %out1303 ret void1304}1305 1306define amdgpu_kernel void @test_f32_mul_y_add_x_negone(ptr addrspace(1) %out,1307; SI-LABEL: test_f32_mul_y_add_x_negone:1308; SI: ; %bb.0:1309; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91310; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1311; SI-NEXT: s_mov_b32 s7, 0xf0001312; SI-NEXT: s_mov_b32 s6, -11313; SI-NEXT: s_mov_b32 s14, s61314; SI-NEXT: s_waitcnt lgkmcnt(0)1315; SI-NEXT: s_mov_b32 s12, s21316; SI-NEXT: s_mov_b32 s13, s31317; SI-NEXT: s_mov_b32 s15, s71318; SI-NEXT: s_mov_b32 s10, s61319; SI-NEXT: s_mov_b32 s11, s71320; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01321; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01322; SI-NEXT: s_mov_b32 s4, s01323; SI-NEXT: s_mov_b32 s5, s11324; SI-NEXT: s_waitcnt vmcnt(1)1325; SI-NEXT: v_add_f32_e32 v0, -1.0, v01326; SI-NEXT: s_waitcnt vmcnt(0)1327; SI-NEXT: v_mul_f32_e32 v0, v1, v01328; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01329; SI-NEXT: s_endpgm1330;1331; GFX11-LABEL: test_f32_mul_y_add_x_negone:1332; GFX11: ; %bb.0:1333; GFX11-NEXT: s_clause 0x11334; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241335; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341336; GFX11-NEXT: v_mov_b32_e32 v0, 01337; GFX11-NEXT: s_waitcnt lgkmcnt(0)1338; GFX11-NEXT: s_clause 0x11339; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1340; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1341; GFX11-NEXT: s_waitcnt vmcnt(1)1342; GFX11-NEXT: v_add_f32_e32 v1, -1.0, v11343; GFX11-NEXT: s_waitcnt vmcnt(0)1344; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1345; GFX11-NEXT: v_mul_f32_e32 v1, v2, v11346; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1347; GFX11-NEXT: s_endpgm1348 ptr addrspace(1) %in1,1349 ptr addrspace(1) %in2) {1350 %x = load float, ptr addrspace(1) %in11351 %y = load float, ptr addrspace(1) %in21352 %a = fadd contract float %x, -1.01353 %m = fmul contract float %y, %a1354 store float %m, ptr addrspace(1) %out1355 ret void1356}1357 1358define amdgpu_kernel void @test_f32_mul_y_add_x_negone_ninf(ptr addrspace(1) %out,1359; SI-NOFMA-LABEL: test_f32_mul_y_add_x_negone_ninf:1360; SI-NOFMA: ; %bb.0:1361; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91362; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1363; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0001364; SI-NOFMA-NEXT: s_mov_b32 s6, -11365; SI-NOFMA-NEXT: s_mov_b32 s14, s61366; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)1367; SI-NOFMA-NEXT: s_mov_b32 s12, s21368; SI-NOFMA-NEXT: s_mov_b32 s13, s31369; SI-NOFMA-NEXT: s_mov_b32 s15, s71370; SI-NOFMA-NEXT: s_mov_b32 s10, s61371; SI-NOFMA-NEXT: s_mov_b32 s11, s71372; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 01373; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 01374; SI-NOFMA-NEXT: s_mov_b32 s4, s01375; SI-NOFMA-NEXT: s_mov_b32 s5, s11376; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1377; SI-NOFMA-NEXT: v_mad_f32 v0, v0, v1, -v11378; SI-NOFMA-NEXT: buffer_store_dword v0, off, s[4:7], 01379; SI-NOFMA-NEXT: s_endpgm1380;1381; SI-FMA-LABEL: test_f32_mul_y_add_x_negone_ninf:1382; SI-FMA: ; %bb.0:1383; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91384; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1385; SI-FMA-NEXT: s_mov_b32 s7, 0xf0001386; SI-FMA-NEXT: s_mov_b32 s6, -11387; SI-FMA-NEXT: s_mov_b32 s14, s61388; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)1389; SI-FMA-NEXT: s_mov_b32 s12, s21390; SI-FMA-NEXT: s_mov_b32 s13, s31391; SI-FMA-NEXT: s_mov_b32 s15, s71392; SI-FMA-NEXT: s_mov_b32 s10, s61393; SI-FMA-NEXT: s_mov_b32 s11, s71394; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 01395; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 01396; SI-FMA-NEXT: s_mov_b32 s4, s01397; SI-FMA-NEXT: s_mov_b32 s5, s11398; SI-FMA-NEXT: s_waitcnt vmcnt(0)1399; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, -v11400; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 01401; SI-FMA-NEXT: s_endpgm1402;1403; GFX11-LABEL: test_f32_mul_y_add_x_negone_ninf:1404; GFX11: ; %bb.0:1405; GFX11-NEXT: s_clause 0x11406; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241407; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341408; GFX11-NEXT: v_mov_b32_e32 v0, 01409; GFX11-NEXT: s_waitcnt lgkmcnt(0)1410; GFX11-NEXT: s_clause 0x11411; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1412; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1413; GFX11-NEXT: s_waitcnt vmcnt(0)1414; GFX11-NEXT: v_fma_f32 v1, v1, v2, -v21415; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1416; GFX11-NEXT: s_endpgm1417 ptr addrspace(1) %in1,1418 ptr addrspace(1) %in2) {1419 %x = load float, ptr addrspace(1) %in11420 %y = load float, ptr addrspace(1) %in21421 %a = fadd contract ninf float %x, -1.01422 %m = fmul contract ninf float %y, %a1423 store float %m, ptr addrspace(1) %out1424 ret void1425}1426 1427define amdgpu_kernel void @test_f32_mul_sub_one_x_y(ptr addrspace(1) %out,1428; SI-LABEL: test_f32_mul_sub_one_x_y:1429; SI: ; %bb.0:1430; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91431; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1432; SI-NEXT: s_mov_b32 s7, 0xf0001433; SI-NEXT: s_mov_b32 s6, -11434; SI-NEXT: s_mov_b32 s14, s61435; SI-NEXT: s_waitcnt lgkmcnt(0)1436; SI-NEXT: s_mov_b32 s12, s21437; SI-NEXT: s_mov_b32 s13, s31438; SI-NEXT: s_mov_b32 s15, s71439; SI-NEXT: s_mov_b32 s10, s61440; SI-NEXT: s_mov_b32 s11, s71441; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01442; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01443; SI-NEXT: s_mov_b32 s4, s01444; SI-NEXT: s_mov_b32 s5, s11445; SI-NEXT: s_waitcnt vmcnt(1)1446; SI-NEXT: v_sub_f32_e32 v0, 1.0, v01447; SI-NEXT: s_waitcnt vmcnt(0)1448; SI-NEXT: v_mul_f32_e32 v0, v0, v11449; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01450; SI-NEXT: s_endpgm1451;1452; GFX11-LABEL: test_f32_mul_sub_one_x_y:1453; GFX11: ; %bb.0:1454; GFX11-NEXT: s_clause 0x11455; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241456; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341457; GFX11-NEXT: v_mov_b32_e32 v0, 01458; GFX11-NEXT: s_waitcnt lgkmcnt(0)1459; GFX11-NEXT: s_clause 0x11460; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1461; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1462; GFX11-NEXT: s_waitcnt vmcnt(1)1463; GFX11-NEXT: v_sub_f32_e32 v1, 1.0, v11464; GFX11-NEXT: s_waitcnt vmcnt(0)1465; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1466; GFX11-NEXT: v_mul_f32_e32 v1, v1, v21467; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1468; GFX11-NEXT: s_endpgm1469 ptr addrspace(1) %in1,1470 ptr addrspace(1) %in2) {1471 %x = load float, ptr addrspace(1) %in11472 %y = load float, ptr addrspace(1) %in21473 %s = fsub contract float 1.0, %x1474 %m = fmul contract float %s, %y1475 store float %m, ptr addrspace(1) %out1476 ret void1477}1478 1479define amdgpu_kernel void @test_f32_mul_sub_one_x_y_ninf(ptr addrspace(1) %out,1480; SI-LABEL: test_f32_mul_sub_one_x_y_ninf:1481; SI: ; %bb.0:1482; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91483; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1484; SI-NEXT: s_mov_b32 s7, 0xf0001485; SI-NEXT: s_mov_b32 s6, -11486; SI-NEXT: s_mov_b32 s14, s61487; SI-NEXT: s_waitcnt lgkmcnt(0)1488; SI-NEXT: s_mov_b32 s12, s21489; SI-NEXT: s_mov_b32 s13, s31490; SI-NEXT: s_mov_b32 s15, s71491; SI-NEXT: s_mov_b32 s10, s61492; SI-NEXT: s_mov_b32 s11, s71493; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01494; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01495; SI-NEXT: s_mov_b32 s4, s01496; SI-NEXT: s_mov_b32 s5, s11497; SI-NEXT: s_waitcnt vmcnt(1)1498; SI-NEXT: v_sub_f32_e32 v0, 1.0, v01499; SI-NEXT: s_waitcnt vmcnt(0)1500; SI-NEXT: v_mul_f32_e32 v0, v0, v11501; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01502; SI-NEXT: s_endpgm1503;1504; GFX11-LABEL: test_f32_mul_sub_one_x_y_ninf:1505; GFX11: ; %bb.0:1506; GFX11-NEXT: s_clause 0x11507; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241508; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341509; GFX11-NEXT: v_mov_b32_e32 v0, 01510; GFX11-NEXT: s_waitcnt lgkmcnt(0)1511; GFX11-NEXT: s_clause 0x11512; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1513; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1514; GFX11-NEXT: s_waitcnt vmcnt(1)1515; GFX11-NEXT: v_sub_f32_e32 v1, 1.0, v11516; GFX11-NEXT: s_waitcnt vmcnt(0)1517; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1518; GFX11-NEXT: v_mul_f32_e32 v1, v1, v21519; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1520; GFX11-NEXT: s_endpgm1521 ptr addrspace(1) %in1,1522 ptr addrspace(1) %in2) {1523 %x = load float, ptr addrspace(1) %in11524 %y = load float, ptr addrspace(1) %in21525 %s = fsub contract ninf float 1.0, %x1526 %m = fmul contract ninf float %s, %y1527 store float %m, ptr addrspace(1) %out1528 ret void1529}1530 1531define amdgpu_kernel void @test_f32_mul_y_sub_one_x(ptr addrspace(1) %out,1532; SI-LABEL: test_f32_mul_y_sub_one_x:1533; SI: ; %bb.0:1534; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91535; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1536; SI-NEXT: s_mov_b32 s7, 0xf0001537; SI-NEXT: s_mov_b32 s6, -11538; SI-NEXT: s_mov_b32 s14, s61539; SI-NEXT: s_waitcnt lgkmcnt(0)1540; SI-NEXT: s_mov_b32 s12, s21541; SI-NEXT: s_mov_b32 s13, s31542; SI-NEXT: s_mov_b32 s15, s71543; SI-NEXT: s_mov_b32 s10, s61544; SI-NEXT: s_mov_b32 s11, s71545; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01546; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01547; SI-NEXT: s_mov_b32 s4, s01548; SI-NEXT: s_mov_b32 s5, s11549; SI-NEXT: s_waitcnt vmcnt(1)1550; SI-NEXT: v_sub_f32_e32 v0, 1.0, v01551; SI-NEXT: s_waitcnt vmcnt(0)1552; SI-NEXT: v_mul_f32_e32 v0, v1, v01553; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01554; SI-NEXT: s_endpgm1555;1556; GFX11-LABEL: test_f32_mul_y_sub_one_x:1557; GFX11: ; %bb.0:1558; GFX11-NEXT: s_clause 0x11559; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241560; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341561; GFX11-NEXT: v_mov_b32_e32 v0, 01562; GFX11-NEXT: s_waitcnt lgkmcnt(0)1563; GFX11-NEXT: s_clause 0x11564; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1565; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1566; GFX11-NEXT: s_waitcnt vmcnt(1)1567; GFX11-NEXT: v_sub_f32_e32 v1, 1.0, v11568; GFX11-NEXT: s_waitcnt vmcnt(0)1569; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1570; GFX11-NEXT: v_mul_f32_e32 v1, v2, v11571; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1572; GFX11-NEXT: s_endpgm1573 ptr addrspace(1) %in1,1574 ptr addrspace(1) %in2) {1575 %x = load float, ptr addrspace(1) %in11576 %y = load float, ptr addrspace(1) %in21577 %s = fsub contract float 1.0, %x1578 %m = fmul contract float %y, %s1579 store float %m, ptr addrspace(1) %out1580 ret void1581}1582 1583define amdgpu_kernel void @test_f32_mul_y_sub_one_x_ninf(ptr addrspace(1) %out,1584; SI-NOFMA-LABEL: test_f32_mul_y_sub_one_x_ninf:1585; SI-NOFMA: ; %bb.0:1586; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91587; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1588; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0001589; SI-NOFMA-NEXT: s_mov_b32 s6, -11590; SI-NOFMA-NEXT: s_mov_b32 s14, s61591; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)1592; SI-NOFMA-NEXT: s_mov_b32 s12, s21593; SI-NOFMA-NEXT: s_mov_b32 s13, s31594; SI-NOFMA-NEXT: s_mov_b32 s15, s71595; SI-NOFMA-NEXT: s_mov_b32 s10, s61596; SI-NOFMA-NEXT: s_mov_b32 s11, s71597; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 01598; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 01599; SI-NOFMA-NEXT: s_mov_b32 s4, s01600; SI-NOFMA-NEXT: s_mov_b32 s5, s11601; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1602; SI-NOFMA-NEXT: v_mad_f32 v0, -v0, v1, v11603; SI-NOFMA-NEXT: buffer_store_dword v0, off, s[4:7], 01604; SI-NOFMA-NEXT: s_endpgm1605;1606; SI-FMA-LABEL: test_f32_mul_y_sub_one_x_ninf:1607; SI-FMA: ; %bb.0:1608; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91609; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1610; SI-FMA-NEXT: s_mov_b32 s7, 0xf0001611; SI-FMA-NEXT: s_mov_b32 s6, -11612; SI-FMA-NEXT: s_mov_b32 s14, s61613; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)1614; SI-FMA-NEXT: s_mov_b32 s12, s21615; SI-FMA-NEXT: s_mov_b32 s13, s31616; SI-FMA-NEXT: s_mov_b32 s15, s71617; SI-FMA-NEXT: s_mov_b32 s10, s61618; SI-FMA-NEXT: s_mov_b32 s11, s71619; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 01620; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 01621; SI-FMA-NEXT: s_mov_b32 s4, s01622; SI-FMA-NEXT: s_mov_b32 s5, s11623; SI-FMA-NEXT: s_waitcnt vmcnt(0)1624; SI-FMA-NEXT: v_fma_f32 v0, -v0, v1, v11625; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 01626; SI-FMA-NEXT: s_endpgm1627;1628; GFX11-LABEL: test_f32_mul_y_sub_one_x_ninf:1629; GFX11: ; %bb.0:1630; GFX11-NEXT: s_clause 0x11631; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241632; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341633; GFX11-NEXT: v_mov_b32_e32 v0, 01634; GFX11-NEXT: s_waitcnt lgkmcnt(0)1635; GFX11-NEXT: s_clause 0x11636; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1637; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1638; GFX11-NEXT: s_waitcnt vmcnt(0)1639; GFX11-NEXT: v_fma_f32 v1, -v1, v2, v21640; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1641; GFX11-NEXT: s_endpgm1642 ptr addrspace(1) %in1,1643 ptr addrspace(1) %in2) {1644 %x = load float, ptr addrspace(1) %in11645 %y = load float, ptr addrspace(1) %in21646 %s = fsub contract ninf float 1.0, %x1647 %m = fmul contract ninf float %y, %s1648 store float %m, ptr addrspace(1) %out1649 ret void1650}1651 1652define amdgpu_kernel void @test_f32_mul_sub_negone_x_y(ptr addrspace(1) %out,1653; SI-LABEL: test_f32_mul_sub_negone_x_y:1654; SI: ; %bb.0:1655; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91656; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1657; SI-NEXT: s_mov_b32 s7, 0xf0001658; SI-NEXT: s_mov_b32 s6, -11659; SI-NEXT: s_mov_b32 s14, s61660; SI-NEXT: s_waitcnt lgkmcnt(0)1661; SI-NEXT: s_mov_b32 s12, s21662; SI-NEXT: s_mov_b32 s13, s31663; SI-NEXT: s_mov_b32 s15, s71664; SI-NEXT: s_mov_b32 s10, s61665; SI-NEXT: s_mov_b32 s11, s71666; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01667; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01668; SI-NEXT: s_mov_b32 s4, s01669; SI-NEXT: s_mov_b32 s5, s11670; SI-NEXT: s_waitcnt vmcnt(1)1671; SI-NEXT: v_sub_f32_e32 v0, -1.0, v01672; SI-NEXT: s_waitcnt vmcnt(0)1673; SI-NEXT: v_mul_f32_e32 v0, v0, v11674; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01675; SI-NEXT: s_endpgm1676;1677; GFX11-LABEL: test_f32_mul_sub_negone_x_y:1678; GFX11: ; %bb.0:1679; GFX11-NEXT: s_clause 0x11680; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241681; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341682; GFX11-NEXT: v_mov_b32_e32 v0, 01683; GFX11-NEXT: s_waitcnt lgkmcnt(0)1684; GFX11-NEXT: s_clause 0x11685; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1686; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1687; GFX11-NEXT: s_waitcnt vmcnt(1)1688; GFX11-NEXT: v_sub_f32_e32 v1, -1.0, v11689; GFX11-NEXT: s_waitcnt vmcnt(0)1690; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1691; GFX11-NEXT: v_mul_f32_e32 v1, v1, v21692; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1693; GFX11-NEXT: s_endpgm1694 ptr addrspace(1) %in1,1695 ptr addrspace(1) %in2) {1696 %x = load float, ptr addrspace(1) %in11697 %y = load float, ptr addrspace(1) %in21698 %s = fsub contract float -1.0, %x1699 %m = fmul contract float %s, %y1700 store float %m, ptr addrspace(1) %out1701 ret void1702}1703 1704define amdgpu_kernel void @test_f32_mul_sub_negone_x_y_ninf(ptr addrspace(1) %out,1705; SI-LABEL: test_f32_mul_sub_negone_x_y_ninf:1706; SI: ; %bb.0:1707; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91708; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1709; SI-NEXT: s_mov_b32 s7, 0xf0001710; SI-NEXT: s_mov_b32 s6, -11711; SI-NEXT: s_mov_b32 s14, s61712; SI-NEXT: s_waitcnt lgkmcnt(0)1713; SI-NEXT: s_mov_b32 s12, s21714; SI-NEXT: s_mov_b32 s13, s31715; SI-NEXT: s_mov_b32 s15, s71716; SI-NEXT: s_mov_b32 s10, s61717; SI-NEXT: s_mov_b32 s11, s71718; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01719; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01720; SI-NEXT: s_mov_b32 s4, s01721; SI-NEXT: s_mov_b32 s5, s11722; SI-NEXT: s_waitcnt vmcnt(1)1723; SI-NEXT: v_sub_f32_e32 v0, -1.0, v01724; SI-NEXT: s_waitcnt vmcnt(0)1725; SI-NEXT: v_mul_f32_e32 v0, v0, v11726; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01727; SI-NEXT: s_endpgm1728;1729; GFX11-LABEL: test_f32_mul_sub_negone_x_y_ninf:1730; GFX11: ; %bb.0:1731; GFX11-NEXT: s_clause 0x11732; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241733; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341734; GFX11-NEXT: v_mov_b32_e32 v0, 01735; GFX11-NEXT: s_waitcnt lgkmcnt(0)1736; GFX11-NEXT: s_clause 0x11737; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1738; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1739; GFX11-NEXT: s_waitcnt vmcnt(1)1740; GFX11-NEXT: v_sub_f32_e32 v1, -1.0, v11741; GFX11-NEXT: s_waitcnt vmcnt(0)1742; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1743; GFX11-NEXT: v_mul_f32_e32 v1, v1, v21744; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1745; GFX11-NEXT: s_endpgm1746 ptr addrspace(1) %in1,1747 ptr addrspace(1) %in2) {1748 %x = load float, ptr addrspace(1) %in11749 %y = load float, ptr addrspace(1) %in21750 %s = fsub contract ninf float -1.0, %x1751 %m = fmul contract ninf float %s, %y1752 store float %m, ptr addrspace(1) %out1753 ret void1754}1755 1756define amdgpu_kernel void @test_f32_mul_y_sub_negone_x(ptr addrspace(1) %out,1757; SI-LABEL: test_f32_mul_y_sub_negone_x:1758; SI: ; %bb.0:1759; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91760; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1761; SI-NEXT: s_mov_b32 s7, 0xf0001762; SI-NEXT: s_mov_b32 s6, -11763; SI-NEXT: s_mov_b32 s14, s61764; SI-NEXT: s_waitcnt lgkmcnt(0)1765; SI-NEXT: s_mov_b32 s12, s21766; SI-NEXT: s_mov_b32 s13, s31767; SI-NEXT: s_mov_b32 s15, s71768; SI-NEXT: s_mov_b32 s10, s61769; SI-NEXT: s_mov_b32 s11, s71770; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01771; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01772; SI-NEXT: s_mov_b32 s4, s01773; SI-NEXT: s_mov_b32 s5, s11774; SI-NEXT: s_waitcnt vmcnt(1)1775; SI-NEXT: v_sub_f32_e32 v0, -1.0, v01776; SI-NEXT: s_waitcnt vmcnt(0)1777; SI-NEXT: v_mul_f32_e32 v0, v1, v01778; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01779; SI-NEXT: s_endpgm1780;1781; GFX11-LABEL: test_f32_mul_y_sub_negone_x:1782; GFX11: ; %bb.0:1783; GFX11-NEXT: s_clause 0x11784; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241785; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341786; GFX11-NEXT: v_mov_b32_e32 v0, 01787; GFX11-NEXT: s_waitcnt lgkmcnt(0)1788; GFX11-NEXT: s_clause 0x11789; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1790; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1791; GFX11-NEXT: s_waitcnt vmcnt(1)1792; GFX11-NEXT: v_sub_f32_e32 v1, -1.0, v11793; GFX11-NEXT: s_waitcnt vmcnt(0)1794; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1795; GFX11-NEXT: v_mul_f32_e32 v1, v2, v11796; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1797; GFX11-NEXT: s_endpgm1798 ptr addrspace(1) %in1,1799 ptr addrspace(1) %in2) {1800 %x = load float, ptr addrspace(1) %in11801 %y = load float, ptr addrspace(1) %in21802 %s = fsub contract float -1.0, %x1803 %m = fmul contract float %y, %s1804 store float %m, ptr addrspace(1) %out1805 ret void1806}1807 1808define amdgpu_kernel void @test_f32_mul_y_sub_negone_x_ninf(ptr addrspace(1) %out,1809; SI-NOFMA-LABEL: test_f32_mul_y_sub_negone_x_ninf:1810; SI-NOFMA: ; %bb.0:1811; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91812; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1813; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0001814; SI-NOFMA-NEXT: s_mov_b32 s6, -11815; SI-NOFMA-NEXT: s_mov_b32 s14, s61816; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)1817; SI-NOFMA-NEXT: s_mov_b32 s12, s21818; SI-NOFMA-NEXT: s_mov_b32 s13, s31819; SI-NOFMA-NEXT: s_mov_b32 s15, s71820; SI-NOFMA-NEXT: s_mov_b32 s10, s61821; SI-NOFMA-NEXT: s_mov_b32 s11, s71822; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 01823; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 01824; SI-NOFMA-NEXT: s_mov_b32 s4, s01825; SI-NOFMA-NEXT: s_mov_b32 s5, s11826; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1827; SI-NOFMA-NEXT: v_mad_f32 v0, -v0, v1, -v11828; SI-NOFMA-NEXT: buffer_store_dword v0, off, s[4:7], 01829; SI-NOFMA-NEXT: s_endpgm1830;1831; SI-FMA-LABEL: test_f32_mul_y_sub_negone_x_ninf:1832; SI-FMA: ; %bb.0:1833; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91834; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1835; SI-FMA-NEXT: s_mov_b32 s7, 0xf0001836; SI-FMA-NEXT: s_mov_b32 s6, -11837; SI-FMA-NEXT: s_mov_b32 s14, s61838; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)1839; SI-FMA-NEXT: s_mov_b32 s12, s21840; SI-FMA-NEXT: s_mov_b32 s13, s31841; SI-FMA-NEXT: s_mov_b32 s15, s71842; SI-FMA-NEXT: s_mov_b32 s10, s61843; SI-FMA-NEXT: s_mov_b32 s11, s71844; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 01845; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 01846; SI-FMA-NEXT: s_mov_b32 s4, s01847; SI-FMA-NEXT: s_mov_b32 s5, s11848; SI-FMA-NEXT: s_waitcnt vmcnt(0)1849; SI-FMA-NEXT: v_fma_f32 v0, -v0, v1, -v11850; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 01851; SI-FMA-NEXT: s_endpgm1852;1853; GFX11-LABEL: test_f32_mul_y_sub_negone_x_ninf:1854; GFX11: ; %bb.0:1855; GFX11-NEXT: s_clause 0x11856; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241857; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341858; GFX11-NEXT: v_mov_b32_e32 v0, 01859; GFX11-NEXT: s_waitcnt lgkmcnt(0)1860; GFX11-NEXT: s_clause 0x11861; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1862; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1863; GFX11-NEXT: s_waitcnt vmcnt(0)1864; GFX11-NEXT: v_fma_f32 v1, -v1, v2, -v21865; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1866; GFX11-NEXT: s_endpgm1867 ptr addrspace(1) %in1,1868 ptr addrspace(1) %in2) {1869 %x = load float, ptr addrspace(1) %in11870 %y = load float, ptr addrspace(1) %in21871 %s = fsub contract ninf float -1.0, %x1872 %m = fmul contract ninf float %y, %s1873 store float %m, ptr addrspace(1) %out1874 ret void1875}1876 1877define amdgpu_kernel void @test_f32_mul_sub_x_one_y(ptr addrspace(1) %out,1878; SI-LABEL: test_f32_mul_sub_x_one_y:1879; SI: ; %bb.0:1880; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91881; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1882; SI-NEXT: s_mov_b32 s7, 0xf0001883; SI-NEXT: s_mov_b32 s6, -11884; SI-NEXT: s_mov_b32 s14, s61885; SI-NEXT: s_waitcnt lgkmcnt(0)1886; SI-NEXT: s_mov_b32 s12, s21887; SI-NEXT: s_mov_b32 s13, s31888; SI-NEXT: s_mov_b32 s15, s71889; SI-NEXT: s_mov_b32 s10, s61890; SI-NEXT: s_mov_b32 s11, s71891; SI-NEXT: buffer_load_dword v0, off, s[12:15], 01892; SI-NEXT: buffer_load_dword v1, off, s[8:11], 01893; SI-NEXT: s_mov_b32 s4, s01894; SI-NEXT: s_mov_b32 s5, s11895; SI-NEXT: s_waitcnt vmcnt(1)1896; SI-NEXT: v_add_f32_e32 v0, -1.0, v01897; SI-NEXT: s_waitcnt vmcnt(0)1898; SI-NEXT: v_mul_f32_e32 v0, v0, v11899; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01900; SI-NEXT: s_endpgm1901;1902; GFX11-LABEL: test_f32_mul_sub_x_one_y:1903; GFX11: ; %bb.0:1904; GFX11-NEXT: s_clause 0x11905; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241906; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341907; GFX11-NEXT: v_mov_b32_e32 v0, 01908; GFX11-NEXT: s_waitcnt lgkmcnt(0)1909; GFX11-NEXT: s_clause 0x11910; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1911; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1912; GFX11-NEXT: s_waitcnt vmcnt(1)1913; GFX11-NEXT: v_add_f32_e32 v1, -1.0, v11914; GFX11-NEXT: s_waitcnt vmcnt(0)1915; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1916; GFX11-NEXT: v_mul_f32_e32 v1, v1, v21917; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1918; GFX11-NEXT: s_endpgm1919 ptr addrspace(1) %in1,1920 ptr addrspace(1) %in2) {1921 %x = load float, ptr addrspace(1) %in11922 %y = load float, ptr addrspace(1) %in21923 %s = fsub contract float %x, 1.01924 %m = fmul contract float %s, %y1925 store float %m, ptr addrspace(1) %out1926 ret void1927}1928 1929define amdgpu_kernel void @test_f32_mul_sub_x_one_y_ninf(ptr addrspace(1) %out,1930; SI-NOFMA-LABEL: test_f32_mul_sub_x_one_y_ninf:1931; SI-NOFMA: ; %bb.0:1932; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91933; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1934; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0001935; SI-NOFMA-NEXT: s_mov_b32 s6, -11936; SI-NOFMA-NEXT: s_mov_b32 s14, s61937; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)1938; SI-NOFMA-NEXT: s_mov_b32 s12, s21939; SI-NOFMA-NEXT: s_mov_b32 s13, s31940; SI-NOFMA-NEXT: s_mov_b32 s15, s71941; SI-NOFMA-NEXT: s_mov_b32 s10, s61942; SI-NOFMA-NEXT: s_mov_b32 s11, s71943; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 01944; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 01945; SI-NOFMA-NEXT: s_mov_b32 s4, s01946; SI-NOFMA-NEXT: s_mov_b32 s5, s11947; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)1948; SI-NOFMA-NEXT: v_mad_f32 v0, v0, v1, -v11949; SI-NOFMA-NEXT: buffer_store_dword v0, off, s[4:7], 01950; SI-NOFMA-NEXT: s_endpgm1951;1952; SI-FMA-LABEL: test_f32_mul_sub_x_one_y_ninf:1953; SI-FMA: ; %bb.0:1954; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91955; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1956; SI-FMA-NEXT: s_mov_b32 s7, 0xf0001957; SI-FMA-NEXT: s_mov_b32 s6, -11958; SI-FMA-NEXT: s_mov_b32 s14, s61959; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)1960; SI-FMA-NEXT: s_mov_b32 s12, s21961; SI-FMA-NEXT: s_mov_b32 s13, s31962; SI-FMA-NEXT: s_mov_b32 s15, s71963; SI-FMA-NEXT: s_mov_b32 s10, s61964; SI-FMA-NEXT: s_mov_b32 s11, s71965; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 01966; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 01967; SI-FMA-NEXT: s_mov_b32 s4, s01968; SI-FMA-NEXT: s_mov_b32 s5, s11969; SI-FMA-NEXT: s_waitcnt vmcnt(0)1970; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, -v11971; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 01972; SI-FMA-NEXT: s_endpgm1973;1974; GFX11-LABEL: test_f32_mul_sub_x_one_y_ninf:1975; GFX11: ; %bb.0:1976; GFX11-NEXT: s_clause 0x11977; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241978; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341979; GFX11-NEXT: v_mov_b32_e32 v0, 01980; GFX11-NEXT: s_waitcnt lgkmcnt(0)1981; GFX11-NEXT: s_clause 0x11982; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1983; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1984; GFX11-NEXT: s_waitcnt vmcnt(0)1985; GFX11-NEXT: v_fma_f32 v1, v1, v2, -v21986; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1987; GFX11-NEXT: s_endpgm1988 ptr addrspace(1) %in1,1989 ptr addrspace(1) %in2) {1990 %x = load float, ptr addrspace(1) %in11991 %y = load float, ptr addrspace(1) %in21992 %s = fsub contract ninf float %x, 1.01993 %m = fmul contract ninf float %s, %y1994 store float %m, ptr addrspace(1) %out1995 ret void1996}1997 1998define amdgpu_kernel void @test_f32_mul_y_sub_x_one(ptr addrspace(1) %out,1999; SI-LABEL: test_f32_mul_y_sub_x_one:2000; SI: ; %bb.0:2001; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92002; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2003; SI-NEXT: s_mov_b32 s7, 0xf0002004; SI-NEXT: s_mov_b32 s6, -12005; SI-NEXT: s_mov_b32 s14, s62006; SI-NEXT: s_waitcnt lgkmcnt(0)2007; SI-NEXT: s_mov_b32 s12, s22008; SI-NEXT: s_mov_b32 s13, s32009; SI-NEXT: s_mov_b32 s15, s72010; SI-NEXT: s_mov_b32 s10, s62011; SI-NEXT: s_mov_b32 s11, s72012; SI-NEXT: buffer_load_dword v0, off, s[12:15], 02013; SI-NEXT: buffer_load_dword v1, off, s[8:11], 02014; SI-NEXT: s_mov_b32 s4, s02015; SI-NEXT: s_mov_b32 s5, s12016; SI-NEXT: s_waitcnt vmcnt(1)2017; SI-NEXT: v_add_f32_e32 v0, -1.0, v02018; SI-NEXT: s_waitcnt vmcnt(0)2019; SI-NEXT: v_mul_f32_e32 v0, v1, v02020; SI-NEXT: buffer_store_dword v0, off, s[4:7], 02021; SI-NEXT: s_endpgm2022;2023; GFX11-LABEL: test_f32_mul_y_sub_x_one:2024; GFX11: ; %bb.0:2025; GFX11-NEXT: s_clause 0x12026; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242027; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x342028; GFX11-NEXT: v_mov_b32_e32 v0, 02029; GFX11-NEXT: s_waitcnt lgkmcnt(0)2030; GFX11-NEXT: s_clause 0x12031; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2032; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2033; GFX11-NEXT: s_waitcnt vmcnt(1)2034; GFX11-NEXT: v_add_f32_e32 v1, -1.0, v12035; GFX11-NEXT: s_waitcnt vmcnt(0)2036; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2037; GFX11-NEXT: v_mul_f32_e32 v1, v2, v12038; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2039; GFX11-NEXT: s_endpgm2040 ptr addrspace(1) %in1,2041 ptr addrspace(1) %in2) {2042 %x = load float, ptr addrspace(1) %in12043 %y = load float, ptr addrspace(1) %in22044 %s = fsub contract float %x, 1.02045 %m = fmul contract float %y, %s2046 store float %m, ptr addrspace(1) %out2047 ret void2048}2049 2050define amdgpu_kernel void @test_f32_mul_y_sub_x_one_ninf(ptr addrspace(1) %out,2051; SI-NOFMA-LABEL: test_f32_mul_y_sub_x_one_ninf:2052; SI-NOFMA: ; %bb.0:2053; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92054; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2055; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0002056; SI-NOFMA-NEXT: s_mov_b32 s6, -12057; SI-NOFMA-NEXT: s_mov_b32 s14, s62058; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)2059; SI-NOFMA-NEXT: s_mov_b32 s12, s22060; SI-NOFMA-NEXT: s_mov_b32 s13, s32061; SI-NOFMA-NEXT: s_mov_b32 s15, s72062; SI-NOFMA-NEXT: s_mov_b32 s10, s62063; SI-NOFMA-NEXT: s_mov_b32 s11, s72064; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 02065; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 02066; SI-NOFMA-NEXT: s_mov_b32 s4, s02067; SI-NOFMA-NEXT: s_mov_b32 s5, s12068; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)2069; SI-NOFMA-NEXT: v_mad_f32 v0, v0, v1, -v12070; SI-NOFMA-NEXT: buffer_store_dword v0, off, s[4:7], 02071; SI-NOFMA-NEXT: s_endpgm2072;2073; SI-FMA-LABEL: test_f32_mul_y_sub_x_one_ninf:2074; SI-FMA: ; %bb.0:2075; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92076; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2077; SI-FMA-NEXT: s_mov_b32 s7, 0xf0002078; SI-FMA-NEXT: s_mov_b32 s6, -12079; SI-FMA-NEXT: s_mov_b32 s14, s62080; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)2081; SI-FMA-NEXT: s_mov_b32 s12, s22082; SI-FMA-NEXT: s_mov_b32 s13, s32083; SI-FMA-NEXT: s_mov_b32 s15, s72084; SI-FMA-NEXT: s_mov_b32 s10, s62085; SI-FMA-NEXT: s_mov_b32 s11, s72086; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 02087; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 02088; SI-FMA-NEXT: s_mov_b32 s4, s02089; SI-FMA-NEXT: s_mov_b32 s5, s12090; SI-FMA-NEXT: s_waitcnt vmcnt(0)2091; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, -v12092; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 02093; SI-FMA-NEXT: s_endpgm2094;2095; GFX11-LABEL: test_f32_mul_y_sub_x_one_ninf:2096; GFX11: ; %bb.0:2097; GFX11-NEXT: s_clause 0x12098; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242099; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x342100; GFX11-NEXT: v_mov_b32_e32 v0, 02101; GFX11-NEXT: s_waitcnt lgkmcnt(0)2102; GFX11-NEXT: s_clause 0x12103; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2104; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2105; GFX11-NEXT: s_waitcnt vmcnt(0)2106; GFX11-NEXT: v_fma_f32 v1, v1, v2, -v22107; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2108; GFX11-NEXT: s_endpgm2109 ptr addrspace(1) %in1,2110 ptr addrspace(1) %in2) {2111 %x = load float, ptr addrspace(1) %in12112 %y = load float, ptr addrspace(1) %in22113 %s = fsub contract ninf float %x, 1.02114 %m = fmul contract ninf float %y, %s2115 store float %m, ptr addrspace(1) %out2116 ret void2117}2118 2119define amdgpu_kernel void @test_f32_mul_sub_x_negone_y(ptr addrspace(1) %out,2120; SI-LABEL: test_f32_mul_sub_x_negone_y:2121; SI: ; %bb.0:2122; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92123; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2124; SI-NEXT: s_mov_b32 s7, 0xf0002125; SI-NEXT: s_mov_b32 s6, -12126; SI-NEXT: s_mov_b32 s14, s62127; SI-NEXT: s_waitcnt lgkmcnt(0)2128; SI-NEXT: s_mov_b32 s12, s22129; SI-NEXT: s_mov_b32 s13, s32130; SI-NEXT: s_mov_b32 s15, s72131; SI-NEXT: s_mov_b32 s10, s62132; SI-NEXT: s_mov_b32 s11, s72133; SI-NEXT: buffer_load_dword v0, off, s[12:15], 02134; SI-NEXT: buffer_load_dword v1, off, s[8:11], 02135; SI-NEXT: s_mov_b32 s4, s02136; SI-NEXT: s_mov_b32 s5, s12137; SI-NEXT: s_waitcnt vmcnt(1)2138; SI-NEXT: v_add_f32_e32 v0, 1.0, v02139; SI-NEXT: s_waitcnt vmcnt(0)2140; SI-NEXT: v_mul_f32_e32 v0, v0, v12141; SI-NEXT: buffer_store_dword v0, off, s[4:7], 02142; SI-NEXT: s_endpgm2143;2144; GFX11-LABEL: test_f32_mul_sub_x_negone_y:2145; GFX11: ; %bb.0:2146; GFX11-NEXT: s_clause 0x12147; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242148; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x342149; GFX11-NEXT: v_mov_b32_e32 v0, 02150; GFX11-NEXT: s_waitcnt lgkmcnt(0)2151; GFX11-NEXT: s_clause 0x12152; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2153; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2154; GFX11-NEXT: s_waitcnt vmcnt(1)2155; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v12156; GFX11-NEXT: s_waitcnt vmcnt(0)2157; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2158; GFX11-NEXT: v_mul_f32_e32 v1, v1, v22159; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2160; GFX11-NEXT: s_endpgm2161 ptr addrspace(1) %in1,2162 ptr addrspace(1) %in2) {2163 %x = load float, ptr addrspace(1) %in12164 %y = load float, ptr addrspace(1) %in22165 %s = fsub contract float %x, -1.02166 %m = fmul contract float %s, %y2167 store float %m, ptr addrspace(1) %out2168 ret void2169}2170 2171define amdgpu_kernel void @test_f32_mul_sub_x_negone_y_ninf(ptr addrspace(1) %out,2172; SI-NOFMA-LABEL: test_f32_mul_sub_x_negone_y_ninf:2173; SI-NOFMA: ; %bb.0:2174; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92175; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2176; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0002177; SI-NOFMA-NEXT: s_mov_b32 s6, -12178; SI-NOFMA-NEXT: s_mov_b32 s14, s62179; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)2180; SI-NOFMA-NEXT: s_mov_b32 s12, s22181; SI-NOFMA-NEXT: s_mov_b32 s13, s32182; SI-NOFMA-NEXT: s_mov_b32 s15, s72183; SI-NOFMA-NEXT: s_mov_b32 s10, s62184; SI-NOFMA-NEXT: s_mov_b32 s11, s72185; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 02186; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 02187; SI-NOFMA-NEXT: s_mov_b32 s4, s02188; SI-NOFMA-NEXT: s_mov_b32 s5, s12189; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)2190; SI-NOFMA-NEXT: v_mac_f32_e32 v1, v0, v12191; SI-NOFMA-NEXT: buffer_store_dword v1, off, s[4:7], 02192; SI-NOFMA-NEXT: s_endpgm2193;2194; SI-FMA-LABEL: test_f32_mul_sub_x_negone_y_ninf:2195; SI-FMA: ; %bb.0:2196; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92197; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2198; SI-FMA-NEXT: s_mov_b32 s7, 0xf0002199; SI-FMA-NEXT: s_mov_b32 s6, -12200; SI-FMA-NEXT: s_mov_b32 s14, s62201; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)2202; SI-FMA-NEXT: s_mov_b32 s12, s22203; SI-FMA-NEXT: s_mov_b32 s13, s32204; SI-FMA-NEXT: s_mov_b32 s15, s72205; SI-FMA-NEXT: s_mov_b32 s10, s62206; SI-FMA-NEXT: s_mov_b32 s11, s72207; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 02208; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 02209; SI-FMA-NEXT: s_mov_b32 s4, s02210; SI-FMA-NEXT: s_mov_b32 s5, s12211; SI-FMA-NEXT: s_waitcnt vmcnt(0)2212; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, v12213; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 02214; SI-FMA-NEXT: s_endpgm2215;2216; GFX11-LABEL: test_f32_mul_sub_x_negone_y_ninf:2217; GFX11: ; %bb.0:2218; GFX11-NEXT: s_clause 0x12219; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242220; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x342221; GFX11-NEXT: v_mov_b32_e32 v0, 02222; GFX11-NEXT: s_waitcnt lgkmcnt(0)2223; GFX11-NEXT: s_clause 0x12224; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2225; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2226; GFX11-NEXT: s_waitcnt vmcnt(0)2227; GFX11-NEXT: v_fmac_f32_e32 v2, v1, v22228; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]2229; GFX11-NEXT: s_endpgm2230 ptr addrspace(1) %in1,2231 ptr addrspace(1) %in2) {2232 %x = load float, ptr addrspace(1) %in12233 %y = load float, ptr addrspace(1) %in22234 %s = fsub contract ninf float %x, -1.02235 %m = fmul contract ninf float %s, %y2236 store float %m, ptr addrspace(1) %out2237 ret void2238}2239 2240define amdgpu_kernel void @test_f32_mul_y_sub_x_negone(ptr addrspace(1) %out,2241; SI-LABEL: test_f32_mul_y_sub_x_negone:2242; SI: ; %bb.0:2243; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92244; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2245; SI-NEXT: s_mov_b32 s7, 0xf0002246; SI-NEXT: s_mov_b32 s6, -12247; SI-NEXT: s_mov_b32 s14, s62248; SI-NEXT: s_waitcnt lgkmcnt(0)2249; SI-NEXT: s_mov_b32 s12, s22250; SI-NEXT: s_mov_b32 s13, s32251; SI-NEXT: s_mov_b32 s15, s72252; SI-NEXT: s_mov_b32 s10, s62253; SI-NEXT: s_mov_b32 s11, s72254; SI-NEXT: buffer_load_dword v0, off, s[12:15], 02255; SI-NEXT: buffer_load_dword v1, off, s[8:11], 02256; SI-NEXT: s_mov_b32 s4, s02257; SI-NEXT: s_mov_b32 s5, s12258; SI-NEXT: s_waitcnt vmcnt(1)2259; SI-NEXT: v_add_f32_e32 v0, 1.0, v02260; SI-NEXT: s_waitcnt vmcnt(0)2261; SI-NEXT: v_mul_f32_e32 v0, v1, v02262; SI-NEXT: buffer_store_dword v0, off, s[4:7], 02263; SI-NEXT: s_endpgm2264;2265; GFX11-LABEL: test_f32_mul_y_sub_x_negone:2266; GFX11: ; %bb.0:2267; GFX11-NEXT: s_clause 0x12268; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242269; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x342270; GFX11-NEXT: v_mov_b32_e32 v0, 02271; GFX11-NEXT: s_waitcnt lgkmcnt(0)2272; GFX11-NEXT: s_clause 0x12273; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2274; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2275; GFX11-NEXT: s_waitcnt vmcnt(1)2276; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v12277; GFX11-NEXT: s_waitcnt vmcnt(0)2278; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2279; GFX11-NEXT: v_mul_f32_e32 v1, v2, v12280; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2281; GFX11-NEXT: s_endpgm2282 ptr addrspace(1) %in1,2283 ptr addrspace(1) %in2) {2284 %x = load float, ptr addrspace(1) %in12285 %y = load float, ptr addrspace(1) %in22286 %s = fsub contract float %x, -1.02287 %m = fmul contract float %y, %s2288 store float %m, ptr addrspace(1) %out2289 ret void2290}2291 2292define amdgpu_kernel void @test_f32_mul_y_sub_x_negone_ninf(ptr addrspace(1) %out,2293; SI-NOFMA-LABEL: test_f32_mul_y_sub_x_negone_ninf:2294; SI-NOFMA: ; %bb.0:2295; SI-NOFMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92296; SI-NOFMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2297; SI-NOFMA-NEXT: s_mov_b32 s7, 0xf0002298; SI-NOFMA-NEXT: s_mov_b32 s6, -12299; SI-NOFMA-NEXT: s_mov_b32 s14, s62300; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)2301; SI-NOFMA-NEXT: s_mov_b32 s12, s22302; SI-NOFMA-NEXT: s_mov_b32 s13, s32303; SI-NOFMA-NEXT: s_mov_b32 s15, s72304; SI-NOFMA-NEXT: s_mov_b32 s10, s62305; SI-NOFMA-NEXT: s_mov_b32 s11, s72306; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[12:15], 02307; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[8:11], 02308; SI-NOFMA-NEXT: s_mov_b32 s4, s02309; SI-NOFMA-NEXT: s_mov_b32 s5, s12310; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)2311; SI-NOFMA-NEXT: v_mac_f32_e32 v1, v0, v12312; SI-NOFMA-NEXT: buffer_store_dword v1, off, s[4:7], 02313; SI-NOFMA-NEXT: s_endpgm2314;2315; SI-FMA-LABEL: test_f32_mul_y_sub_x_negone_ninf:2316; SI-FMA: ; %bb.0:2317; SI-FMA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92318; SI-FMA-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd2319; SI-FMA-NEXT: s_mov_b32 s7, 0xf0002320; SI-FMA-NEXT: s_mov_b32 s6, -12321; SI-FMA-NEXT: s_mov_b32 s14, s62322; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)2323; SI-FMA-NEXT: s_mov_b32 s12, s22324; SI-FMA-NEXT: s_mov_b32 s13, s32325; SI-FMA-NEXT: s_mov_b32 s15, s72326; SI-FMA-NEXT: s_mov_b32 s10, s62327; SI-FMA-NEXT: s_mov_b32 s11, s72328; SI-FMA-NEXT: buffer_load_dword v0, off, s[12:15], 02329; SI-FMA-NEXT: buffer_load_dword v1, off, s[8:11], 02330; SI-FMA-NEXT: s_mov_b32 s4, s02331; SI-FMA-NEXT: s_mov_b32 s5, s12332; SI-FMA-NEXT: s_waitcnt vmcnt(0)2333; SI-FMA-NEXT: v_fma_f32 v0, v0, v1, v12334; SI-FMA-NEXT: buffer_store_dword v0, off, s[4:7], 02335; SI-FMA-NEXT: s_endpgm2336;2337; GFX11-LABEL: test_f32_mul_y_sub_x_negone_ninf:2338; GFX11: ; %bb.0:2339; GFX11-NEXT: s_clause 0x12340; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242341; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x342342; GFX11-NEXT: v_mov_b32_e32 v0, 02343; GFX11-NEXT: s_waitcnt lgkmcnt(0)2344; GFX11-NEXT: s_clause 0x12345; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2346; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2347; GFX11-NEXT: s_waitcnt vmcnt(0)2348; GFX11-NEXT: v_fmac_f32_e32 v2, v1, v22349; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]2350; GFX11-NEXT: s_endpgm2351 ptr addrspace(1) %in1,2352 ptr addrspace(1) %in2) {2353 %x = load float, ptr addrspace(1) %in12354 %y = load float, ptr addrspace(1) %in22355 %s = fsub contract ninf float %x, -1.02356 %m = fmul contract ninf float %y, %s2357 store float %m, ptr addrspace(1) %out2358 ret void2359}2360 2361;2362; Interpolation Patterns: add(mul(x,t),mul(sub(1.0,t),y))2363;2364 2365define amdgpu_kernel void @test_f32_interp(ptr addrspace(1) %out,2366; SI-NOFMA-LABEL: test_f32_interp:2367; SI-NOFMA: ; %bb.0:2368; SI-NOFMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92369; SI-NOFMA-NEXT: s_mov_b32 s11, 0xf0002370; SI-NOFMA-NEXT: s_mov_b32 s10, -12371; SI-NOFMA-NEXT: s_mov_b32 s14, s102372; SI-NOFMA-NEXT: s_mov_b32 s15, s112373; SI-NOFMA-NEXT: s_waitcnt lgkmcnt(0)2374; SI-NOFMA-NEXT: s_mov_b32 s16, s42375; SI-NOFMA-NEXT: s_mov_b32 s17, s52376; SI-NOFMA-NEXT: s_mov_b32 s4, s62377; SI-NOFMA-NEXT: s_mov_b32 s5, s72378; SI-NOFMA-NEXT: s_mov_b32 s6, s102379; SI-NOFMA-NEXT: s_mov_b32 s7, s112380; SI-NOFMA-NEXT: s_mov_b32 s12, s22381; SI-NOFMA-NEXT: s_mov_b32 s13, s32382; SI-NOFMA-NEXT: s_mov_b32 s18, s102383; SI-NOFMA-NEXT: s_mov_b32 s19, s112384; SI-NOFMA-NEXT: buffer_load_dword v0, off, s[4:7], 02385; SI-NOFMA-NEXT: buffer_load_dword v1, off, s[16:19], 02386; SI-NOFMA-NEXT: buffer_load_dword v2, off, s[12:15], 02387; SI-NOFMA-NEXT: s_mov_b32 s8, s02388; SI-NOFMA-NEXT: s_mov_b32 s9, s12389; SI-NOFMA-NEXT: s_waitcnt vmcnt(2)2390; SI-NOFMA-NEXT: v_sub_f32_e32 v3, 1.0, v02391; SI-NOFMA-NEXT: s_waitcnt vmcnt(1)2392; SI-NOFMA-NEXT: v_mul_f32_e32 v1, v1, v32393; SI-NOFMA-NEXT: s_waitcnt vmcnt(0)2394; SI-NOFMA-NEXT: v_mac_f32_e32 v1, v2, v02395; SI-NOFMA-NEXT: buffer_store_dword v1, off, s[8:11], 02396; SI-NOFMA-NEXT: s_endpgm2397;2398; SI-FMA-LABEL: test_f32_interp:2399; SI-FMA: ; %bb.0:2400; SI-FMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92401; SI-FMA-NEXT: s_mov_b32 s11, 0xf0002402; SI-FMA-NEXT: s_mov_b32 s10, -12403; SI-FMA-NEXT: s_mov_b32 s14, s102404; SI-FMA-NEXT: s_mov_b32 s15, s112405; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)2406; SI-FMA-NEXT: s_mov_b32 s16, s42407; SI-FMA-NEXT: s_mov_b32 s17, s52408; SI-FMA-NEXT: s_mov_b32 s4, s62409; SI-FMA-NEXT: s_mov_b32 s5, s72410; SI-FMA-NEXT: s_mov_b32 s6, s102411; SI-FMA-NEXT: s_mov_b32 s7, s112412; SI-FMA-NEXT: s_mov_b32 s12, s22413; SI-FMA-NEXT: s_mov_b32 s13, s32414; SI-FMA-NEXT: s_mov_b32 s18, s102415; SI-FMA-NEXT: s_mov_b32 s19, s112416; SI-FMA-NEXT: buffer_load_dword v0, off, s[4:7], 02417; SI-FMA-NEXT: buffer_load_dword v1, off, s[16:19], 02418; SI-FMA-NEXT: buffer_load_dword v2, off, s[12:15], 02419; SI-FMA-NEXT: s_mov_b32 s8, s02420; SI-FMA-NEXT: s_mov_b32 s9, s12421; SI-FMA-NEXT: s_waitcnt vmcnt(2)2422; SI-FMA-NEXT: v_sub_f32_e32 v3, 1.0, v02423; SI-FMA-NEXT: s_waitcnt vmcnt(1)2424; SI-FMA-NEXT: v_mul_f32_e32 v1, v1, v32425; SI-FMA-NEXT: s_waitcnt vmcnt(0)2426; SI-FMA-NEXT: v_fma_f32 v0, v2, v0, v12427; SI-FMA-NEXT: buffer_store_dword v0, off, s[8:11], 02428; SI-FMA-NEXT: s_endpgm2429;2430; GFX11-LABEL: test_f32_interp:2431; GFX11: ; %bb.0:2432; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x242433; GFX11-NEXT: v_mov_b32_e32 v0, 02434; GFX11-NEXT: s_waitcnt lgkmcnt(0)2435; GFX11-NEXT: s_clause 0x22436; GFX11-NEXT: global_load_b32 v1, v0, s[6:7]2437; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2438; GFX11-NEXT: global_load_b32 v3, v0, s[2:3]2439; GFX11-NEXT: s_waitcnt vmcnt(2)2440; GFX11-NEXT: v_sub_f32_e32 v4, 1.0, v12441; GFX11-NEXT: s_waitcnt vmcnt(1)2442; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)2443; GFX11-NEXT: v_mul_f32_e32 v2, v2, v42444; GFX11-NEXT: s_waitcnt vmcnt(0)2445; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v12446; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]2447; GFX11-NEXT: s_endpgm2448 ptr addrspace(1) %in1,2449 ptr addrspace(1) %in2,2450 ptr addrspace(1) %in3) {2451 %x = load float, ptr addrspace(1) %in12452 %y = load float, ptr addrspace(1) %in22453 %t = load float, ptr addrspace(1) %in32454 %t1 = fsub contract float 1.0, %t2455 %tx = fmul contract float %x, %t2456 %ty = fmul contract float %y, %t12457 %r = fadd contract float %tx, %ty2458 store float %r, ptr addrspace(1) %out2459 ret void2460}2461 2462define amdgpu_kernel void @test_f64_interp(ptr addrspace(1) %out,2463; TAHITI-LABEL: test_f64_interp:2464; TAHITI: ; %bb.0:2465; TAHITI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92466; TAHITI-NEXT: s_mov_b32 s11, 0xf0002467; TAHITI-NEXT: s_mov_b32 s10, -12468; TAHITI-NEXT: s_mov_b32 s18, s102469; TAHITI-NEXT: s_mov_b32 s19, s112470; TAHITI-NEXT: s_waitcnt lgkmcnt(0)2471; TAHITI-NEXT: s_mov_b32 s16, s42472; TAHITI-NEXT: s_mov_b32 s17, s52473; TAHITI-NEXT: s_mov_b32 s4, s62474; TAHITI-NEXT: s_mov_b32 s5, s72475; TAHITI-NEXT: s_mov_b32 s6, s102476; TAHITI-NEXT: s_mov_b32 s7, s112477; TAHITI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 02478; TAHITI-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 02479; TAHITI-NEXT: s_mov_b32 s14, s102480; TAHITI-NEXT: s_mov_b32 s12, s22481; TAHITI-NEXT: s_mov_b32 s13, s32482; TAHITI-NEXT: s_mov_b32 s15, s112483; TAHITI-NEXT: buffer_load_dwordx2 v[4:5], off, s[12:15], 02484; TAHITI-NEXT: s_mov_b32 s8, s02485; TAHITI-NEXT: s_mov_b32 s9, s12486; TAHITI-NEXT: s_waitcnt vmcnt(2)2487; TAHITI-NEXT: v_add_f64 v[6:7], -v[0:1], 1.02488; TAHITI-NEXT: s_waitcnt vmcnt(1)2489; TAHITI-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7]2490; TAHITI-NEXT: s_waitcnt vmcnt(0)2491; TAHITI-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]2492; TAHITI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 02493; TAHITI-NEXT: s_endpgm2494;2495; VERDE-LABEL: test_f64_interp:2496; VERDE: ; %bb.0:2497; VERDE-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92498; VERDE-NEXT: s_mov_b32 s11, 0xf0002499; VERDE-NEXT: s_mov_b32 s10, -12500; VERDE-NEXT: s_mov_b32 s14, s102501; VERDE-NEXT: s_mov_b32 s15, s112502; VERDE-NEXT: s_waitcnt lgkmcnt(0)2503; VERDE-NEXT: s_mov_b32 s12, s62504; VERDE-NEXT: s_mov_b32 s13, s72505; VERDE-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 02506; VERDE-NEXT: s_mov_b32 s6, s102507; VERDE-NEXT: s_mov_b32 s7, s112508; VERDE-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 02509; VERDE-NEXT: s_mov_b32 s4, s22510; VERDE-NEXT: s_mov_b32 s5, s32511; VERDE-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 02512; VERDE-NEXT: s_mov_b32 s8, s02513; VERDE-NEXT: s_mov_b32 s9, s12514; VERDE-NEXT: s_waitcnt vmcnt(2)2515; VERDE-NEXT: v_add_f64 v[6:7], -v[0:1], 1.02516; VERDE-NEXT: s_waitcnt vmcnt(1)2517; VERDE-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7]2518; VERDE-NEXT: s_waitcnt vmcnt(0)2519; VERDE-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]2520; VERDE-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 02521; VERDE-NEXT: s_endpgm2522;2523; SI-FMA-LABEL: test_f64_interp:2524; SI-FMA: ; %bb.0:2525; SI-FMA-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x92526; SI-FMA-NEXT: s_mov_b32 s11, 0xf0002527; SI-FMA-NEXT: s_mov_b32 s10, -12528; SI-FMA-NEXT: s_mov_b32 s18, s102529; SI-FMA-NEXT: s_mov_b32 s19, s112530; SI-FMA-NEXT: s_waitcnt lgkmcnt(0)2531; SI-FMA-NEXT: s_mov_b32 s16, s42532; SI-FMA-NEXT: s_mov_b32 s17, s52533; SI-FMA-NEXT: s_mov_b32 s4, s62534; SI-FMA-NEXT: s_mov_b32 s5, s72535; SI-FMA-NEXT: s_mov_b32 s6, s102536; SI-FMA-NEXT: s_mov_b32 s7, s112537; SI-FMA-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 02538; SI-FMA-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 02539; SI-FMA-NEXT: s_mov_b32 s14, s102540; SI-FMA-NEXT: s_mov_b32 s12, s22541; SI-FMA-NEXT: s_mov_b32 s13, s32542; SI-FMA-NEXT: s_mov_b32 s15, s112543; SI-FMA-NEXT: buffer_load_dwordx2 v[4:5], off, s[12:15], 02544; SI-FMA-NEXT: s_mov_b32 s8, s02545; SI-FMA-NEXT: s_mov_b32 s9, s12546; SI-FMA-NEXT: s_waitcnt vmcnt(2)2547; SI-FMA-NEXT: v_add_f64 v[6:7], -v[0:1], 1.02548; SI-FMA-NEXT: s_waitcnt vmcnt(1)2549; SI-FMA-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7]2550; SI-FMA-NEXT: s_waitcnt vmcnt(0)2551; SI-FMA-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]2552; SI-FMA-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 02553; SI-FMA-NEXT: s_endpgm2554;2555; GFX11-LABEL: test_f64_interp:2556; GFX11: ; %bb.0:2557; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x242558; GFX11-NEXT: v_mov_b32_e32 v8, 02559; GFX11-NEXT: s_waitcnt lgkmcnt(0)2560; GFX11-NEXT: s_clause 0x22561; GFX11-NEXT: global_load_b64 v[0:1], v8, s[6:7]2562; GFX11-NEXT: global_load_b64 v[2:3], v8, s[4:5]2563; GFX11-NEXT: global_load_b64 v[4:5], v8, s[2:3]2564; GFX11-NEXT: s_waitcnt vmcnt(2)2565; GFX11-NEXT: v_add_f64 v[6:7], -v[0:1], 1.02566; GFX11-NEXT: s_waitcnt vmcnt(1)2567; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)2568; GFX11-NEXT: v_mul_f64 v[2:3], v[2:3], v[6:7]2569; GFX11-NEXT: s_waitcnt vmcnt(0)2570; GFX11-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], v[2:3]2571; GFX11-NEXT: global_store_b64 v8, v[0:1], s[0:1]2572; GFX11-NEXT: s_endpgm2573 ptr addrspace(1) %in1,2574 ptr addrspace(1) %in2,2575 ptr addrspace(1) %in3) {2576 %x = load double, ptr addrspace(1) %in12577 %y = load double, ptr addrspace(1) %in22578 %t = load double, ptr addrspace(1) %in32579 %t1 = fsub contract double 1.0, %t2580 %tx = fmul contract double %x, %t2581 %ty = fmul contract double %y, %t12582 %r = fadd contract double %tx, %ty2583 store double %r, ptr addrspace(1) %out2584 ret void2585}2586 2587; Make sure negative constant cancels out fneg2588define amdgpu_kernel void @fma_neg_2.0_neg_a_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {2589; SI-LABEL: fma_neg_2.0_neg_a_b_f32:2590; SI: ; %bb.0:2591; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92592; SI-NEXT: s_mov_b32 s3, 0xf0002593; SI-NEXT: s_mov_b32 s2, 02594; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v02595; SI-NEXT: v_mov_b32_e32 v1, 02596; SI-NEXT: s_waitcnt lgkmcnt(0)2597; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc2598; SI-NEXT: s_waitcnt vmcnt(0)2599; SI-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc2600; SI-NEXT: s_waitcnt vmcnt(0)2601; SI-NEXT: v_fma_f32 v2, v2, 2.0, v32602; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr642603; SI-NEXT: s_endpgm2604;2605; GFX11-LABEL: fma_neg_2.0_neg_a_b_f32:2606; GFX11: ; %bb.0:2607; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x242608; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v02609; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2610; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v02611; GFX11-NEXT: s_waitcnt lgkmcnt(0)2612; GFX11-NEXT: global_load_b32 v1, v0, s[0:1] glc dlc2613; GFX11-NEXT: s_waitcnt vmcnt(0)2614; GFX11-NEXT: global_load_b32 v2, v0, s[0:1] offset:4 glc dlc2615; GFX11-NEXT: s_waitcnt vmcnt(0)2616; GFX11-NEXT: v_fmac_f32_e32 v2, 2.0, v12617; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]2618; GFX11-NEXT: s_endpgm2619 %tid = call i32 @llvm.amdgcn.workitem.id.x()2620 %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid2621 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 12622 %gep.out = getelementptr float, ptr addrspace(1) %out, i32 %tid2623 2624 %r1 = load volatile float, ptr addrspace(1) %gep.02625 %r2 = load volatile float, ptr addrspace(1) %gep.12626 2627 %r1.fneg = fneg float %r12628 2629 %r3 = tail call float @llvm.fma.f32(float -2.0, float %r1.fneg, float %r2)2630 store float %r3, ptr addrspace(1) %gep.out2631 ret void2632}2633 2634define amdgpu_kernel void @fma_2.0_neg_a_b_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {2635; SI-LABEL: fma_2.0_neg_a_b_f32:2636; SI: ; %bb.0:2637; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x92638; SI-NEXT: s_mov_b32 s3, 0xf0002639; SI-NEXT: s_mov_b32 s2, 02640; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v02641; SI-NEXT: v_mov_b32_e32 v1, 02642; SI-NEXT: s_waitcnt lgkmcnt(0)2643; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc2644; SI-NEXT: s_waitcnt vmcnt(0)2645; SI-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4 glc2646; SI-NEXT: s_waitcnt vmcnt(0)2647; SI-NEXT: v_fma_f32 v2, v2, -2.0, v32648; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr642649; SI-NEXT: s_endpgm2650;2651; GFX11-LABEL: fma_2.0_neg_a_b_f32:2652; GFX11: ; %bb.0:2653; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x242654; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v02655; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2656; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v02657; GFX11-NEXT: s_waitcnt lgkmcnt(0)2658; GFX11-NEXT: global_load_b32 v1, v0, s[0:1] glc dlc2659; GFX11-NEXT: s_waitcnt vmcnt(0)2660; GFX11-NEXT: global_load_b32 v2, v0, s[0:1] offset:4 glc dlc2661; GFX11-NEXT: s_waitcnt vmcnt(0)2662; GFX11-NEXT: v_fmac_f32_e32 v2, -2.0, v12663; GFX11-NEXT: global_store_b32 v0, v2, s[0:1]2664; GFX11-NEXT: s_endpgm2665 %tid = call i32 @llvm.amdgcn.workitem.id.x()2666 %gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid2667 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 12668 %gep.out = getelementptr float, ptr addrspace(1) %out, i32 %tid2669 2670 %r1 = load volatile float, ptr addrspace(1) %gep.02671 %r2 = load volatile float, ptr addrspace(1) %gep.12672 2673 %r1.fneg = fneg float %r12674 2675 %r3 = tail call float @llvm.fma.f32(float 2.0, float %r1.fneg, float %r2)2676 store float %r3, ptr addrspace(1) %gep.out2677 ret void2678}2679 2680define amdgpu_kernel void @fma_neg_b_c_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #2 {2681; SI-LABEL: fma_neg_b_c_v4f32:2682; SI: ; %bb.0:2683; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x92684; SI-NEXT: s_mov_b32 s7, 0xf0002685; SI-NEXT: s_mov_b32 s6, 02686; SI-NEXT: v_lshlrev_b32_e32 v12, 4, v02687; SI-NEXT: v_mov_b32_e32 v13, 02688; SI-NEXT: s_waitcnt lgkmcnt(0)2689; SI-NEXT: s_mov_b64 s[4:5], s[2:3]2690; SI-NEXT: buffer_load_dwordx4 v[0:3], v[12:13], s[4:7], 0 addr642691; SI-NEXT: buffer_load_dwordx4 v[4:7], v[12:13], s[4:7], 0 addr64 offset:162692; SI-NEXT: buffer_load_dwordx4 v[8:11], v[12:13], s[4:7], 0 addr64 offset:482693; SI-NEXT: s_mov_b64 s[2:3], s[6:7]2694; SI-NEXT: s_waitcnt vmcnt(0)2695; SI-NEXT: v_fma_f32 v3, v11, -v3, -v72696; SI-NEXT: v_fma_f32 v2, v10, -v2, -v62697; SI-NEXT: v_fma_f32 v1, v9, -v1, -v52698; SI-NEXT: v_fma_f32 v0, v8, -v0, -v42699; SI-NEXT: buffer_store_dwordx4 v[0:3], v[12:13], s[0:3], 0 addr642700; SI-NEXT: s_endpgm2701;2702; GFX11-LABEL: fma_neg_b_c_v4f32:2703; GFX11: ; %bb.0:2704; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x242705; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v02706; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2707; GFX11-NEXT: v_lshlrev_b32_e32 v12, 4, v02708; GFX11-NEXT: s_waitcnt lgkmcnt(0)2709; GFX11-NEXT: s_clause 0x22710; GFX11-NEXT: global_load_b128 v[0:3], v12, s[2:3] offset:162711; GFX11-NEXT: global_load_b128 v[4:7], v12, s[2:3]2712; GFX11-NEXT: global_load_b128 v[8:11], v12, s[2:3] offset:482713; GFX11-NEXT: s_waitcnt vmcnt(0)2714; GFX11-NEXT: v_fma_f32 v3, v11, -v7, -v32715; GFX11-NEXT: v_fma_f32 v2, v10, -v6, -v22716; GFX11-NEXT: v_fma_f32 v1, v9, -v5, -v12717; GFX11-NEXT: v_fma_f32 v0, v8, -v4, -v02718; GFX11-NEXT: global_store_b128 v12, v[0:3], s[0:1]2719; GFX11-NEXT: s_endpgm2720 %tid = call i32 @llvm.amdgcn.workitem.id.x()2721 %gep.0 = getelementptr <4 x float>, ptr addrspace(1) %in, i32 %tid2722 %gep.1 = getelementptr <4 x float>, ptr addrspace(1) %gep.0, i32 12723 %gep.2 = getelementptr <4 x float>, ptr addrspace(1) %gep.1, i32 22724 %gep.out = getelementptr <4 x float>, ptr addrspace(1) %out, i32 %tid2725 2726 %tmp0 = load <4 x float>, ptr addrspace(1) %gep.02727 %tmp1 = load <4 x float>, ptr addrspace(1) %gep.12728 %tmp2 = load <4 x float>, ptr addrspace(1) %gep.22729 2730 %fneg0 = fneg fast <4 x float> %tmp02731 %fneg1 = fneg fast <4 x float> %tmp12732 %fma0 = tail call fast <4 x float> @llvm.fma.v4f32(<4 x float> %tmp2, <4 x float> %fneg0, <4 x float> %fneg1)2733 2734 store <4 x float> %fma0, ptr addrspace(1) %gep.out2735 ret void2736}2737 2738attributes #0 = { nounwind readnone }2739attributes #1 = { nounwind }2740attributes #2 = { nounwind "no-signed-zeros-fp-math"="true" }2741;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:2742; GFX11-FMA: {{.*}}2743; GFX11-NOFMA: {{.*}}2744