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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefix=GFX906 -check-prefix=FUNC %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s4; RUN: not llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=cedar < %s5; RUN: not llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=juniper < %s6; RUN: not llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s7; RUN: not llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=sumo < %s8; RUN: not llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=barts < %s9; RUN: not llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=caicos < %s10; RUN: not llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=turks < %s11 12declare float @llvm.fma.f32(float, float, float) nounwind readnone13declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone14declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone15 16declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone17 18; FUNC-LABEL: {{^}}fma_f32:19; SI: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}20; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}21 22; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}},23; EG: FMA {{\*? *}}[[RES]]24define amdgpu_kernel void @fma_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,25 ptr addrspace(1) %in2, ptr addrspace(1) %in3) {26 %r0 = load float, ptr addrspace(1) %in127 %r1 = load float, ptr addrspace(1) %in228 %r2 = load float, ptr addrspace(1) %in329 %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)30 store float %r3, ptr addrspace(1) %out31 ret void32}33 34; GCN-LABEL: {{^}}fmac_to_3addr_f32:35; GCN: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}36define float @fmac_to_3addr_f32(float %r0, float %r1, float %r2) {37 %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)38 ret float %r339}40 41; FUNC-LABEL: {{^}}fma_v2f32:42; SI: v_fma_f3243; SI: v_fma_f3244 45; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}46; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}47 48; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}},49; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]]50; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]51define amdgpu_kernel void @fma_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,52 ptr addrspace(1) %in2, ptr addrspace(1) %in3) {53 %r0 = load <2 x float>, ptr addrspace(1) %in154 %r1 = load <2 x float>, ptr addrspace(1) %in255 %r2 = load <2 x float>, ptr addrspace(1) %in356 %r3 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %r0, <2 x float> %r1, <2 x float> %r2)57 store <2 x float> %r3, ptr addrspace(1) %out58 ret void59}60 61; FUNC-LABEL: {{^}}fma_v4f32:62; SI: v_fma_f3263; SI: v_fma_f3264; SI: v_fma_f3265; SI: v_fma_f3266; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}67; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}68; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}69; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+$}}70 71; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}},72; EG-DAG: FMA {{\*? *}}[[RES]].X73; EG-DAG: FMA {{\*? *}}[[RES]].Y74; EG-DAG: FMA {{\*? *}}[[RES]].Z75; EG-DAG: FMA {{\*? *}}[[RES]].W76define amdgpu_kernel void @fma_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,77 ptr addrspace(1) %in2, ptr addrspace(1) %in3) {78 %r0 = load <4 x float>, ptr addrspace(1) %in179 %r1 = load <4 x float>, ptr addrspace(1) %in280 %r2 = load <4 x float>, ptr addrspace(1) %in381 %r3 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %r0, <4 x float> %r1, <4 x float> %r2)82 store <4 x float> %r3, ptr addrspace(1) %out83 ret void84}85 86; FUNC-LABEL: @fma_commute_mul_inline_imm_f3287; SI: v_fma_f32 {{v[0-9]+}}, {{v[0-9]+}}, 2.0, {{v[0-9]+}}88define amdgpu_kernel void @fma_commute_mul_inline_imm_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in.a, ptr addrspace(1) noalias %in.b) nounwind {89 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone90 %in.a.gep = getelementptr float, ptr addrspace(1) %in.a, i32 %tid91 %in.b.gep = getelementptr float, ptr addrspace(1) %in.b, i32 %tid92 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid93 94 %a = load float, ptr addrspace(1) %in.a.gep, align 495 %b = load float, ptr addrspace(1) %in.b.gep, align 496 97 %fma = call float @llvm.fma.f32(float %a, float 2.0, float %b)98 store float %fma, ptr addrspace(1) %out.gep, align 499 ret void100}101 102; FUNC-LABEL: @fma_commute_mul_s_f32103define amdgpu_kernel void @fma_commute_mul_s_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in.a, ptr addrspace(1) noalias %in.b, float %b) nounwind {104 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone105 %in.a.gep = getelementptr float, ptr addrspace(1) %in.a, i32 %tid106 %in.b.gep = getelementptr float, ptr addrspace(1) %in.b, i32 %tid107 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid108 109 %a = load float, ptr addrspace(1) %in.a.gep, align 4110 %c = load float, ptr addrspace(1) %in.b.gep, align 4111 112 %fma = call float @llvm.fma.f32(float %a, float %b, float %c)113 store float %fma, ptr addrspace(1) %out.gep, align 4114 ret void115}116 117; Without special casing the inline constant check for v_fmac_f32's118; src2, this fails to fold the 1.0 into an fma.119 120; FUNC-LABEL: {{^}}fold_inline_imm_into_fmac_src2_f32:121; GFX906: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]122; GFX906: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]123 124; GFX906: v_add_f32_e32 [[TMP2:v[0-9]+]], [[A]], [[A]]125; GFX906: v_fma_f32 v{{[0-9]+}}, [[TMP2]], -4.0, 1.0126define amdgpu_kernel void @fold_inline_imm_into_fmac_src2_f32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) nounwind {127bb:128 %tid = call i32 @llvm.amdgcn.workitem.id.x()129 %tid.ext = sext i32 %tid to i64130 %gep.a = getelementptr inbounds float, ptr addrspace(1) %a, i64 %tid.ext131 %gep.b = getelementptr inbounds float, ptr addrspace(1) %b, i64 %tid.ext132 %gep.out = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext133 %tmp = load volatile float, ptr addrspace(1) %gep.a134 %tmp1 = load volatile float, ptr addrspace(1) %gep.b135 %tmp2 = fadd contract float %tmp, %tmp136 %tmp3 = fmul contract float %tmp2, 4.0137 %tmp4 = fsub contract float 1.0, %tmp3138 %tmp5 = fadd contract float %tmp4, %tmp1139 %tmp6 = fadd contract float %tmp1, %tmp1140 %tmp7 = fmul contract float %tmp6, %tmp141 %tmp8 = fsub contract float 1.0, %tmp7142 %tmp9 = fmul contract float %tmp8, 8.0143 %tmp10 = fadd contract float %tmp5, %tmp9144 store float %tmp10, ptr addrspace(1) %gep.out145 ret void146}147 148; Fold (fmul (fadd x, 1.0), y) -> (fma x, y, y) without FP specific command-line149; options.150; FUNC-LABEL: {{^}}fold_fmul_distributive:151; GFX906: v_fmac_f32_e32 v0, v1, v0152define float @fold_fmul_distributive(float %x, float %y) {153 %fadd = fadd ninf float %y, 1.0154 %fmul = fmul contract float %fadd, %x155 ret float %fmul156}157 158; test to make sure contract is not dropped such that we can generate fma from following mul/add159define amdgpu_kernel void @vec_mul_scalar_add_fma(<2 x float> %a, <2 x float> %b, float %c1, ptr addrspace(1) %inptr) {160; GFX906-LABEL: vec_mul_scalar_add_fma:161; GFX906: ; %bb.0:162; GFX906-NEXT: s_load_dword s8, s[4:5], 0x34163; GFX906-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24164; GFX906-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x3c165; GFX906-NEXT: v_mov_b32_e32 v0, 0166; GFX906-NEXT: s_waitcnt lgkmcnt(0)167; GFX906-NEXT: v_mov_b32_e32 v1, s8168; GFX906-NEXT: v_mov_b32_e32 v2, s2169; GFX906-NEXT: v_fmac_f32_e32 v1, s0, v2170; GFX906-NEXT: global_store_dword v0, v1, s[6:7] offset:4171; GFX906-NEXT: s_endpgm172 %gep = getelementptr float, ptr addrspace(1) %inptr, i32 1173 %c = shufflevector <2 x float> %a, <2 x float> poison, <2 x i32> zeroinitializer174 %mul = fmul contract <2 x float> %c, %b175 %elv = extractelement <2 x float> %mul, i64 0176 %add = fadd contract float %elv, %c1177 store float %add, ptr addrspace(1) %gep, align 4178 ret void179}180