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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s3 4; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI %s5 6; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI %s7 8; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s9; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s10 11define half @test_fmax_legacy_ugt_f16(half %a, half %b) #0 {12; GFX9-LABEL: test_fmax_legacy_ugt_f16:13; GFX9: ; %bb.0:14; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v116; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc17; GFX9-NEXT: s_setpc_b64 s[30:31]18;19; VI-LABEL: test_fmax_legacy_ugt_f16:20; VI: ; %bb.0:21; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)22; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v123; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc24; VI-NEXT: s_setpc_b64 s[30:31]25;26; SI-LABEL: test_fmax_legacy_ugt_f16:27; SI: ; %bb.0:28; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)29; SI-NEXT: v_cvt_f16_f32_e32 v0, v030; SI-NEXT: v_cvt_f16_f32_e32 v1, v131; SI-NEXT: v_cvt_f32_f16_e32 v0, v032; SI-NEXT: v_cvt_f32_f16_e32 v1, v133; SI-NEXT: v_max_legacy_f32_e32 v0, v1, v034; SI-NEXT: s_setpc_b64 s[30:31]35;36; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_f16:37; GFX11-TRUE16: ; %bb.0:38; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)39; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l40; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo41; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]42;43; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_f16:44; GFX11-FAKE16: ; %bb.0:45; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v147; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo48; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]49 %cmp = fcmp ugt half %a, %b50 %val = select i1 %cmp, half %a, half %b51 ret half %val52}53 54define half @test_fmax_legacy_ugt_f16_fast(half %a, half %b) #0 {55; GFX9-LABEL: test_fmax_legacy_ugt_f16_fast:56; GFX9: ; %bb.0:57; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; GFX9-NEXT: v_max_f16_e32 v0, v0, v159; GFX9-NEXT: s_setpc_b64 s[30:31]60;61; VI-LABEL: test_fmax_legacy_ugt_f16_fast:62; VI: ; %bb.0:63; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)64; VI-NEXT: v_max_f16_e32 v0, v0, v165; VI-NEXT: s_setpc_b64 s[30:31]66;67; SI-LABEL: test_fmax_legacy_ugt_f16_fast:68; SI: ; %bb.0:69; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)70; SI-NEXT: v_cvt_f16_f32_e32 v1, v171; SI-NEXT: v_cvt_f16_f32_e32 v0, v072; SI-NEXT: v_cvt_f32_f16_e32 v1, v173; SI-NEXT: v_cvt_f32_f16_e32 v0, v074; SI-NEXT: v_max_f32_e32 v0, v0, v175; SI-NEXT: s_setpc_b64 s[30:31]76;77; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_f16_fast:78; GFX11-TRUE16: ; %bb.0:79; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)80; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l81; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]82;83; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_f16_fast:84; GFX11-FAKE16: ; %bb.0:85; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)86; GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v187; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]88 %cmp = fcmp ugt half %a, %b89 %val = select nnan nsz i1 %cmp, half %a, half %b90 ret half %val91}92 93define <2 x half> @test_fmax_legacy_ugt_v2f16(<2 x half> %a, <2 x half> %b) #0 {94; GFX9-LABEL: test_fmax_legacy_ugt_v2f16:95; GFX9: ; %bb.0:96; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)97; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v198; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v099; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2100; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc101; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1102; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc103; GFX9-NEXT: s_mov_b32 s4, 0x5040100104; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4105; GFX9-NEXT: s_setpc_b64 s[30:31]106;107; VI-LABEL: test_fmax_legacy_ugt_v2f16:108; VI: ; %bb.0:109; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)110; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1111; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0112; VI-NEXT: v_cmp_nle_f16_e32 vcc, v3, v2113; VI-NEXT: v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD114; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1115; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc116; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD117; VI-NEXT: s_setpc_b64 s[30:31]118;119; SI-LABEL: test_fmax_legacy_ugt_v2f16:120; SI: ; %bb.0:121; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; SI-NEXT: v_cvt_f16_f32_e32 v1, v1123; SI-NEXT: v_cvt_f16_f32_e32 v3, v3124; SI-NEXT: v_cvt_f16_f32_e32 v0, v0125; SI-NEXT: v_cvt_f16_f32_e32 v2, v2126; SI-NEXT: v_cvt_f32_f16_e32 v1, v1127; SI-NEXT: v_cvt_f32_f16_e32 v3, v3128; SI-NEXT: v_cvt_f32_f16_e32 v0, v0129; SI-NEXT: v_cvt_f32_f16_e32 v2, v2130; SI-NEXT: v_max_legacy_f32_e32 v0, v2, v0131; SI-NEXT: v_max_legacy_f32_e32 v1, v3, v1132; SI-NEXT: s_setpc_b64 s[30:31]133;134; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v2f16:135; GFX11-TRUE16: ; %bb.0:136; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)137; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h138; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v1.l139; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo140; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)141; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0142; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]143;144; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v2f16:145; GFX11-FAKE16: ; %bb.0:146; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)147; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1148; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0149; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)150; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v2151; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo152; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1153; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo154; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100155; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]156 %cmp = fcmp ugt <2 x half> %a, %b157 %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b158 ret <2 x half> %val159}160 161define <2 x half> @test_fmax_legacy_ugt_v2f16_fast(<2 x half> %a, <2 x half> %b) #0 {162; GFX9-LABEL: test_fmax_legacy_ugt_v2f16_fast:163; GFX9: ; %bb.0:164; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; GFX9-NEXT: v_pk_max_f16 v0, v0, v1166; GFX9-NEXT: s_setpc_b64 s[30:31]167;168; VI-LABEL: test_fmax_legacy_ugt_v2f16_fast:169; VI: ; %bb.0:170; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)171; VI-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1172; VI-NEXT: v_max_f16_e32 v0, v0, v1173; VI-NEXT: v_or_b32_e32 v0, v0, v2174; VI-NEXT: s_setpc_b64 s[30:31]175;176; SI-LABEL: test_fmax_legacy_ugt_v2f16_fast:177; SI: ; %bb.0:178; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)179; SI-NEXT: v_cvt_f16_f32_e32 v3, v3180; SI-NEXT: v_cvt_f16_f32_e32 v1, v1181; SI-NEXT: v_cvt_f16_f32_e32 v2, v2182; SI-NEXT: v_cvt_f16_f32_e32 v0, v0183; SI-NEXT: v_cvt_f32_f16_e32 v3, v3184; SI-NEXT: v_cvt_f32_f16_e32 v1, v1185; SI-NEXT: v_cvt_f32_f16_e32 v2, v2186; SI-NEXT: v_cvt_f32_f16_e32 v0, v0187; SI-NEXT: v_max_f32_e32 v0, v0, v2188; SI-NEXT: v_max_f32_e32 v1, v1, v3189; SI-NEXT: s_setpc_b64 s[30:31]190;191; GFX11-LABEL: test_fmax_legacy_ugt_v2f16_fast:192; GFX11: ; %bb.0:193; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)194; GFX11-NEXT: v_pk_max_f16 v0, v0, v1195; GFX11-NEXT: s_setpc_b64 s[30:31]196 %cmp = fcmp ugt <2 x half> %a, %b197 %val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b198 ret <2 x half> %val199}200 201define <3 x half> @test_fmax_legacy_ugt_v3f16(<3 x half> %a, <3 x half> %b) #0 {202; GFX9-LABEL: test_fmax_legacy_ugt_v3f16:203; GFX9: ; %bb.0:204; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)205; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2206; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0207; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4208; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc209; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3210; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc211; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2212; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc213; GFX9-NEXT: s_mov_b32 s4, 0x5040100214; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4215; GFX9-NEXT: s_setpc_b64 s[30:31]216;217; VI-LABEL: test_fmax_legacy_ugt_v3f16:218; VI: ; %bb.0:219; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)220; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2221; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0222; VI-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4223; VI-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD224; VI-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3225; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc226; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2227; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc228; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD229; VI-NEXT: s_setpc_b64 s[30:31]230;231; SI-LABEL: test_fmax_legacy_ugt_v3f16:232; SI: ; %bb.0:233; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)234; SI-NEXT: v_cvt_f16_f32_e32 v2, v2235; SI-NEXT: v_cvt_f16_f32_e32 v5, v5236; SI-NEXT: v_cvt_f16_f32_e32 v1, v1237; SI-NEXT: v_cvt_f16_f32_e32 v4, v4238; SI-NEXT: v_cvt_f16_f32_e32 v0, v0239; SI-NEXT: v_cvt_f16_f32_e32 v3, v3240; SI-NEXT: v_cvt_f32_f16_e32 v2, v2241; SI-NEXT: v_cvt_f32_f16_e32 v5, v5242; SI-NEXT: v_cvt_f32_f16_e32 v1, v1243; SI-NEXT: v_cvt_f32_f16_e32 v4, v4244; SI-NEXT: v_cvt_f32_f16_e32 v0, v0245; SI-NEXT: v_cvt_f32_f16_e32 v3, v3246; SI-NEXT: v_max_legacy_f32_e32 v0, v3, v0247; SI-NEXT: v_max_legacy_f32_e32 v1, v4, v1248; SI-NEXT: v_max_legacy_f32_e32 v2, v5, v2249; SI-NEXT: s_setpc_b64 s[30:31]250;251; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v3f16:252; GFX11-TRUE16: ; %bb.0:253; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)254; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v2.h255; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v2.l256; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v1.l, v3.l257; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo258; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)259; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0260; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1261; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]262;263; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v3f16:264; GFX11-FAKE16: ; %bb.0:265; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)266; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2267; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0268; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2269; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo270; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)271; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v5, v4272; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo273; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v3274; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo275; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100276; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]277 %cmp = fcmp ugt <3 x half> %a, %b278 %val = select <3 x i1> %cmp, <3 x half> %a, <3 x half> %b279 ret <3 x half> %val280}281 282define <3 x half> @test_fmax_legacy_ugt_v3f16_fast(<3 x half> %a, <3 x half> %b) #0 {283; GFX9-LABEL: test_fmax_legacy_ugt_v3f16_fast:284; GFX9: ; %bb.0:285; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)286; GFX9-NEXT: v_pk_max_f16 v3, v3, v3287; GFX9-NEXT: v_pk_max_f16 v1, v1, v1288; GFX9-NEXT: v_pk_max_f16 v1, v1, v3289; GFX9-NEXT: v_pk_max_f16 v0, v0, v2290; GFX9-NEXT: s_setpc_b64 s[30:31]291;292; VI-LABEL: test_fmax_legacy_ugt_v3f16_fast:293; VI: ; %bb.0:294; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; VI-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1296; VI-NEXT: v_max_f16_e32 v0, v0, v2297; VI-NEXT: v_max_f16_e32 v1, v1, v3298; VI-NEXT: v_or_b32_e32 v0, v0, v4299; VI-NEXT: s_setpc_b64 s[30:31]300;301; SI-LABEL: test_fmax_legacy_ugt_v3f16_fast:302; SI: ; %bb.0:303; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)304; SI-NEXT: v_cvt_f16_f32_e32 v5, v5305; SI-NEXT: v_cvt_f16_f32_e32 v2, v2306; SI-NEXT: v_cvt_f16_f32_e32 v4, v4307; SI-NEXT: v_cvt_f16_f32_e32 v1, v1308; SI-NEXT: v_cvt_f16_f32_e32 v3, v3309; SI-NEXT: v_cvt_f16_f32_e32 v0, v0310; SI-NEXT: v_cvt_f32_f16_e32 v5, v5311; SI-NEXT: v_cvt_f32_f16_e32 v2, v2312; SI-NEXT: v_cvt_f32_f16_e32 v4, v4313; SI-NEXT: v_cvt_f32_f16_e32 v1, v1314; SI-NEXT: v_cvt_f32_f16_e32 v3, v3315; SI-NEXT: v_cvt_f32_f16_e32 v0, v0316; SI-NEXT: v_max_f32_e32 v0, v0, v3317; SI-NEXT: v_max_f32_e32 v1, v1, v4318; SI-NEXT: v_max_f32_e32 v2, v2, v5319; SI-NEXT: s_setpc_b64 s[30:31]320;321; GFX11-LABEL: test_fmax_legacy_ugt_v3f16_fast:322; GFX11: ; %bb.0:323; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)324; GFX11-NEXT: v_pk_max_f16 v3, v3, v3325; GFX11-NEXT: v_pk_max_f16 v1, v1, v1326; GFX11-NEXT: v_pk_max_f16 v0, v0, v2327; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)328; GFX11-NEXT: v_pk_max_f16 v1, v1, v3329; GFX11-NEXT: s_setpc_b64 s[30:31]330 %cmp = fcmp ugt <3 x half> %a, %b331 %val = select nnan nsz <3 x i1> %cmp, <3 x half> %a, <3 x half> %b332 ret <3 x half> %val333}334 335define <4 x half> @test_fmax_legacy_ugt_v4f16(<4 x half> %a, <4 x half> %b) #0 {336; GFX9-LABEL: test_fmax_legacy_ugt_v4f16:337; GFX9: ; %bb.0:338; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)339; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3340; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v1341; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2342; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0343; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6344; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc345; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4346; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc347; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3348; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc349; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2350; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc351; GFX9-NEXT: s_mov_b32 s4, 0x5040100352; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4353; GFX9-NEXT: v_perm_b32 v1, v6, v1, s4354; GFX9-NEXT: s_setpc_b64 s[30:31]355;356; VI-LABEL: test_fmax_legacy_ugt_v4f16:357; VI: ; %bb.0:358; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)359; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3360; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v1361; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2362; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0363; VI-NEXT: v_cmp_nle_f16_e32 vcc, v7, v6364; VI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc365; VI-NEXT: v_cmp_nle_f16_e32 vcc, v5, v4366; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc367; VI-NEXT: v_cmp_nle_f16_e32 vcc, v1, v3368; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc369; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v2370; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc371; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v4372; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD373; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6374; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD375; VI-NEXT: s_setpc_b64 s[30:31]376;377; SI-LABEL: test_fmax_legacy_ugt_v4f16:378; SI: ; %bb.0:379; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)380; SI-NEXT: v_cvt_f16_f32_e32 v3, v3381; SI-NEXT: v_cvt_f16_f32_e32 v7, v7382; SI-NEXT: v_cvt_f16_f32_e32 v2, v2383; SI-NEXT: v_cvt_f16_f32_e32 v6, v6384; SI-NEXT: v_cvt_f16_f32_e32 v1, v1385; SI-NEXT: v_cvt_f16_f32_e32 v5, v5386; SI-NEXT: v_cvt_f16_f32_e32 v0, v0387; SI-NEXT: v_cvt_f16_f32_e32 v4, v4388; SI-NEXT: v_cvt_f32_f16_e32 v3, v3389; SI-NEXT: v_cvt_f32_f16_e32 v7, v7390; SI-NEXT: v_cvt_f32_f16_e32 v2, v2391; SI-NEXT: v_cvt_f32_f16_e32 v6, v6392; SI-NEXT: v_cvt_f32_f16_e32 v1, v1393; SI-NEXT: v_cvt_f32_f16_e32 v5, v5394; SI-NEXT: v_cvt_f32_f16_e32 v0, v0395; SI-NEXT: v_cvt_f32_f16_e32 v4, v4396; SI-NEXT: v_max_legacy_f32_e32 v0, v4, v0397; SI-NEXT: v_max_legacy_f32_e32 v1, v5, v1398; SI-NEXT: v_max_legacy_f32_e32 v2, v6, v2399; SI-NEXT: v_max_legacy_f32_e32 v3, v7, v3400; SI-NEXT: s_setpc_b64 s[30:31]401;402; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v4f16:403; GFX11-TRUE16: ; %bb.0:404; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)405; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.h, v3.h406; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.h, v2.h407; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v0.l, v2.l408; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v1.l, v3.l409; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo410; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)411; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0412; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1413; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)414; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2415; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]416;417; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v4f16:418; GFX11-FAKE16: ; %bb.0:419; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)420; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3421; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1422; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2423; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0424; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)425; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v5, v4426; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo427; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v7, v6428; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo429; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2430; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo431; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v3432; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo433; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)434; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100435; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100436; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]437 %cmp = fcmp ugt <4 x half> %a, %b438 %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b439 ret <4 x half> %val440}441 442define <4 x half> @test_fmax_legacy_ugt_v4f16_fast(<4 x half> %a, <4 x half> %b) #0 {443; GFX9-LABEL: test_fmax_legacy_ugt_v4f16_fast:444; GFX9: ; %bb.0:445; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)446; GFX9-NEXT: v_pk_max_f16 v0, v0, v2447; GFX9-NEXT: v_pk_max_f16 v1, v1, v3448; GFX9-NEXT: s_setpc_b64 s[30:31]449;450; VI-LABEL: test_fmax_legacy_ugt_v4f16_fast:451; VI: ; %bb.0:452; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)453; VI-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1454; VI-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1455; VI-NEXT: v_max_f16_e32 v1, v1, v3456; VI-NEXT: v_max_f16_e32 v0, v0, v2457; VI-NEXT: v_or_b32_e32 v0, v0, v5458; VI-NEXT: v_or_b32_e32 v1, v1, v4459; VI-NEXT: s_setpc_b64 s[30:31]460;461; SI-LABEL: test_fmax_legacy_ugt_v4f16_fast:462; SI: ; %bb.0:463; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)464; SI-NEXT: v_cvt_f16_f32_e32 v7, v7465; SI-NEXT: v_cvt_f16_f32_e32 v3, v3466; SI-NEXT: v_cvt_f16_f32_e32 v6, v6467; SI-NEXT: v_cvt_f16_f32_e32 v2, v2468; SI-NEXT: v_cvt_f16_f32_e32 v5, v5469; SI-NEXT: v_cvt_f16_f32_e32 v1, v1470; SI-NEXT: v_cvt_f16_f32_e32 v4, v4471; SI-NEXT: v_cvt_f16_f32_e32 v0, v0472; SI-NEXT: v_cvt_f32_f16_e32 v7, v7473; SI-NEXT: v_cvt_f32_f16_e32 v3, v3474; SI-NEXT: v_cvt_f32_f16_e32 v6, v6475; SI-NEXT: v_cvt_f32_f16_e32 v2, v2476; SI-NEXT: v_cvt_f32_f16_e32 v5, v5477; SI-NEXT: v_cvt_f32_f16_e32 v1, v1478; SI-NEXT: v_cvt_f32_f16_e32 v4, v4479; SI-NEXT: v_cvt_f32_f16_e32 v0, v0480; SI-NEXT: v_max_f32_e32 v0, v0, v4481; SI-NEXT: v_max_f32_e32 v1, v1, v5482; SI-NEXT: v_max_f32_e32 v2, v2, v6483; SI-NEXT: v_max_f32_e32 v3, v3, v7484; SI-NEXT: s_setpc_b64 s[30:31]485;486; GFX11-LABEL: test_fmax_legacy_ugt_v4f16_fast:487; GFX11: ; %bb.0:488; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)489; GFX11-NEXT: v_pk_max_f16 v0, v0, v2490; GFX11-NEXT: v_pk_max_f16 v1, v1, v3491; GFX11-NEXT: s_setpc_b64 s[30:31]492 %cmp = fcmp ugt <4 x half> %a, %b493 %val = select nnan nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b494 ret <4 x half> %val495}496 497define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 {498; GFX9-LABEL: test_fmax_legacy_ugt_v8f16:499; GFX9: ; %bb.0:500; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)501; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7502; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v3503; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v6504; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v2505; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14506; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5507; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v1508; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc509; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12510; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v4511; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0512; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc513; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10514; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc515; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8516; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc517; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7518; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc519; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6520; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc521; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5522; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc523; GFX9-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4524; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc525; GFX9-NEXT: s_mov_b32 s4, 0x5040100526; GFX9-NEXT: v_perm_b32 v0, v8, v0, s4527; GFX9-NEXT: v_perm_b32 v1, v10, v1, s4528; GFX9-NEXT: v_perm_b32 v2, v12, v2, s4529; GFX9-NEXT: v_perm_b32 v3, v14, v3, s4530; GFX9-NEXT: s_setpc_b64 s[30:31]531;532; VI-LABEL: test_fmax_legacy_ugt_v8f16:533; VI: ; %bb.0:534; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)535; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v7536; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v3537; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v6538; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v2539; VI-NEXT: v_cmp_nle_f16_e32 vcc, v15, v14540; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v5541; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v1542; VI-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc543; VI-NEXT: v_cmp_nle_f16_e32 vcc, v13, v12544; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v4545; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0546; VI-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc547; VI-NEXT: v_cmp_nle_f16_e32 vcc, v11, v10548; VI-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc549; VI-NEXT: v_cmp_nle_f16_e32 vcc, v9, v8550; VI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc551; VI-NEXT: v_cmp_nle_f16_e32 vcc, v3, v7552; VI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc553; VI-NEXT: v_cmp_nle_f16_e32 vcc, v2, v6554; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc555; VI-NEXT: v_cmp_nle_f16_e32 vcc, v1, v5556; VI-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc557; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v4558; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc559; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v8560; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD561; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v10562; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD563; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v12564; VI-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD565; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14566; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD567; VI-NEXT: s_setpc_b64 s[30:31]568;569; SI-LABEL: test_fmax_legacy_ugt_v8f16:570; SI: ; %bb.0:571; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)572; SI-NEXT: v_cvt_f16_f32_e32 v7, v7573; SI-NEXT: v_cvt_f16_f32_e32 v15, v15574; SI-NEXT: v_cvt_f16_f32_e32 v6, v6575; SI-NEXT: v_cvt_f16_f32_e32 v14, v14576; SI-NEXT: v_cvt_f16_f32_e32 v5, v5577; SI-NEXT: v_cvt_f16_f32_e32 v13, v13578; SI-NEXT: v_cvt_f16_f32_e32 v4, v4579; SI-NEXT: v_cvt_f16_f32_e32 v12, v12580; SI-NEXT: v_cvt_f16_f32_e32 v3, v3581; SI-NEXT: v_cvt_f16_f32_e32 v11, v11582; SI-NEXT: v_cvt_f16_f32_e32 v2, v2583; SI-NEXT: v_cvt_f16_f32_e32 v10, v10584; SI-NEXT: v_cvt_f16_f32_e32 v1, v1585; SI-NEXT: v_cvt_f16_f32_e32 v9, v9586; SI-NEXT: v_cvt_f16_f32_e32 v0, v0587; SI-NEXT: v_cvt_f16_f32_e32 v8, v8588; SI-NEXT: v_cvt_f32_f16_e32 v7, v7589; SI-NEXT: v_cvt_f32_f16_e32 v15, v15590; SI-NEXT: v_cvt_f32_f16_e32 v6, v6591; SI-NEXT: v_cvt_f32_f16_e32 v14, v14592; SI-NEXT: v_cvt_f32_f16_e32 v5, v5593; SI-NEXT: v_cvt_f32_f16_e32 v13, v13594; SI-NEXT: v_cvt_f32_f16_e32 v4, v4595; SI-NEXT: v_cvt_f32_f16_e32 v12, v12596; SI-NEXT: v_cvt_f32_f16_e32 v3, v3597; SI-NEXT: v_cvt_f32_f16_e32 v11, v11598; SI-NEXT: v_cvt_f32_f16_e32 v2, v2599; SI-NEXT: v_cvt_f32_f16_e32 v10, v10600; SI-NEXT: v_cvt_f32_f16_e32 v1, v1601; SI-NEXT: v_cvt_f32_f16_e32 v9, v9602; SI-NEXT: v_cvt_f32_f16_e32 v0, v0603; SI-NEXT: v_cvt_f32_f16_e32 v8, v8604; SI-NEXT: v_max_legacy_f32_e32 v0, v8, v0605; SI-NEXT: v_max_legacy_f32_e32 v1, v9, v1606; SI-NEXT: v_max_legacy_f32_e32 v2, v10, v2607; SI-NEXT: v_max_legacy_f32_e32 v3, v11, v3608; SI-NEXT: v_max_legacy_f32_e32 v4, v12, v4609; SI-NEXT: v_max_legacy_f32_e32 v5, v13, v5610; SI-NEXT: v_max_legacy_f32_e32 v6, v14, v6611; SI-NEXT: v_max_legacy_f32_e32 v7, v15, v7612; SI-NEXT: s_setpc_b64 s[30:31]613;614; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v8f16:615; GFX11-TRUE16: ; %bb.0:616; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)617; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v4.h618; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v1.h, v5.h619; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v2.h, v6.h620; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v3.h, v7.h621; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s3, v0.l, v4.l622; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s4, v1.l, v5.l623; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s5, v2.l, v6.l624; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s6, v3.l, v7.l625; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2626; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s1627; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0628; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo629; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3630; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4631; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5632; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6633; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]634;635; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v8f16:636; GFX11-FAKE16: ; %bb.0:637; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)638; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7639; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3640; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6641; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2642; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5643; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1644; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v11, v10645; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4646; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0647; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo648; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v13, v12649; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc_lo650; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v15, v14651; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo652; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v9, v8653; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo654; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v2, v6655; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo656; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v4657; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)658; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100659; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo660; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v5661; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo662; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v7663; GFX11-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100664; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo665; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100666; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)667; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100668; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]669 %cmp = fcmp ugt <8 x half> %a, %b670 %val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b671 ret <8 x half> %val672}673 674define <8 x half> @test_fmax_legacy_ugt_v8f16_fast(<8 x half> %a, <8 x half> %b) #0 {675; GFX9-LABEL: test_fmax_legacy_ugt_v8f16_fast:676; GFX9: ; %bb.0:677; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)678; GFX9-NEXT: v_pk_max_f16 v0, v0, v4679; GFX9-NEXT: v_pk_max_f16 v1, v1, v5680; GFX9-NEXT: v_pk_max_f16 v2, v2, v6681; GFX9-NEXT: v_pk_max_f16 v3, v3, v7682; GFX9-NEXT: s_setpc_b64 s[30:31]683;684; VI-LABEL: test_fmax_legacy_ugt_v8f16_fast:685; VI: ; %bb.0:686; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)687; VI-NEXT: v_max_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1688; VI-NEXT: v_max_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1689; VI-NEXT: v_max_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1690; VI-NEXT: v_max_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1691; VI-NEXT: v_max_f16_e32 v3, v3, v7692; VI-NEXT: v_max_f16_e32 v2, v2, v6693; VI-NEXT: v_max_f16_e32 v1, v1, v5694; VI-NEXT: v_max_f16_e32 v0, v0, v4695; VI-NEXT: v_or_b32_e32 v0, v0, v11696; VI-NEXT: v_or_b32_e32 v1, v1, v10697; VI-NEXT: v_or_b32_e32 v2, v2, v9698; VI-NEXT: v_or_b32_e32 v3, v3, v8699; VI-NEXT: s_setpc_b64 s[30:31]700;701; SI-LABEL: test_fmax_legacy_ugt_v8f16_fast:702; SI: ; %bb.0:703; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)704; SI-NEXT: v_cvt_f16_f32_e32 v15, v15705; SI-NEXT: v_cvt_f16_f32_e32 v7, v7706; SI-NEXT: v_cvt_f16_f32_e32 v14, v14707; SI-NEXT: v_cvt_f16_f32_e32 v6, v6708; SI-NEXT: v_cvt_f16_f32_e32 v13, v13709; SI-NEXT: v_cvt_f16_f32_e32 v5, v5710; SI-NEXT: v_cvt_f16_f32_e32 v12, v12711; SI-NEXT: v_cvt_f16_f32_e32 v4, v4712; SI-NEXT: v_cvt_f16_f32_e32 v11, v11713; SI-NEXT: v_cvt_f16_f32_e32 v3, v3714; SI-NEXT: v_cvt_f16_f32_e32 v10, v10715; SI-NEXT: v_cvt_f16_f32_e32 v2, v2716; SI-NEXT: v_cvt_f16_f32_e32 v9, v9717; SI-NEXT: v_cvt_f16_f32_e32 v1, v1718; SI-NEXT: v_cvt_f16_f32_e32 v8, v8719; SI-NEXT: v_cvt_f16_f32_e32 v0, v0720; SI-NEXT: v_cvt_f32_f16_e32 v15, v15721; SI-NEXT: v_cvt_f32_f16_e32 v7, v7722; SI-NEXT: v_cvt_f32_f16_e32 v14, v14723; SI-NEXT: v_cvt_f32_f16_e32 v6, v6724; SI-NEXT: v_cvt_f32_f16_e32 v13, v13725; SI-NEXT: v_cvt_f32_f16_e32 v5, v5726; SI-NEXT: v_cvt_f32_f16_e32 v12, v12727; SI-NEXT: v_cvt_f32_f16_e32 v4, v4728; SI-NEXT: v_cvt_f32_f16_e32 v11, v11729; SI-NEXT: v_cvt_f32_f16_e32 v3, v3730; SI-NEXT: v_cvt_f32_f16_e32 v10, v10731; SI-NEXT: v_cvt_f32_f16_e32 v2, v2732; SI-NEXT: v_cvt_f32_f16_e32 v9, v9733; SI-NEXT: v_cvt_f32_f16_e32 v1, v1734; SI-NEXT: v_cvt_f32_f16_e32 v8, v8735; SI-NEXT: v_cvt_f32_f16_e32 v0, v0736; SI-NEXT: v_max_f32_e32 v0, v0, v8737; SI-NEXT: v_max_f32_e32 v1, v1, v9738; SI-NEXT: v_max_f32_e32 v2, v2, v10739; SI-NEXT: v_max_f32_e32 v3, v3, v11740; SI-NEXT: v_max_f32_e32 v4, v4, v12741; SI-NEXT: v_max_f32_e32 v5, v5, v13742; SI-NEXT: v_max_f32_e32 v6, v6, v14743; SI-NEXT: v_max_f32_e32 v7, v7, v15744; SI-NEXT: s_setpc_b64 s[30:31]745;746; GFX11-LABEL: test_fmax_legacy_ugt_v8f16_fast:747; GFX11: ; %bb.0:748; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)749; GFX11-NEXT: v_pk_max_f16 v0, v0, v4750; GFX11-NEXT: v_pk_max_f16 v1, v1, v5751; GFX11-NEXT: v_pk_max_f16 v2, v2, v6752; GFX11-NEXT: v_pk_max_f16 v3, v3, v7753; GFX11-NEXT: s_setpc_b64 s[30:31]754 %cmp = fcmp ugt <8 x half> %a, %b755 %val = select nnan nsz <8 x i1> %cmp, <8 x half> %a, <8 x half> %b756 ret <8 x half> %val757}758 759attributes #0 = { nounwind }760