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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -check-prefix=VI %s4 5; Make sure we don't try to form FMAX_LEGACY nodes with f646 7define amdgpu_kernel void @test_fmax_legacy_uge_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {8; SI-LABEL: test_fmax_legacy_uge_f64:9; SI: ; %bb.0:10; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x911; SI-NEXT: s_mov_b32 s7, 0xf00012; SI-NEXT: s_mov_b32 s10, 013; SI-NEXT: s_mov_b32 s11, s714; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v015; SI-NEXT: s_waitcnt lgkmcnt(0)16; SI-NEXT: s_mov_b64 s[8:9], s[2:3]17; SI-NEXT: v_mov_b32_e32 v1, 018; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr6419; SI-NEXT: s_mov_b32 s6, -120; SI-NEXT: s_mov_b32 s4, s021; SI-NEXT: s_mov_b32 s5, s122; SI-NEXT: s_waitcnt vmcnt(0)23; SI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]24; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc25; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc26; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 027; SI-NEXT: s_endpgm28;29; VI-LABEL: test_fmax_legacy_uge_f64:30; VI: ; %bb.0:31; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2432; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v033; VI-NEXT: s_waitcnt lgkmcnt(0)34; VI-NEXT: v_mov_b32_e32 v1, s335; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v036; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc37; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]38; VI-NEXT: v_mov_b32_e32 v4, s039; VI-NEXT: v_mov_b32_e32 v5, s140; VI-NEXT: s_waitcnt vmcnt(0)41; VI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]42; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc43; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc44; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]45; VI-NEXT: s_endpgm46 %tid = call i32 @llvm.amdgcn.workitem.id.x() #147 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid48 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 149 50 %a = load double, ptr addrspace(1) %gep.0, align 851 %b = load double, ptr addrspace(1) %gep.1, align 852 53 %cmp = fcmp uge double %a, %b54 %val = select i1 %cmp, double %a, double %b55 store double %val, ptr addrspace(1) %out, align 856 ret void57}58 59define amdgpu_kernel void @test_fmax_legacy_oge_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {60; SI-LABEL: test_fmax_legacy_oge_f64:61; SI: ; %bb.0:62; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x963; SI-NEXT: s_mov_b32 s7, 0xf00064; SI-NEXT: s_mov_b32 s10, 065; SI-NEXT: s_mov_b32 s11, s766; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v067; SI-NEXT: s_waitcnt lgkmcnt(0)68; SI-NEXT: s_mov_b64 s[8:9], s[2:3]69; SI-NEXT: v_mov_b32_e32 v1, 070; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr6471; SI-NEXT: s_mov_b32 s6, -172; SI-NEXT: s_mov_b32 s4, s073; SI-NEXT: s_mov_b32 s5, s174; SI-NEXT: s_waitcnt vmcnt(0)75; SI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]76; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc77; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc78; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 079; SI-NEXT: s_endpgm80;81; VI-LABEL: test_fmax_legacy_oge_f64:82; VI: ; %bb.0:83; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2484; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v085; VI-NEXT: s_waitcnt lgkmcnt(0)86; VI-NEXT: v_mov_b32_e32 v1, s387; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v088; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc89; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]90; VI-NEXT: v_mov_b32_e32 v4, s091; VI-NEXT: v_mov_b32_e32 v5, s192; VI-NEXT: s_waitcnt vmcnt(0)93; VI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]94; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc95; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc96; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]97; VI-NEXT: s_endpgm98 %tid = call i32 @llvm.amdgcn.workitem.id.x() #199 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid100 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1101 102 %a = load double, ptr addrspace(1) %gep.0, align 8103 %b = load double, ptr addrspace(1) %gep.1, align 8104 105 %cmp = fcmp oge double %a, %b106 %val = select i1 %cmp, double %a, double %b107 store double %val, ptr addrspace(1) %out, align 8108 ret void109}110 111define amdgpu_kernel void @test_fmax_legacy_ugt_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {112; SI-LABEL: test_fmax_legacy_ugt_f64:113; SI: ; %bb.0:114; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9115; SI-NEXT: s_mov_b32 s7, 0xf000116; SI-NEXT: s_mov_b32 s10, 0117; SI-NEXT: s_mov_b32 s11, s7118; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0119; SI-NEXT: s_waitcnt lgkmcnt(0)120; SI-NEXT: s_mov_b64 s[8:9], s[2:3]121; SI-NEXT: v_mov_b32_e32 v1, 0122; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64123; SI-NEXT: s_mov_b32 s6, -1124; SI-NEXT: s_mov_b32 s4, s0125; SI-NEXT: s_mov_b32 s5, s1126; SI-NEXT: s_waitcnt vmcnt(0)127; SI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]128; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc129; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc130; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0131; SI-NEXT: s_endpgm132;133; VI-LABEL: test_fmax_legacy_ugt_f64:134; VI: ; %bb.0:135; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24136; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0137; VI-NEXT: s_waitcnt lgkmcnt(0)138; VI-NEXT: v_mov_b32_e32 v1, s3139; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0140; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc141; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]142; VI-NEXT: v_mov_b32_e32 v4, s0143; VI-NEXT: v_mov_b32_e32 v5, s1144; VI-NEXT: s_waitcnt vmcnt(0)145; VI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]146; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc147; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc148; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]149; VI-NEXT: s_endpgm150 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1151 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid152 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1153 154 %a = load double, ptr addrspace(1) %gep.0, align 8155 %b = load double, ptr addrspace(1) %gep.1, align 8156 157 %cmp = fcmp ugt double %a, %b158 %val = select i1 %cmp, double %a, double %b159 store double %val, ptr addrspace(1) %out, align 8160 ret void161}162 163define amdgpu_kernel void @test_fmax_legacy_ogt_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {164; SI-LABEL: test_fmax_legacy_ogt_f64:165; SI: ; %bb.0:166; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9167; SI-NEXT: s_mov_b32 s7, 0xf000168; SI-NEXT: s_mov_b32 s10, 0169; SI-NEXT: s_mov_b32 s11, s7170; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0171; SI-NEXT: s_waitcnt lgkmcnt(0)172; SI-NEXT: s_mov_b64 s[8:9], s[2:3]173; SI-NEXT: v_mov_b32_e32 v1, 0174; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64175; SI-NEXT: s_mov_b32 s6, -1176; SI-NEXT: s_mov_b32 s4, s0177; SI-NEXT: s_mov_b32 s5, s1178; SI-NEXT: s_waitcnt vmcnt(0)179; SI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]180; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc181; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc182; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0183; SI-NEXT: s_endpgm184;185; VI-LABEL: test_fmax_legacy_ogt_f64:186; VI: ; %bb.0:187; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24188; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0189; VI-NEXT: s_waitcnt lgkmcnt(0)190; VI-NEXT: v_mov_b32_e32 v1, s3191; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0192; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc193; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]194; VI-NEXT: v_mov_b32_e32 v4, s0195; VI-NEXT: v_mov_b32_e32 v5, s1196; VI-NEXT: s_waitcnt vmcnt(0)197; VI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]198; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc199; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc200; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]201; VI-NEXT: s_endpgm202 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1203 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid204 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1205 206 %a = load double, ptr addrspace(1) %gep.0, align 8207 %b = load double, ptr addrspace(1) %gep.1, align 8208 209 %cmp = fcmp ogt double %a, %b210 %val = select i1 %cmp, double %a, double %b211 store double %val, ptr addrspace(1) %out, align 8212 ret void213}214 215declare i32 @llvm.amdgcn.workitem.id.x() #1216 217attributes #0 = { nounwind }218attributes #1 = { nounwind readnone }219