360 lines · plain
1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN,FUNC %s2 3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,FUNC %s4 5; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s6 7declare i32 @llvm.amdgcn.workitem.id.x() #18 9; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32:10; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]11; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]12 13; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]14 15; VI: v_cmp_nlt_f32_e32 vcc, [[A]], [[B]]16; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]17 18; EG: MAX19define amdgpu_kernel void @test_fmax_legacy_uge_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {20 %tid = call i32 @llvm.amdgcn.workitem.id.x() #121 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid22 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 123 24 %a = load volatile float, ptr addrspace(1) %gep.0, align 425 %b = load volatile float, ptr addrspace(1) %gep.1, align 426 27 %cmp = fcmp uge float %a, %b28 %val = select i1 %cmp, float %a, float %b29 store float %val, ptr addrspace(1) %out, align 430 ret void31}32 33; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_fast:34; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]35; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]36 37; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]38 39; EG: MAX40define amdgpu_kernel void @test_fmax_legacy_uge_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {41 %tid = call i32 @llvm.amdgcn.workitem.id.x() #142 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid43 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 144 45 %a = load volatile float, ptr addrspace(1) %gep.0, align 446 %b = load volatile float, ptr addrspace(1) %gep.1, align 447 48 %cmp = fcmp uge float %a, %b49 %val = select nnan nsz i1 %cmp, float %a, float %b50 store float %val, ptr addrspace(1) %out, align 451 ret void52}53 54; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_nnan_src:55; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]56; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]57; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]]58; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]]59 60; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]61 62; VI: v_cmp_nlt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]63; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[ADD_B]], [[ADD_A]]64 65 66; EG: MAX67define amdgpu_kernel void @test_fmax_legacy_uge_f32_nnan_src(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {68 %tid = call i32 @llvm.amdgcn.workitem.id.x() #169 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid70 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 171 72 %a = load volatile float, ptr addrspace(1) %gep.0, align 473 %b = load volatile float, ptr addrspace(1) %gep.1, align 474 %a.nnan = fadd nnan float %a, 1.075 %b.nnan = fadd nnan float %b, 2.076 77 %cmp = fcmp uge float %a.nnan, %b.nnan78 %val = select i1 %cmp, float %a.nnan, float %b.nnan79 store float %val, ptr addrspace(1) %out, align 480 ret void81}82 83; FUNC-LABEL: {{^}}test_fmax_legacy_uge_f32_nnan_src_fast:84; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]85; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]86; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]]87; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]]88 89; GCN: v_max_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]90 91; EG: MAX92define amdgpu_kernel void @test_fmax_legacy_uge_f32_nnan_src_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {93 %tid = call i32 @llvm.amdgcn.workitem.id.x() #194 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid95 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 196 97 %a = load volatile float, ptr addrspace(1) %gep.0, align 498 %b = load volatile float, ptr addrspace(1) %gep.1, align 499 %a.nnan = fadd nnan float %a, 1.0100 %b.nnan = fadd nnan float %b, 2.0101 102 %cmp = fcmp uge float %a.nnan, %b.nnan103 %val = select nnan nsz i1 %cmp, float %a.nnan, float %b.nnan104 store float %val, ptr addrspace(1) %out, align 4105 ret void106}107 108; FUNC-LABEL: {{^}}test_fmax_legacy_oge_f32:109; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]110; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]111 112; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]113 114; VI: v_cmp_ge_f32_e32 vcc, [[A]], [[B]]115; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]116 117; EG: MAX118define amdgpu_kernel void @test_fmax_legacy_oge_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {119 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1120 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid121 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1122 123 %a = load volatile float, ptr addrspace(1) %gep.0, align 4124 %b = load volatile float, ptr addrspace(1) %gep.1, align 4125 126 %cmp = fcmp oge float %a, %b127 %val = select i1 %cmp, float %a, float %b128 store float %val, ptr addrspace(1) %out, align 4129 ret void130}131 132; FUNC-LABEL: {{^}}test_fmax_legacy_oge_f32_fast:133; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]134; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]135 136; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]137; EG: MAX138define amdgpu_kernel void @test_fmax_legacy_oge_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {139 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1140 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid141 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1142 143 %a = load volatile float, ptr addrspace(1) %gep.0, align 4144 %b = load volatile float, ptr addrspace(1) %gep.1, align 4145 146 %cmp = fcmp oge float %a, %b147 %val = select nnan nsz i1 %cmp, float %a, float %b148 store float %val, ptr addrspace(1) %out, align 4149 ret void150}151 152; FUNC-LABEL: {{^}}test_fmax_legacy_ugt_f32:153; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]154; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]155 156; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]157 158; VI: v_cmp_nle_f32_e32 vcc, [[A]], [[B]]159; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]160 161; EG: MAX162define amdgpu_kernel void @test_fmax_legacy_ugt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {163 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1164 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid165 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1166 167 %a = load volatile float, ptr addrspace(1) %gep.0, align 4168 %b = load volatile float, ptr addrspace(1) %gep.1, align 4169 170 %cmp = fcmp ugt float %a, %b171 %val = select i1 %cmp, float %a, float %b172 store float %val, ptr addrspace(1) %out, align 4173 ret void174}175 176; FUNC-LABEL: {{^}}test_fmax_legacy_ugt_f32_fast:177; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]178; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]179 180; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]181; EG: MAX182define amdgpu_kernel void @test_fmax_legacy_ugt_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {183 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1184 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid185 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1186 187 %a = load volatile float, ptr addrspace(1) %gep.0, align 4188 %b = load volatile float, ptr addrspace(1) %gep.1, align 4189 190 %cmp = fcmp ugt float %a, %b191 %val = select nnan nsz i1 %cmp, float %a, float %b192 store float %val, ptr addrspace(1) %out, align 4193 ret void194}195 196; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32:197; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]198; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]199 200; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]201 202; VI: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]203; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]204 205; EG: MAX206define amdgpu_kernel void @test_fmax_legacy_ogt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {207 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1208 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid209 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1210 211 %a = load volatile float, ptr addrspace(1) %gep.0, align 4212 %b = load volatile float, ptr addrspace(1) %gep.1, align 4213 214 %cmp = fcmp ogt float %a, %b215 %val = select i1 %cmp, float %a, float %b216 store float %val, ptr addrspace(1) %out, align 4217 ret void218}219 220; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32_fast:221; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]222; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]223 224; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]225; EG: MAX226define amdgpu_kernel void @test_fmax_legacy_ogt_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {227 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1228 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid229 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1230 231 %a = load volatile float, ptr addrspace(1) %gep.0, align 4232 %b = load volatile float, ptr addrspace(1) %gep.1, align 4233 234 %cmp = fcmp ogt float %a, %b235 %val = select nnan nsz i1 %cmp, float %a, float %b236 store float %val, ptr addrspace(1) %out, align 4237 ret void238}239 240; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32:241; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]242; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]243 244; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]245 246; VI: v_cmp_gt_f32_e32 vcc, [[A]], [[B]]247; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]248 249; EG: MAX250define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {251 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1252 %gep.0 = getelementptr <1 x float>, ptr addrspace(1) %in, i32 %tid253 %gep.1 = getelementptr <1 x float>, ptr addrspace(1) %gep.0, i32 1254 255 %a = load volatile <1 x float>, ptr addrspace(1) %gep.0256 %b = load volatile <1 x float>, ptr addrspace(1) %gep.1257 258 %cmp = fcmp ogt <1 x float> %a, %b259 %val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b260 store <1 x float> %val, ptr addrspace(1) %out261 ret void262}263 264; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v1f32_fast:265; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]266; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]267 268; GCN: v_max_f32_e32 {{v[0-9]+}}, [[A]], [[B]]269; EG: MAX270define amdgpu_kernel void @test_fmax_legacy_ogt_v1f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {271 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1272 %gep.0 = getelementptr <1 x float>, ptr addrspace(1) %in, i32 %tid273 %gep.1 = getelementptr <1 x float>, ptr addrspace(1) %gep.0, i32 1274 275 %a = load volatile <1 x float>, ptr addrspace(1) %gep.0276 %b = load volatile <1 x float>, ptr addrspace(1) %gep.1277 278 %cmp = fcmp ogt <1 x float> %a, %b279 %val = select nnan nsz <1 x i1> %cmp, <1 x float> %a, <1 x float> %b280 store <1 x float> %val, ptr addrspace(1) %out281 ret void282}283 284; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32:285; SI: v_max_legacy_f32_e32286; SI: v_max_legacy_f32_e32287; SI: v_max_legacy_f32_e32288 289; VI: v_cmp_gt_f32_e32290; VI: v_cndmask_b32_e32291; VI: v_cmp_gt_f32_e32292; VI: v_cndmask_b32_e32293; VI: v_cmp_gt_f32_e32294; VI: v_cndmask_b32_e32295; VI-NOT: v_cmp296; VI-NOT: v_cndmask297 298; GCN-NOT: v_max299define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {300 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1301 %gep.0 = getelementptr <3 x float>, ptr addrspace(1) %in, i32 %tid302 %gep.1 = getelementptr <3 x float>, ptr addrspace(1) %gep.0, i32 1303 304 %a = load <3 x float>, ptr addrspace(1) %gep.0305 %b = load <3 x float>, ptr addrspace(1) %gep.1306 307 %cmp = fcmp ogt <3 x float> %a, %b308 %val = select <3 x i1> %cmp, <3 x float> %a, <3 x float> %b309 store <3 x float> %val, ptr addrspace(1) %out310 ret void311}312 313; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_v3f32_fast:314 315; GCN: v_max_f32_e32316; GCN: v_max_f32_e32317; GCN: v_max_f32_e32318 319; GCN-NOT: v_max320define amdgpu_kernel void @test_fmax_legacy_ogt_v3f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {321 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1322 %gep.0 = getelementptr <3 x float>, ptr addrspace(1) %in, i32 %tid323 %gep.1 = getelementptr <3 x float>, ptr addrspace(1) %gep.0, i32 1324 325 %a = load <3 x float>, ptr addrspace(1) %gep.0326 %b = load <3 x float>, ptr addrspace(1) %gep.1327 328 %cmp = fcmp ogt <3 x float> %a, %b329 %val = select nnan nsz <3 x i1> %cmp, <3 x float> %a, <3 x float> %b330 store <3 x float> %val, ptr addrspace(1) %out331 ret void332}333 334; FUNC-LABEL: {{^}}test_fmax_legacy_ogt_f32_multi_use:335; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]336; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]337; GCN-NOT: v_max_338; GCN: v_cmp_gt_f32339; GCN-NEXT: v_cndmask_b32340; GCN-NOT: v_max_341 342; EG: MAX343define amdgpu_kernel void @test_fmax_legacy_ogt_f32_multi_use(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %in) #0 {344 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1345 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid346 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1347 348 %a = load volatile float, ptr addrspace(1) %gep.0, align 4349 %b = load volatile float, ptr addrspace(1) %gep.1, align 4350 351 %cmp = fcmp ogt float %a, %b352 %val = select i1 %cmp, float %a, float %b353 store float %val, ptr addrspace(1) %out0, align 4354 store i1 %cmp, ptr addrspace(1) %out1355 ret void356}357 358attributes #0 = { nounwind }359attributes #1 = { nounwind readnone }360