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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI,SI-SDAG %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=VI-SDAG %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s7 8define bfloat @v_test_fmed3_r_i_i_bf16_minimumnum_maximumnum(bfloat %a) #1 {9; SI-LABEL: v_test_fmed3_r_i_i_bf16_minimumnum_maximumnum:10; SI: ; %bb.0:11; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; SI-NEXT: v_mul_f32_e32 v0, 1.0, v013; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v014; SI-NEXT: v_max_f32_e32 v0, 2.0, v015; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v016; SI-NEXT: v_min_f32_e32 v0, 4.0, v017; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v018; SI-NEXT: s_setpc_b64 s[30:31]19;20; VI-SDAG-LABEL: v_test_fmed3_r_i_i_bf16_minimumnum_maximumnum:21; VI-SDAG: ; %bb.0:22; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; VI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v024; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x400025; VI-SDAG-NEXT: v_cmp_o_f32_e32 vcc, v1, v126; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc27; VI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v028; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v129; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc30; VI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v031; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x408032; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, 4.0, v133; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc34; VI-SDAG-NEXT: s_setpc_b64 s[30:31]35;36; GFX9-LABEL: v_test_fmed3_r_i_i_bf16_minimumnum_maximumnum:37; GFX9: ; %bb.0:38; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)39; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v040; GFX9-NEXT: v_mov_b32_e32 v2, 0x400041; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v142; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc43; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v044; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v145; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc46; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v047; GFX9-NEXT: v_mov_b32_e32 v2, 0x408048; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 4.0, v149; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc50; GFX9-NEXT: s_setpc_b64 s[30:31]51;52; GFX11-SDAG-FAKE16-LABEL: v_test_fmed3_r_i_i_bf16_minimumnum_maximumnum:53; GFX11-SDAG-FAKE16: ; %bb.0:54; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)55; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v056; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)57; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v158; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v0, vcc_lo59; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v060; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)61; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v162; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v0, vcc_lo63; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v064; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)65; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v166; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4080, v0, vcc_lo67; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]68;69; GFX11-SDAG-TRUE16-LABEL: v_test_fmed3_r_i_i_bf16_minimumnum_maximumnum:70; GFX11-SDAG-TRUE16: ; %bb.0:71; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 073; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l74; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)75; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v176; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x4000, v0.l, vcc_lo77; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v178; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x4000, v1.h, vcc_lo79; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)80; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v181; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4080, v1.h, vcc_lo82; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]83 %max = call bfloat @llvm.maximumnum.bf16(bfloat %a, bfloat 2.0)84 %med = call bfloat @llvm.minimumnum.bf16(bfloat %max, bfloat 4.0)85 ret bfloat %med86}87 88define <2 x bfloat> @v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum(<2 x bfloat> %a) #1 {89; SI-LABEL: v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum:90; SI: ; %bb.0:91; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)92; SI-NEXT: v_mul_f32_e32 v1, 1.0, v193; SI-NEXT: v_mul_f32_e32 v0, 1.0, v094; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v095; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v196; SI-NEXT: v_max_f32_e32 v0, 2.0, v097; SI-NEXT: v_max_f32_e32 v1, 2.0, v198; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v199; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0100; SI-NEXT: v_min_f32_e32 v1, 4.0, v1101; SI-NEXT: v_min_f32_e32 v0, 4.0, v0102; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0103; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1104; SI-NEXT: s_setpc_b64 s[30:31]105;106; VI-SDAG-LABEL: v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum:107; VI-SDAG: ; %bb.0:108; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)109; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v0110; VI-SDAG-NEXT: v_cmp_o_f32_e32 vcc, v1, v1111; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4000112; VI-SDAG-NEXT: v_cndmask_b32_sdwa v2, v1, v0, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1113; VI-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v2114; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v3115; VI-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0116; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc117; VI-SDAG-NEXT: v_cmp_o_f32_e32 vcc, v3, v3118; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc119; VI-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0120; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v3121; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc122; VI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v2123; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, 4.0, v1124; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x4080125; VI-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0126; VI-SDAG-NEXT: v_cndmask_b32_sdwa v2, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD127; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, 4.0, v3128; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc129; VI-SDAG-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD130; VI-SDAG-NEXT: s_setpc_b64 s[30:31]131;132; GFX9-LABEL: v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum:133; GFX9: ; %bb.0:134; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)135; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v0136; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1137; GFX9-NEXT: v_mov_b32_e32 v1, 0x4000138; GFX9-NEXT: v_cndmask_b32_sdwa v2, v1, v0, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1139; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2140; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v3141; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v0142; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc143; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v3144; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc145; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v0146; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, 2.0, v3147; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc148; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v2149; GFX9-NEXT: v_mov_b32_e32 v3, 0x4080150; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 4.0, v1151; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc152; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0153; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 4.0, v2154; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc155; GFX9-NEXT: s_mov_b32 s4, 0x5040100156; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4157; GFX9-NEXT: s_setpc_b64 s[30:31]158;159; GFX11-SDAG-FAKE16-LABEL: v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum:160; GFX11-SDAG-FAKE16: ; %bb.0:161; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)162; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0163; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0164; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0165; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)166; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1167; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v2, vcc_lo168; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)169; GFX11-SDAG-FAKE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v3170; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1171; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v0, vcc_lo172; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)173; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v2174; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0175; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4000, v1, vcc_lo176; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)177; GFX11-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v3178; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1179; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4000, v0, vcc_lo180; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)181; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v2182; GFX11-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0183; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4080, v1, vcc_lo184; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)185; GFX11-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v3186; GFX11-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4080, v0, vcc_lo187; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100188; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]189;190; GFX11-SDAG-TRUE16-LABEL: v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum:191; GFX11-SDAG-TRUE16: ; %bb.0:192; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)193; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0194; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0195; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)196; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1197; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0198; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x4000, v0.h, vcc_lo199; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f32_e64 s0, v1, v1200; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)201; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v2202; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4000, v2.h, vcc_lo203; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x4000, v0.l, s0204; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)205; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v2206; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.h, vcc_lo207; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l208; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)209; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v2210; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l211; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4080, v1.l, vcc_lo212; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)213; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 4.0, v2214; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4080, v0.l, s0215; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]216 %max = call <2 x bfloat> @llvm.maximumnum.v2bf16(<2 x bfloat> %a, <2 x bfloat> splat (bfloat 2.0))217 %med = call <2 x bfloat> @llvm.minimumnum.v2bf16(<2 x bfloat> %max, <2 x bfloat> splat (bfloat 4.0))218 ret <2 x bfloat> %med219}220 221attributes #0 = { nounwind readnone }222attributes #1 = { nounwind "no-nans-fp-math"="false" }223attributes #2 = { nounwind "no-nans-fp-math"="true" }224;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:225; GFX11: {{.*}}226; GFX11-SDAG: {{.*}}227; GFX9-SDAG: {{.*}}228; SI-SDAG: {{.*}}229