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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN %s2 3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN %s4 5; GCN-LABEL: {{^}}min_fneg_select_regression_0:6; GCN-NOT: v_mul7 8; VI: v_cmp_nle_f32_e32 vcc, 1.0, v09; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc10define amdgpu_ps float @min_fneg_select_regression_0(float %a, float %b) #0 {11 %fneg.a = fsub float -0.0, %a12 %cmp.a = fcmp ult float %a, 1.013 %min.a = select i1 %cmp.a, float %fneg.a, float -1.014 ret float %min.a15}16 17; GCN-LABEL: {{^}}min_fneg_select_regression_0_fast:18; GCN-NOT: v_mul19 20define amdgpu_ps float @min_fneg_select_regression_0_fast(float %a, float %b) #0 {21 %fneg.a = fsub float -0.0, %a22 %cmp.a = fcmp ult float %a, 1.023 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float -1.024 ret float %min.a25}26 27; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0:28; GCN-NOT: v_mul29 30; SI: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v031 32; VI: v_cmp_nle_f32_e32 vcc, -1.0, v033; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc34define amdgpu_ps float @min_fneg_select_regression_posk_0(float %a, float %b) #0 {35 %fneg.a = fsub float -0.0, %a36 %cmp.a = fcmp ult float %a, -1.037 %min.a = select i1 %cmp.a, float %fneg.a, float 1.038 ret float %min.a39}40 41; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0_fast:42; GCN-NOT: v_mul43 44; VI: v_max_f32_e64 v{{[0-9]+}}, -v0, 1.045define amdgpu_ps float @min_fneg_select_regression_posk_0_fast(float %a, float %b) #0 {46 %fneg.a = fsub float -0.0, %a47 %cmp.a = fcmp ult float %a, -1.048 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.049 ret float %min.a50}51 52; GCN-LABEL: {{^}}max_fneg_select_regression_0:53; GCN-NOT: v_mul54 55; SI: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v056 57; VI: v_cmp_nge_f32_e32 vcc, 1.0, v058; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc59define amdgpu_ps float @max_fneg_select_regression_0(float %a) #0 {60 %fneg.a = fsub float -0.0, %a61 %cmp.a = fcmp ugt float %a, 1.062 %min.a = select i1 %cmp.a, float %fneg.a, float -1.063 ret float %min.a64}65 66; GCN-LABEL: {{^}}max_fneg_select_regression_0_fast:67; GCN-NOT: v_mul68 69; GCN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, -1.070define amdgpu_ps float @max_fneg_select_regression_0_fast(float %a) #0 {71 %fneg.a = fsub float -0.0, %a72 %cmp.a = fcmp ugt float %a, 1.073 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float -1.074 ret float %min.a75}76 77; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0:78; GCN-NOT: v_mul79 80; SI: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v081 82; VI: v_cmp_nge_f32_e32 vcc, -1.0, v083; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc84define amdgpu_ps float @max_fneg_select_regression_posk_0(float %a) #0 {85 %fneg.a = fsub float -0.0, %a86 %cmp.a = fcmp ugt float %a, -1.087 %min.a = select i1 %cmp.a, float %fneg.a, float 1.088 ret float %min.a89}90 91; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0_fast:92; GCN-NOT: v_mul93 94; GCN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, 1.095define amdgpu_ps float @max_fneg_select_regression_posk_0_fast(float %a) #0 {96 %fneg.a = fsub float -0.0, %a97 %cmp.a = fcmp ugt float %a, -1.098 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.099 ret float %min.a100}101 102; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg1:103; SI: v_min_legacy_f32_e64 v0, 1.0, -v0104 105; VI: v_cmp_nge_f32_e32 vcc, -1.0, v0106; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc107define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg1(float %a, float %b) #0 {108 %fneg.a = fneg float %a109 %cmp.a = fcmp ugt float %a, -1.0110 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0111 ret float %min.a112}113 114; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg1_fast:115 116; VI: v_min_f32_e64 v0, -v0, 1.0117define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg1_fast(float %a, float %b) #0 {118 %fneg.a = fneg float %a119 %cmp.a = fcmp ugt float %a, -1.0120 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0121 ret float %min.a122}123 124; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg1:125; SI: v_max_legacy_f32_e64 v0, 1.0, -v0126 127; VI: v_cmp_nle_f32_e32 vcc, -1.0, v0128; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc129define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg1(float %a, float %b) #0 {130 %fneg.a = fneg float %a131 %cmp.a = fcmp ult float %a, -1.0132 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0133 ret float %min.a134}135 136; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg1_fast:137 138; VI: v_max_f32_e64 v0, -v0, 1.0139define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg1_fast(float %a, float %b) #0 {140 %fneg.a = fneg float %a141 %cmp.a = fcmp ult float %a, -1.0142 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0143 ret float %min.a144}145 146; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg1:147; SI: v_min_legacy_f32_e64 v0, -v0, 1.0148 149; VI: v_cmp_lt_f32_e32 vcc, -1.0, v0150; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc151define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg1(float %a, float %b) #0 {152 %fneg.a = fneg float %a153 %cmp.a = fcmp ogt float %a, -1.0154 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0155 ret float %min.a156}157 158; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg1_fast:159 160; VI: v_min_f32_e64 v0, -v0, 1.0161define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg1_fast(float %a, float %b) #0 {162 %fneg.a = fneg float %a163 %cmp.a = fcmp ogt float %a, -1.0164 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0165 ret float %min.a166}167 168; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg1:169; SI: v_max_legacy_f32_e64 v0, -v0, 1.0170 171; VI: v_cmp_gt_f32_e32 vcc, -1.0, v0172; VI-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc173define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1(float %a, float %b) #0 {174 %fneg.a = fneg float %a175 %cmp.a = fcmp olt float %a, -1.0176 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0177 ret float %min.a178}179 180; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg1_fast:181 182; VI-NANN: v_max_f32_e64 v0, -v0, 1.0183define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1_fast(float %a, float %b) #0 {184 %fneg.a = fneg float %a185 %cmp.a = fcmp olt float %a, -1.0186 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 1.0187 ret float %min.a188}189 190; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg8:191; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000192; SI-NEXT: v_min_legacy_f32_e64 v0, [[K]], -v0193 194; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000195; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000196; VI: v_cmp_nge_f32_e32 vcc, [[K0]], v0197; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc198define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg8(float %a, float %b) #0 {199 %fneg.a = fneg float %a200 %cmp.a = fcmp ugt float %a, -8.0201 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0202 ret float %min.a203}204 205; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg8_fast:206 207; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000208; VI-NEXT: v_min_f32_e64 v0, -v0, [[K]]209define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg8_fast(float %a, float %b) #0 {210 %fneg.a = fneg float %a211 %cmp.a = fcmp ugt float %a, -8.0212 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0213 ret float %min.a214}215 216; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg8:217; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000218; SI-NEXT: v_max_legacy_f32_e64 v0, [[K]], -v0219 220; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000221; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000222; VI: v_cmp_nle_f32_e32 vcc, [[K0]], v0223; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc224define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg8(float %a, float %b) #0 {225 %fneg.a = fneg float %a226 %cmp.a = fcmp ult float %a, -8.0227 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0228 ret float %min.a229}230 231; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg8_fast:232 233; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000234; VI-NEXT: v_max_f32_e64 v0, -v0, [[K]]235define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg8_fast(float %a, float %b) #0 {236 %fneg.a = fneg float %a237 %cmp.a = fcmp ult float %a, -8.0238 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0239 ret float %min.a240}241 242; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg8:243; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000244; SI-NEXT: v_min_legacy_f32_e64 v0, -v0, [[K]]245 246; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000247; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000248; VI: v_cmp_lt_f32_e32 vcc, [[K0]], v0249; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc250define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg8(float %a, float %b) #0 {251 %fneg.a = fneg float %a252 %cmp.a = fcmp ogt float %a, -8.0253 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0254 ret float %min.a255}256 257; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg8_fast:258 259; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000260; VI-NEXT: v_min_f32_e64 v0, -v0, [[K]]261define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg8_fast(float %a, float %b) #0 {262 %fneg.a = fneg float %a263 %cmp.a = fcmp ogt float %a, -8.0264 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0265 ret float %min.a266}267 268; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg8:269; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000270; SI-NEXT: v_max_legacy_f32_e64 v0, -v0, [[K]]271 272 273; VI-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000274; VI-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000275; VI: v_cmp_gt_f32_e32 vcc, [[K0]], v0276; VI-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc277define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg8(float %a, float %b) #0 {278 %fneg.a = fneg float %a279 %cmp.a = fcmp olt float %a, -8.0280 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0281 ret float %min.a282}283 284; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg8_fast:285 286; VI: s_mov_b32 [[K:s[0-9]+]], 0x41000000287; VI-NEXT: v_max_f32_e64 v0, -v0, [[K]]288define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg8_fast(float %a, float %b) #0 {289 %fneg.a = fneg float %a290 %cmp.a = fcmp olt float %a, -8.0291 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float 8.0292 ret float %min.a293}294 295; GCN-LABEL: {{^}}select_fneg_a_or_neg1_cmp_olt_a_1:296; SI: v_max_legacy_f32_e64 v0, -v0, -1.0297 298; VI: v_cmp_gt_f32_e32 vcc, 1.0, v0299; VI-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc300define amdgpu_ps float @select_fneg_a_or_neg1_cmp_olt_a_1(float %a, float %b) #0 {301 %fneg.a = fneg float %a302 %cmp.a = fcmp olt float %a, 1.0303 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0304 ret float %min.a305}306 307; GCN-LABEL: {{^}}select_fneg_a_or_neg1_cmp_olt_a_1_fast:308 309; VI: v_max_f32_e64 v0, -v0, -1.0310define amdgpu_ps float @select_fneg_a_or_neg1_cmp_olt_a_1_fast(float %a, float %b) #0 {311 %fneg.a = fneg float %a312 %cmp.a = fcmp olt float %a, 1.0313 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float -1.0314 ret float %min.a315}316 317; GCN-LABEL: {{^}}ult_a_select_fneg_a_b:318; SI: v_cmp_nge_f32_e32 vcc, v0, v1319; SI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc320 321; VI: v_cmp_nge_f32_e32 vcc, v0, v1322; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc323define amdgpu_ps float @ult_a_select_fneg_a_b(float %a, float %b) #0 {324 %fneg.a = fneg float %a325 %cmp.a = fcmp ult float %a, %b326 %min.a = select i1 %cmp.a, float %fneg.a, float %b327 ret float %min.a328}329 330; GCN-LABEL: {{^}}ult_a_select_fneg_a_b_fast:331 332; VI: v_cmp_lt_f32_e32 vcc, v0, v1333; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc334define amdgpu_ps float @ult_a_select_fneg_a_b_fast(float %a, float %b) #0 {335 %fneg.a = fneg float %a336 %cmp.a = fcmp nnan nsz ult float %a, %b337 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float %b338 ret float %min.a339}340 341; GCN-LABEL: {{^}}ugt_a_select_fneg_a_b:342; SI: v_cmp_nle_f32_e32 vcc, v0, v1343; SI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc344 345; VI: v_cmp_nle_f32_e32 vcc, v0, v1346; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc347define amdgpu_ps float @ugt_a_select_fneg_a_b(float %a, float %b) #0 {348 %fneg.a = fneg float %a349 %cmp.a = fcmp ugt float %a, %b350 %min.a = select i1 %cmp.a, float %fneg.a, float %b351 ret float %min.a352}353 354; GCN-LABEL: {{^}}ugt_a_select_fneg_a_b_fast:355 356; VI: v_cmp_gt_f32_e32 vcc, v0, v1357; VI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc358define amdgpu_ps float @ugt_a_select_fneg_a_b_fast(float %a, float %b) #0 {359 %fneg.a = fneg float %a360 %cmp.a = fcmp nnan nsz ugt float %a, %b361 %min.a = select nnan nsz i1 %cmp.a, float %fneg.a, float %b362 ret float %min.a363}364 365attributes #0 = { nounwind }366attributes #1 = { nounwind readnone }367