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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s3 4; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI %s5 6; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI %s7 8; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s9; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s10 11 12define half @test_fmin_legacy_ule_f16(half %a, half %b) #0 {13; GFX9-LABEL: test_fmin_legacy_ule_f16:14; GFX9: ; %bb.0:15; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v117; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc18; GFX9-NEXT: s_setpc_b64 s[30:31]19;20; VI-LABEL: test_fmin_legacy_ule_f16:21; VI: ; %bb.0:22; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v124; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc25; VI-NEXT: s_setpc_b64 s[30:31]26;27; SI-LABEL: test_fmin_legacy_ule_f16:28; SI: ; %bb.0:29; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)30; SI-NEXT: v_cvt_f16_f32_e32 v0, v031; SI-NEXT: v_cvt_f16_f32_e32 v1, v132; SI-NEXT: v_cvt_f32_f16_e32 v0, v033; SI-NEXT: v_cvt_f32_f16_e32 v1, v134; SI-NEXT: v_min_legacy_f32_e32 v0, v1, v035; SI-NEXT: s_setpc_b64 s[30:31]36;37; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_f16:38; GFX11-TRUE16: ; %bb.0:39; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l41; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo42; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]43;44; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_f16:45; GFX11-FAKE16: ; %bb.0:46; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)47; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v148; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo49; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]50 %cmp = fcmp ule half %a, %b51 %val = select i1 %cmp, half %a, half %b52 ret half %val53}54 55define half @test_fmin_legacy_ule_f16_fast(half %a, half %b) #0 {56; GFX9-LABEL: test_fmin_legacy_ule_f16_fast:57; GFX9: ; %bb.0:58; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)59; GFX9-NEXT: v_min_f16_e32 v0, v0, v160; GFX9-NEXT: s_setpc_b64 s[30:31]61;62; VI-LABEL: test_fmin_legacy_ule_f16_fast:63; VI: ; %bb.0:64; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)65; VI-NEXT: v_min_f16_e32 v0, v0, v166; VI-NEXT: s_setpc_b64 s[30:31]67;68; SI-LABEL: test_fmin_legacy_ule_f16_fast:69; SI: ; %bb.0:70; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)71; SI-NEXT: v_cvt_f16_f32_e32 v1, v172; SI-NEXT: v_cvt_f16_f32_e32 v0, v073; SI-NEXT: v_cvt_f32_f16_e32 v1, v174; SI-NEXT: v_cvt_f32_f16_e32 v0, v075; SI-NEXT: v_min_f32_e32 v0, v0, v176; SI-NEXT: s_setpc_b64 s[30:31]77;78; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_f16_fast:79; GFX11-TRUE16: ; %bb.0:80; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)81; GFX11-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l82; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]83;84; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_f16_fast:85; GFX11-FAKE16: ; %bb.0:86; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; GFX11-FAKE16-NEXT: v_min_f16_e32 v0, v0, v188; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]89 %cmp = fcmp ule half %a, %b90 %val = select nnan nsz i1 %cmp, half %a, half %b91 ret half %val92}93 94define <2 x half> @test_fmin_legacy_ule_v2f16(<2 x half> %a, <2 x half> %b) #0 {95; GFX9-LABEL: test_fmin_legacy_ule_v2f16:96; GFX9: ; %bb.0:97; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v199; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0100; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v2101; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc102; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1103; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc104; GFX9-NEXT: s_mov_b32 s4, 0x5040100105; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4106; GFX9-NEXT: s_setpc_b64 s[30:31]107;108; VI-LABEL: test_fmin_legacy_ule_v2f16:109; VI: ; %bb.0:110; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)111; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1112; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0113; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v2114; VI-NEXT: v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD115; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1116; VI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc117; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD118; VI-NEXT: s_setpc_b64 s[30:31]119;120; SI-LABEL: test_fmin_legacy_ule_v2f16:121; SI: ; %bb.0:122; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)123; SI-NEXT: v_cvt_f16_f32_e32 v1, v1124; SI-NEXT: v_cvt_f16_f32_e32 v3, v3125; SI-NEXT: v_cvt_f16_f32_e32 v0, v0126; SI-NEXT: v_cvt_f16_f32_e32 v2, v2127; SI-NEXT: v_cvt_f32_f16_e32 v1, v1128; SI-NEXT: v_cvt_f32_f16_e32 v3, v3129; SI-NEXT: v_cvt_f32_f16_e32 v0, v0130; SI-NEXT: v_cvt_f32_f16_e32 v2, v2131; SI-NEXT: v_min_legacy_f32_e32 v0, v2, v0132; SI-NEXT: v_min_legacy_f32_e32 v1, v3, v1133; SI-NEXT: s_setpc_b64 s[30:31]134;135; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v2f16:136; GFX11-TRUE16: ; %bb.0:137; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)138; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h139; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l140; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo141; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)142; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0143; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]144;145; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v2f16:146; GFX11-FAKE16: ; %bb.0:147; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)148; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1149; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0150; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)151; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2152; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo153; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1154; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo155; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100156; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]157 %cmp = fcmp ule <2 x half> %a, %b158 %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b159 ret <2 x half> %val160}161 162define <2 x half> @test_fmin_legacy_ule_v2f16_fast(<2 x half> %a, <2 x half> %b) #0 {163; GFX9-LABEL: test_fmin_legacy_ule_v2f16_fast:164; GFX9: ; %bb.0:165; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)166; GFX9-NEXT: v_pk_min_f16 v0, v0, v1167; GFX9-NEXT: s_setpc_b64 s[30:31]168;169; VI-LABEL: test_fmin_legacy_ule_v2f16_fast:170; VI: ; %bb.0:171; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)172; VI-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1173; VI-NEXT: v_min_f16_e32 v0, v0, v1174; VI-NEXT: v_or_b32_e32 v0, v0, v2175; VI-NEXT: s_setpc_b64 s[30:31]176;177; SI-LABEL: test_fmin_legacy_ule_v2f16_fast:178; SI: ; %bb.0:179; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)180; SI-NEXT: v_cvt_f16_f32_e32 v3, v3181; SI-NEXT: v_cvt_f16_f32_e32 v1, v1182; SI-NEXT: v_cvt_f16_f32_e32 v2, v2183; SI-NEXT: v_cvt_f16_f32_e32 v0, v0184; SI-NEXT: v_cvt_f32_f16_e32 v3, v3185; SI-NEXT: v_cvt_f32_f16_e32 v1, v1186; SI-NEXT: v_cvt_f32_f16_e32 v2, v2187; SI-NEXT: v_cvt_f32_f16_e32 v0, v0188; SI-NEXT: v_min_f32_e32 v0, v0, v2189; SI-NEXT: v_min_f32_e32 v1, v1, v3190; SI-NEXT: s_setpc_b64 s[30:31]191;192; GFX11-LABEL: test_fmin_legacy_ule_v2f16_fast:193; GFX11: ; %bb.0:194; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)195; GFX11-NEXT: v_pk_min_f16 v0, v0, v1196; GFX11-NEXT: s_setpc_b64 s[30:31]197 %cmp = fcmp ule <2 x half> %a, %b198 %val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b199 ret <2 x half> %val200}201 202define <3 x half> @test_fmin_legacy_ule_v3f16(<3 x half> %a, <3 x half> %b) #0 {203; GFX9-LABEL: test_fmin_legacy_ule_v3f16:204; GFX9: ; %bb.0:205; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)206; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2207; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0208; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4209; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc210; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3211; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc212; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2213; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc214; GFX9-NEXT: s_mov_b32 s4, 0x5040100215; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4216; GFX9-NEXT: s_setpc_b64 s[30:31]217;218; VI-LABEL: test_fmin_legacy_ule_v3f16:219; VI: ; %bb.0:220; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)221; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2222; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0223; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4224; VI-NEXT: v_cndmask_b32_sdwa v4, v4, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD225; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3226; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc227; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2228; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc229; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD230; VI-NEXT: s_setpc_b64 s[30:31]231;232; SI-LABEL: test_fmin_legacy_ule_v3f16:233; SI: ; %bb.0:234; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)235; SI-NEXT: v_cvt_f16_f32_e32 v2, v2236; SI-NEXT: v_cvt_f16_f32_e32 v5, v5237; SI-NEXT: v_cvt_f16_f32_e32 v1, v1238; SI-NEXT: v_cvt_f16_f32_e32 v4, v4239; SI-NEXT: v_cvt_f16_f32_e32 v0, v0240; SI-NEXT: v_cvt_f16_f32_e32 v3, v3241; SI-NEXT: v_cvt_f32_f16_e32 v2, v2242; SI-NEXT: v_cvt_f32_f16_e32 v5, v5243; SI-NEXT: v_cvt_f32_f16_e32 v1, v1244; SI-NEXT: v_cvt_f32_f16_e32 v4, v4245; SI-NEXT: v_cvt_f32_f16_e32 v0, v0246; SI-NEXT: v_cvt_f32_f16_e32 v3, v3247; SI-NEXT: v_min_legacy_f32_e32 v0, v3, v0248; SI-NEXT: v_min_legacy_f32_e32 v1, v4, v1249; SI-NEXT: v_min_legacy_f32_e32 v2, v5, v2250; SI-NEXT: s_setpc_b64 s[30:31]251;252; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v3f16:253; GFX11-TRUE16: ; %bb.0:254; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)255; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v2.h256; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l257; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v1.l, v3.l258; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo259; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)260; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0261; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1262; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]263;264; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v3f16:265; GFX11-FAKE16: ; %bb.0:266; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)267; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2268; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0269; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2270; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo271; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)272; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4273; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo274; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3275; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo276; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100277; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]278 %cmp = fcmp ule <3 x half> %a, %b279 %val = select <3 x i1> %cmp, <3 x half> %a, <3 x half> %b280 ret <3 x half> %val281}282 283define <3 x half> @test_fmin_legacy_ule_v3f16_fast(<3 x half> %a, <3 x half> %b) #0 {284; GFX9-LABEL: test_fmin_legacy_ule_v3f16_fast:285; GFX9: ; %bb.0:286; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)287; GFX9-NEXT: v_pk_max_f16 v3, v3, v3288; GFX9-NEXT: v_pk_max_f16 v1, v1, v1289; GFX9-NEXT: v_pk_min_f16 v1, v1, v3290; GFX9-NEXT: v_pk_min_f16 v0, v0, v2291; GFX9-NEXT: s_setpc_b64 s[30:31]292;293; VI-LABEL: test_fmin_legacy_ule_v3f16_fast:294; VI: ; %bb.0:295; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)296; VI-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1297; VI-NEXT: v_min_f16_e32 v0, v0, v2298; VI-NEXT: v_min_f16_e32 v1, v1, v3299; VI-NEXT: v_or_b32_e32 v0, v0, v4300; VI-NEXT: s_setpc_b64 s[30:31]301;302; SI-LABEL: test_fmin_legacy_ule_v3f16_fast:303; SI: ; %bb.0:304; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)305; SI-NEXT: v_cvt_f16_f32_e32 v5, v5306; SI-NEXT: v_cvt_f16_f32_e32 v2, v2307; SI-NEXT: v_cvt_f16_f32_e32 v4, v4308; SI-NEXT: v_cvt_f16_f32_e32 v1, v1309; SI-NEXT: v_cvt_f16_f32_e32 v3, v3310; SI-NEXT: v_cvt_f16_f32_e32 v0, v0311; SI-NEXT: v_cvt_f32_f16_e32 v5, v5312; SI-NEXT: v_cvt_f32_f16_e32 v2, v2313; SI-NEXT: v_cvt_f32_f16_e32 v4, v4314; SI-NEXT: v_cvt_f32_f16_e32 v1, v1315; SI-NEXT: v_cvt_f32_f16_e32 v3, v3316; SI-NEXT: v_cvt_f32_f16_e32 v0, v0317; SI-NEXT: v_min_f32_e32 v0, v0, v3318; SI-NEXT: v_min_f32_e32 v1, v1, v4319; SI-NEXT: v_min_f32_e32 v2, v2, v5320; SI-NEXT: s_setpc_b64 s[30:31]321;322; GFX11-LABEL: test_fmin_legacy_ule_v3f16_fast:323; GFX11: ; %bb.0:324; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)325; GFX11-NEXT: v_pk_max_f16 v3, v3, v3326; GFX11-NEXT: v_pk_max_f16 v1, v1, v1327; GFX11-NEXT: v_pk_min_f16 v0, v0, v2328; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)329; GFX11-NEXT: v_pk_min_f16 v1, v1, v3330; GFX11-NEXT: s_setpc_b64 s[30:31]331 %cmp = fcmp ule <3 x half> %a, %b332 %val = select nnan nsz <3 x i1> %cmp, <3 x half> %a, <3 x half> %b333 ret <3 x half> %val334}335 336define <4 x half> @test_fmin_legacy_ule_v4f16(<4 x half> %a, <4 x half> %b) #0 {337; GFX9-LABEL: test_fmin_legacy_ule_v4f16:338; GFX9: ; %bb.0:339; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)340; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3341; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v1342; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2343; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0344; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v7, v6345; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc346; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4347; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc348; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3349; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc350; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2351; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc352; GFX9-NEXT: s_mov_b32 s4, 0x5040100353; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4354; GFX9-NEXT: v_perm_b32 v1, v6, v1, s4355; GFX9-NEXT: s_setpc_b64 s[30:31]356;357; VI-LABEL: test_fmin_legacy_ule_v4f16:358; VI: ; %bb.0:359; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)360; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3361; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v1362; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2363; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0364; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v7, v6365; VI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc366; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4367; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc368; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3369; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc370; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2371; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc372; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v4373; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD374; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6375; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD376; VI-NEXT: s_setpc_b64 s[30:31]377;378; SI-LABEL: test_fmin_legacy_ule_v4f16:379; SI: ; %bb.0:380; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)381; SI-NEXT: v_cvt_f16_f32_e32 v3, v3382; SI-NEXT: v_cvt_f16_f32_e32 v7, v7383; SI-NEXT: v_cvt_f16_f32_e32 v2, v2384; SI-NEXT: v_cvt_f16_f32_e32 v6, v6385; SI-NEXT: v_cvt_f16_f32_e32 v1, v1386; SI-NEXT: v_cvt_f16_f32_e32 v5, v5387; SI-NEXT: v_cvt_f16_f32_e32 v0, v0388; SI-NEXT: v_cvt_f16_f32_e32 v4, v4389; SI-NEXT: v_cvt_f32_f16_e32 v3, v3390; SI-NEXT: v_cvt_f32_f16_e32 v7, v7391; SI-NEXT: v_cvt_f32_f16_e32 v2, v2392; SI-NEXT: v_cvt_f32_f16_e32 v6, v6393; SI-NEXT: v_cvt_f32_f16_e32 v1, v1394; SI-NEXT: v_cvt_f32_f16_e32 v5, v5395; SI-NEXT: v_cvt_f32_f16_e32 v0, v0396; SI-NEXT: v_cvt_f32_f16_e32 v4, v4397; SI-NEXT: v_min_legacy_f32_e32 v0, v4, v0398; SI-NEXT: v_min_legacy_f32_e32 v1, v5, v1399; SI-NEXT: v_min_legacy_f32_e32 v2, v6, v2400; SI-NEXT: v_min_legacy_f32_e32 v3, v7, v3401; SI-NEXT: s_setpc_b64 s[30:31]402;403; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v4f16:404; GFX11-TRUE16: ; %bb.0:405; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)406; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h407; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h408; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l409; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l410; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo411; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)412; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0413; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1414; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)415; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2416; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]417;418; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v4f16:419; GFX11-FAKE16: ; %bb.0:420; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)421; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3422; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1423; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2424; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0425; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)426; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4427; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo428; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v7, v6429; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo430; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2431; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo432; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3433; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo434; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)435; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100436; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100437; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]438 %cmp = fcmp ule <4 x half> %a, %b439 %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b440 ret <4 x half> %val441}442 443define <4 x half> @test_fmin_legacy_ule_v4f16_fast(<4 x half> %a, <4 x half> %b) #0 {444; GFX9-LABEL: test_fmin_legacy_ule_v4f16_fast:445; GFX9: ; %bb.0:446; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)447; GFX9-NEXT: v_pk_min_f16 v0, v0, v2448; GFX9-NEXT: v_pk_min_f16 v1, v1, v3449; GFX9-NEXT: s_setpc_b64 s[30:31]450;451; VI-LABEL: test_fmin_legacy_ule_v4f16_fast:452; VI: ; %bb.0:453; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)454; VI-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1455; VI-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1456; VI-NEXT: v_min_f16_e32 v1, v1, v3457; VI-NEXT: v_min_f16_e32 v0, v0, v2458; VI-NEXT: v_or_b32_e32 v0, v0, v5459; VI-NEXT: v_or_b32_e32 v1, v1, v4460; VI-NEXT: s_setpc_b64 s[30:31]461;462; SI-LABEL: test_fmin_legacy_ule_v4f16_fast:463; SI: ; %bb.0:464; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)465; SI-NEXT: v_cvt_f16_f32_e32 v7, v7466; SI-NEXT: v_cvt_f16_f32_e32 v3, v3467; SI-NEXT: v_cvt_f16_f32_e32 v6, v6468; SI-NEXT: v_cvt_f16_f32_e32 v2, v2469; SI-NEXT: v_cvt_f16_f32_e32 v5, v5470; SI-NEXT: v_cvt_f16_f32_e32 v1, v1471; SI-NEXT: v_cvt_f16_f32_e32 v4, v4472; SI-NEXT: v_cvt_f16_f32_e32 v0, v0473; SI-NEXT: v_cvt_f32_f16_e32 v7, v7474; SI-NEXT: v_cvt_f32_f16_e32 v3, v3475; SI-NEXT: v_cvt_f32_f16_e32 v6, v6476; SI-NEXT: v_cvt_f32_f16_e32 v2, v2477; SI-NEXT: v_cvt_f32_f16_e32 v5, v5478; SI-NEXT: v_cvt_f32_f16_e32 v1, v1479; SI-NEXT: v_cvt_f32_f16_e32 v4, v4480; SI-NEXT: v_cvt_f32_f16_e32 v0, v0481; SI-NEXT: v_min_f32_e32 v0, v0, v4482; SI-NEXT: v_min_f32_e32 v1, v1, v5483; SI-NEXT: v_min_f32_e32 v2, v2, v6484; SI-NEXT: v_min_f32_e32 v3, v3, v7485; SI-NEXT: s_setpc_b64 s[30:31]486;487; GFX11-LABEL: test_fmin_legacy_ule_v4f16_fast:488; GFX11: ; %bb.0:489; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)490; GFX11-NEXT: v_pk_min_f16 v0, v0, v2491; GFX11-NEXT: v_pk_min_f16 v1, v1, v3492; GFX11-NEXT: s_setpc_b64 s[30:31]493 %cmp = fcmp ule <4 x half> %a, %b494 %val = select nnan nsz <4 x i1> %cmp, <4 x half> %a, <4 x half> %b495 ret <4 x half> %val496}497 498define <8 x half> @test_fmin_legacy_ule_v8f16(<8 x half> %a, <8 x half> %b) #0 {499; GFX9-LABEL: test_fmin_legacy_ule_v8f16:500; GFX9: ; %bb.0:501; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)502; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7503; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v3504; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v6505; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v2506; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v15, v14507; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5508; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v1509; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc510; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v13, v12511; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v4512; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v0513; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc514; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v11, v10515; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc516; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v9, v8517; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc518; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v7519; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc520; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v2, v6521; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc522; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v5523; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc524; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v4525; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc526; GFX9-NEXT: s_mov_b32 s4, 0x5040100527; GFX9-NEXT: v_perm_b32 v0, v8, v0, s4528; GFX9-NEXT: v_perm_b32 v1, v10, v1, s4529; GFX9-NEXT: v_perm_b32 v2, v12, v2, s4530; GFX9-NEXT: v_perm_b32 v3, v14, v3, s4531; GFX9-NEXT: s_setpc_b64 s[30:31]532;533; VI-LABEL: test_fmin_legacy_ule_v8f16:534; VI: ; %bb.0:535; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)536; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v7537; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v3538; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v6539; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v2540; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v15, v14541; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v5542; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v1543; VI-NEXT: v_cndmask_b32_e32 v14, v14, v15, vcc544; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v13, v12545; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v4546; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0547; VI-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc548; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v11, v10549; VI-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc550; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v9, v8551; VI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc552; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v7553; VI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc554; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v2, v6555; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc556; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v5557; VI-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc558; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v4559; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc560; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v8561; VI-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD562; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v10563; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD564; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v12565; VI-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD566; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14567; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD568; VI-NEXT: s_setpc_b64 s[30:31]569;570; SI-LABEL: test_fmin_legacy_ule_v8f16:571; SI: ; %bb.0:572; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)573; SI-NEXT: v_cvt_f16_f32_e32 v7, v7574; SI-NEXT: v_cvt_f16_f32_e32 v15, v15575; SI-NEXT: v_cvt_f16_f32_e32 v6, v6576; SI-NEXT: v_cvt_f16_f32_e32 v14, v14577; SI-NEXT: v_cvt_f16_f32_e32 v5, v5578; SI-NEXT: v_cvt_f16_f32_e32 v13, v13579; SI-NEXT: v_cvt_f16_f32_e32 v4, v4580; SI-NEXT: v_cvt_f16_f32_e32 v12, v12581; SI-NEXT: v_cvt_f16_f32_e32 v3, v3582; SI-NEXT: v_cvt_f16_f32_e32 v11, v11583; SI-NEXT: v_cvt_f16_f32_e32 v2, v2584; SI-NEXT: v_cvt_f16_f32_e32 v10, v10585; SI-NEXT: v_cvt_f16_f32_e32 v1, v1586; SI-NEXT: v_cvt_f16_f32_e32 v9, v9587; SI-NEXT: v_cvt_f16_f32_e32 v0, v0588; SI-NEXT: v_cvt_f16_f32_e32 v8, v8589; SI-NEXT: v_cvt_f32_f16_e32 v7, v7590; SI-NEXT: v_cvt_f32_f16_e32 v15, v15591; SI-NEXT: v_cvt_f32_f16_e32 v6, v6592; SI-NEXT: v_cvt_f32_f16_e32 v14, v14593; SI-NEXT: v_cvt_f32_f16_e32 v5, v5594; SI-NEXT: v_cvt_f32_f16_e32 v13, v13595; SI-NEXT: v_cvt_f32_f16_e32 v4, v4596; SI-NEXT: v_cvt_f32_f16_e32 v12, v12597; SI-NEXT: v_cvt_f32_f16_e32 v3, v3598; SI-NEXT: v_cvt_f32_f16_e32 v11, v11599; SI-NEXT: v_cvt_f32_f16_e32 v2, v2600; SI-NEXT: v_cvt_f32_f16_e32 v10, v10601; SI-NEXT: v_cvt_f32_f16_e32 v1, v1602; SI-NEXT: v_cvt_f32_f16_e32 v9, v9603; SI-NEXT: v_cvt_f32_f16_e32 v0, v0604; SI-NEXT: v_cvt_f32_f16_e32 v8, v8605; SI-NEXT: v_min_legacy_f32_e32 v0, v8, v0606; SI-NEXT: v_min_legacy_f32_e32 v1, v9, v1607; SI-NEXT: v_min_legacy_f32_e32 v2, v10, v2608; SI-NEXT: v_min_legacy_f32_e32 v3, v11, v3609; SI-NEXT: v_min_legacy_f32_e32 v4, v12, v4610; SI-NEXT: v_min_legacy_f32_e32 v5, v13, v5611; SI-NEXT: v_min_legacy_f32_e32 v6, v14, v6612; SI-NEXT: v_min_legacy_f32_e32 v7, v15, v7613; SI-NEXT: s_setpc_b64 s[30:31]614;615; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v8f16:616; GFX11-TRUE16: ; %bb.0:617; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)618; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v4.h619; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v1.h, v5.h620; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v2.h, v6.h621; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v3.h, v7.h622; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s3, v0.l, v4.l623; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s4, v1.l, v5.l624; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s5, v2.l, v6.l625; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s6, v3.l, v7.l626; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2627; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s1628; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0629; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, vcc_lo630; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3631; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4632; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5633; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6634; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]635;636; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v8f16:637; GFX11-FAKE16: ; %bb.0:638; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)639; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v7640; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v3641; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6642; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2643; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v5644; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1645; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v11, v10646; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4647; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0648; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo649; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v13, v12650; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc_lo651; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v15, v14652; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo653; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v9, v8654; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo655; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v2, v6656; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo657; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v4658; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)659; GFX11-FAKE16-NEXT: v_perm_b32 v2, v11, v2, 0x5040100660; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo661; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v5662; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo663; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v7664; GFX11-FAKE16-NEXT: v_perm_b32 v1, v12, v1, 0x5040100665; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo666; GFX11-FAKE16-NEXT: v_perm_b32 v0, v8, v0, 0x5040100667; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)668; GFX11-FAKE16-NEXT: v_perm_b32 v3, v10, v3, 0x5040100669; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]670 %cmp = fcmp ule <8 x half> %a, %b671 %val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b672 ret <8 x half> %val673}674 675define <8 x half> @test_fmin_legacy_ule_v8f16_fast(<8 x half> %a, <8 x half> %b) #0 {676; GFX9-LABEL: test_fmin_legacy_ule_v8f16_fast:677; GFX9: ; %bb.0:678; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)679; GFX9-NEXT: v_pk_min_f16 v0, v0, v4680; GFX9-NEXT: v_pk_min_f16 v1, v1, v5681; GFX9-NEXT: v_pk_min_f16 v2, v2, v6682; GFX9-NEXT: v_pk_min_f16 v3, v3, v7683; GFX9-NEXT: s_setpc_b64 s[30:31]684;685; VI-LABEL: test_fmin_legacy_ule_v8f16_fast:686; VI: ; %bb.0:687; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)688; VI-NEXT: v_min_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1689; VI-NEXT: v_min_f16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1690; VI-NEXT: v_min_f16_sdwa v10, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1691; VI-NEXT: v_min_f16_sdwa v11, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1692; VI-NEXT: v_min_f16_e32 v3, v3, v7693; VI-NEXT: v_min_f16_e32 v2, v2, v6694; VI-NEXT: v_min_f16_e32 v1, v1, v5695; VI-NEXT: v_min_f16_e32 v0, v0, v4696; VI-NEXT: v_or_b32_e32 v0, v0, v11697; VI-NEXT: v_or_b32_e32 v1, v1, v10698; VI-NEXT: v_or_b32_e32 v2, v2, v9699; VI-NEXT: v_or_b32_e32 v3, v3, v8700; VI-NEXT: s_setpc_b64 s[30:31]701;702; SI-LABEL: test_fmin_legacy_ule_v8f16_fast:703; SI: ; %bb.0:704; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)705; SI-NEXT: v_cvt_f16_f32_e32 v15, v15706; SI-NEXT: v_cvt_f16_f32_e32 v7, v7707; SI-NEXT: v_cvt_f16_f32_e32 v14, v14708; SI-NEXT: v_cvt_f16_f32_e32 v6, v6709; SI-NEXT: v_cvt_f16_f32_e32 v13, v13710; SI-NEXT: v_cvt_f16_f32_e32 v5, v5711; SI-NEXT: v_cvt_f16_f32_e32 v12, v12712; SI-NEXT: v_cvt_f16_f32_e32 v4, v4713; SI-NEXT: v_cvt_f16_f32_e32 v11, v11714; SI-NEXT: v_cvt_f16_f32_e32 v3, v3715; SI-NEXT: v_cvt_f16_f32_e32 v10, v10716; SI-NEXT: v_cvt_f16_f32_e32 v2, v2717; SI-NEXT: v_cvt_f16_f32_e32 v9, v9718; SI-NEXT: v_cvt_f16_f32_e32 v1, v1719; SI-NEXT: v_cvt_f16_f32_e32 v8, v8720; SI-NEXT: v_cvt_f16_f32_e32 v0, v0721; SI-NEXT: v_cvt_f32_f16_e32 v15, v15722; SI-NEXT: v_cvt_f32_f16_e32 v7, v7723; SI-NEXT: v_cvt_f32_f16_e32 v14, v14724; SI-NEXT: v_cvt_f32_f16_e32 v6, v6725; SI-NEXT: v_cvt_f32_f16_e32 v13, v13726; SI-NEXT: v_cvt_f32_f16_e32 v5, v5727; SI-NEXT: v_cvt_f32_f16_e32 v12, v12728; SI-NEXT: v_cvt_f32_f16_e32 v4, v4729; SI-NEXT: v_cvt_f32_f16_e32 v11, v11730; SI-NEXT: v_cvt_f32_f16_e32 v3, v3731; SI-NEXT: v_cvt_f32_f16_e32 v10, v10732; SI-NEXT: v_cvt_f32_f16_e32 v2, v2733; SI-NEXT: v_cvt_f32_f16_e32 v9, v9734; SI-NEXT: v_cvt_f32_f16_e32 v1, v1735; SI-NEXT: v_cvt_f32_f16_e32 v8, v8736; SI-NEXT: v_cvt_f32_f16_e32 v0, v0737; SI-NEXT: v_min_f32_e32 v0, v0, v8738; SI-NEXT: v_min_f32_e32 v1, v1, v9739; SI-NEXT: v_min_f32_e32 v2, v2, v10740; SI-NEXT: v_min_f32_e32 v3, v3, v11741; SI-NEXT: v_min_f32_e32 v4, v4, v12742; SI-NEXT: v_min_f32_e32 v5, v5, v13743; SI-NEXT: v_min_f32_e32 v6, v6, v14744; SI-NEXT: v_min_f32_e32 v7, v7, v15745; SI-NEXT: s_setpc_b64 s[30:31]746;747; GFX11-LABEL: test_fmin_legacy_ule_v8f16_fast:748; GFX11: ; %bb.0:749; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)750; GFX11-NEXT: v_pk_min_f16 v0, v0, v4751; GFX11-NEXT: v_pk_min_f16 v1, v1, v5752; GFX11-NEXT: v_pk_min_f16 v2, v2, v6753; GFX11-NEXT: v_pk_min_f16 v3, v3, v7754; GFX11-NEXT: s_setpc_b64 s[30:31]755 %cmp = fcmp ule <8 x half> %a, %b756 %val = select nnan nsz <8 x i1> %cmp, <8 x half> %a, <8 x half> %b757 ret <8 x half> %val758}759 760attributes #0 = { nounwind }761