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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -check-prefix=VI %s4 5define amdgpu_kernel void @test_fmin_legacy_uge_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {6; SI-LABEL: test_fmin_legacy_uge_f64:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x99; SI-NEXT: s_mov_b32 s7, 0xf00010; SI-NEXT: s_mov_b32 s10, 011; SI-NEXT: s_mov_b32 s11, s712; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v013; SI-NEXT: s_waitcnt lgkmcnt(0)14; SI-NEXT: s_mov_b64 s[8:9], s[2:3]15; SI-NEXT: v_mov_b32_e32 v1, 016; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr6417; SI-NEXT: s_mov_b32 s6, -118; SI-NEXT: s_mov_b32 s4, s019; SI-NEXT: s_mov_b32 s5, s120; SI-NEXT: s_waitcnt vmcnt(0)21; SI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]22; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc23; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc24; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 025; SI-NEXT: s_endpgm26;27; VI-LABEL: test_fmin_legacy_uge_f64:28; VI: ; %bb.0:29; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2430; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v031; VI-NEXT: s_waitcnt lgkmcnt(0)32; VI-NEXT: v_mov_b32_e32 v1, s333; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v034; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc35; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]36; VI-NEXT: v_mov_b32_e32 v4, s037; VI-NEXT: v_mov_b32_e32 v5, s138; VI-NEXT: s_waitcnt vmcnt(0)39; VI-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[2:3]40; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc41; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc42; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]43; VI-NEXT: s_endpgm44 %tid = call i32 @llvm.amdgcn.workitem.id.x() #145 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid46 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 147 48 %a = load double, ptr addrspace(1) %gep.0, align 849 %b = load double, ptr addrspace(1) %gep.1, align 850 51 %cmp = fcmp uge double %a, %b52 %val = select i1 %cmp, double %b, double %a53 store double %val, ptr addrspace(1) %out, align 854 ret void55}56 57define amdgpu_kernel void @test_fmin_legacy_ugt_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {58; SI-LABEL: test_fmin_legacy_ugt_f64:59; SI: ; %bb.0:60; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x961; SI-NEXT: s_mov_b32 s7, 0xf00062; SI-NEXT: s_mov_b32 s10, 063; SI-NEXT: s_mov_b32 s11, s764; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v065; SI-NEXT: s_waitcnt lgkmcnt(0)66; SI-NEXT: s_mov_b64 s[8:9], s[2:3]67; SI-NEXT: v_mov_b32_e32 v1, 068; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr6469; SI-NEXT: s_mov_b32 s6, -170; SI-NEXT: s_mov_b32 s4, s071; SI-NEXT: s_mov_b32 s5, s172; SI-NEXT: s_waitcnt vmcnt(0)73; SI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]74; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc75; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc76; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 077; SI-NEXT: s_endpgm78;79; VI-LABEL: test_fmin_legacy_ugt_f64:80; VI: ; %bb.0:81; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2482; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v083; VI-NEXT: s_waitcnt lgkmcnt(0)84; VI-NEXT: v_mov_b32_e32 v1, s385; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v086; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc87; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]88; VI-NEXT: v_mov_b32_e32 v4, s089; VI-NEXT: v_mov_b32_e32 v5, s190; VI-NEXT: s_waitcnt vmcnt(0)91; VI-NEXT: v_cmp_nle_f64_e32 vcc, v[0:1], v[2:3]92; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc93; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc94; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]95; VI-NEXT: s_endpgm96 %tid = call i32 @llvm.amdgcn.workitem.id.x() #197 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid98 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 199 100 %a = load double, ptr addrspace(1) %gep.0, align 8101 %b = load double, ptr addrspace(1) %gep.1, align 8102 103 %cmp = fcmp ugt double %a, %b104 %val = select i1 %cmp, double %b, double %a105 store double %val, ptr addrspace(1) %out, align 8106 ret void107}108 109define amdgpu_kernel void @test_fmin_legacy_ule_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {110; SI-LABEL: test_fmin_legacy_ule_f64:111; SI: ; %bb.0:112; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9113; SI-NEXT: s_mov_b32 s7, 0xf000114; SI-NEXT: s_mov_b32 s10, 0115; SI-NEXT: s_mov_b32 s11, s7116; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0117; SI-NEXT: s_waitcnt lgkmcnt(0)118; SI-NEXT: s_mov_b64 s[8:9], s[2:3]119; SI-NEXT: v_mov_b32_e32 v1, 0120; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64121; SI-NEXT: s_mov_b32 s6, -1122; SI-NEXT: s_mov_b32 s4, s0123; SI-NEXT: s_mov_b32 s5, s1124; SI-NEXT: s_waitcnt vmcnt(0)125; SI-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[2:3]126; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc127; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc128; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0129; SI-NEXT: s_endpgm130;131; VI-LABEL: test_fmin_legacy_ule_f64:132; VI: ; %bb.0:133; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24134; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0135; VI-NEXT: s_waitcnt lgkmcnt(0)136; VI-NEXT: v_mov_b32_e32 v1, s3137; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0138; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc139; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]140; VI-NEXT: v_mov_b32_e32 v4, s0141; VI-NEXT: v_mov_b32_e32 v5, s1142; VI-NEXT: s_waitcnt vmcnt(0)143; VI-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[2:3]144; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc145; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc146; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]147; VI-NEXT: s_endpgm148 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1149 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid150 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1151 152 %a = load double, ptr addrspace(1) %gep.0, align 8153 %b = load double, ptr addrspace(1) %gep.1, align 8154 155 %cmp = fcmp ule double %a, %b156 %val = select i1 %cmp, double %a, double %b157 store double %val, ptr addrspace(1) %out, align 8158 ret void159}160 161define amdgpu_kernel void @test_fmin_legacy_ult_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {162; SI-LABEL: test_fmin_legacy_ult_f64:163; SI: ; %bb.0:164; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9165; SI-NEXT: s_mov_b32 s7, 0xf000166; SI-NEXT: s_mov_b32 s10, 0167; SI-NEXT: s_mov_b32 s11, s7168; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0169; SI-NEXT: s_waitcnt lgkmcnt(0)170; SI-NEXT: s_mov_b64 s[8:9], s[2:3]171; SI-NEXT: v_mov_b32_e32 v1, 0172; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64173; SI-NEXT: s_mov_b32 s6, -1174; SI-NEXT: s_mov_b32 s4, s0175; SI-NEXT: s_mov_b32 s5, s1176; SI-NEXT: s_waitcnt vmcnt(0)177; SI-NEXT: v_cmp_nge_f64_e32 vcc, v[0:1], v[2:3]178; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc179; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc180; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0181; SI-NEXT: s_endpgm182;183; VI-LABEL: test_fmin_legacy_ult_f64:184; VI: ; %bb.0:185; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24186; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0187; VI-NEXT: s_waitcnt lgkmcnt(0)188; VI-NEXT: v_mov_b32_e32 v1, s3189; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0190; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc191; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]192; VI-NEXT: v_mov_b32_e32 v4, s0193; VI-NEXT: v_mov_b32_e32 v5, s1194; VI-NEXT: s_waitcnt vmcnt(0)195; VI-NEXT: v_cmp_nge_f64_e32 vcc, v[0:1], v[2:3]196; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc197; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc198; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]199; VI-NEXT: s_endpgm200 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1201 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid202 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1203 204 %a = load double, ptr addrspace(1) %gep.0, align 8205 %b = load double, ptr addrspace(1) %gep.1, align 8206 207 %cmp = fcmp ult double %a, %b208 %val = select i1 %cmp, double %a, double %b209 store double %val, ptr addrspace(1) %out, align 8210 ret void211}212 213define amdgpu_kernel void @test_fmin_legacy_oge_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {214; SI-LABEL: test_fmin_legacy_oge_f64:215; SI: ; %bb.0:216; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9217; SI-NEXT: s_mov_b32 s7, 0xf000218; SI-NEXT: s_mov_b32 s10, 0219; SI-NEXT: s_mov_b32 s11, s7220; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0221; SI-NEXT: s_waitcnt lgkmcnt(0)222; SI-NEXT: s_mov_b64 s[8:9], s[2:3]223; SI-NEXT: v_mov_b32_e32 v1, 0224; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64225; SI-NEXT: s_mov_b32 s6, -1226; SI-NEXT: s_mov_b32 s4, s0227; SI-NEXT: s_mov_b32 s5, s1228; SI-NEXT: s_waitcnt vmcnt(0)229; SI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]230; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc231; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc232; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0233; SI-NEXT: s_endpgm234;235; VI-LABEL: test_fmin_legacy_oge_f64:236; VI: ; %bb.0:237; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24238; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0239; VI-NEXT: s_waitcnt lgkmcnt(0)240; VI-NEXT: v_mov_b32_e32 v1, s3241; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0242; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc243; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]244; VI-NEXT: v_mov_b32_e32 v4, s0245; VI-NEXT: v_mov_b32_e32 v5, s1246; VI-NEXT: s_waitcnt vmcnt(0)247; VI-NEXT: v_cmp_ge_f64_e32 vcc, v[0:1], v[2:3]248; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc249; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc250; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]251; VI-NEXT: s_endpgm252 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1253 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid254 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1255 256 %a = load double, ptr addrspace(1) %gep.0, align 8257 %b = load double, ptr addrspace(1) %gep.1, align 8258 259 %cmp = fcmp oge double %a, %b260 %val = select i1 %cmp, double %b, double %a261 store double %val, ptr addrspace(1) %out, align 8262 ret void263}264 265define amdgpu_kernel void @test_fmin_legacy_ogt_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {266; SI-LABEL: test_fmin_legacy_ogt_f64:267; SI: ; %bb.0:268; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9269; SI-NEXT: s_mov_b32 s7, 0xf000270; SI-NEXT: s_mov_b32 s10, 0271; SI-NEXT: s_mov_b32 s11, s7272; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0273; SI-NEXT: s_waitcnt lgkmcnt(0)274; SI-NEXT: s_mov_b64 s[8:9], s[2:3]275; SI-NEXT: v_mov_b32_e32 v1, 0276; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64277; SI-NEXT: s_mov_b32 s6, -1278; SI-NEXT: s_mov_b32 s4, s0279; SI-NEXT: s_mov_b32 s5, s1280; SI-NEXT: s_waitcnt vmcnt(0)281; SI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]282; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc283; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc284; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0285; SI-NEXT: s_endpgm286;287; VI-LABEL: test_fmin_legacy_ogt_f64:288; VI: ; %bb.0:289; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24290; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0291; VI-NEXT: s_waitcnt lgkmcnt(0)292; VI-NEXT: v_mov_b32_e32 v1, s3293; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0294; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc295; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]296; VI-NEXT: v_mov_b32_e32 v4, s0297; VI-NEXT: v_mov_b32_e32 v5, s1298; VI-NEXT: s_waitcnt vmcnt(0)299; VI-NEXT: v_cmp_gt_f64_e32 vcc, v[0:1], v[2:3]300; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc301; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc302; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]303; VI-NEXT: s_endpgm304 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1305 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid306 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1307 308 %a = load double, ptr addrspace(1) %gep.0, align 8309 %b = load double, ptr addrspace(1) %gep.1, align 8310 311 %cmp = fcmp ogt double %a, %b312 %val = select i1 %cmp, double %b, double %a313 store double %val, ptr addrspace(1) %out, align 8314 ret void315}316 317define amdgpu_kernel void @test_fmin_legacy_ole_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {318; SI-LABEL: test_fmin_legacy_ole_f64:319; SI: ; %bb.0:320; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9321; SI-NEXT: s_mov_b32 s7, 0xf000322; SI-NEXT: s_mov_b32 s10, 0323; SI-NEXT: s_mov_b32 s11, s7324; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0325; SI-NEXT: s_waitcnt lgkmcnt(0)326; SI-NEXT: s_mov_b64 s[8:9], s[2:3]327; SI-NEXT: v_mov_b32_e32 v1, 0328; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64329; SI-NEXT: s_mov_b32 s6, -1330; SI-NEXT: s_mov_b32 s4, s0331; SI-NEXT: s_mov_b32 s5, s1332; SI-NEXT: s_waitcnt vmcnt(0)333; SI-NEXT: v_cmp_le_f64_e32 vcc, v[0:1], v[2:3]334; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc335; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc336; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0337; SI-NEXT: s_endpgm338;339; VI-LABEL: test_fmin_legacy_ole_f64:340; VI: ; %bb.0:341; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24342; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0343; VI-NEXT: s_waitcnt lgkmcnt(0)344; VI-NEXT: v_mov_b32_e32 v1, s3345; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0346; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc347; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]348; VI-NEXT: v_mov_b32_e32 v4, s0349; VI-NEXT: v_mov_b32_e32 v5, s1350; VI-NEXT: s_waitcnt vmcnt(0)351; VI-NEXT: v_cmp_le_f64_e32 vcc, v[0:1], v[2:3]352; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc353; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc354; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]355; VI-NEXT: s_endpgm356 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1357 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid358 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1359 360 %a = load double, ptr addrspace(1) %gep.0, align 8361 %b = load double, ptr addrspace(1) %gep.1, align 8362 363 %cmp = fcmp ole double %a, %b364 %val = select i1 %cmp, double %a, double %b365 store double %val, ptr addrspace(1) %out, align 8366 ret void367}368 369define amdgpu_kernel void @test_fmin_legacy_olt_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {370; SI-LABEL: test_fmin_legacy_olt_f64:371; SI: ; %bb.0:372; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9373; SI-NEXT: s_mov_b32 s7, 0xf000374; SI-NEXT: s_mov_b32 s10, 0375; SI-NEXT: s_mov_b32 s11, s7376; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0377; SI-NEXT: s_waitcnt lgkmcnt(0)378; SI-NEXT: s_mov_b64 s[8:9], s[2:3]379; SI-NEXT: v_mov_b32_e32 v1, 0380; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64381; SI-NEXT: s_mov_b32 s6, -1382; SI-NEXT: s_mov_b32 s4, s0383; SI-NEXT: s_mov_b32 s5, s1384; SI-NEXT: s_waitcnt vmcnt(0)385; SI-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]386; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc387; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc388; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0389; SI-NEXT: s_endpgm390;391; VI-LABEL: test_fmin_legacy_olt_f64:392; VI: ; %bb.0:393; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24394; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0395; VI-NEXT: s_waitcnt lgkmcnt(0)396; VI-NEXT: v_mov_b32_e32 v1, s3397; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0398; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc399; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]400; VI-NEXT: v_mov_b32_e32 v4, s0401; VI-NEXT: v_mov_b32_e32 v5, s1402; VI-NEXT: s_waitcnt vmcnt(0)403; VI-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]404; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc405; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc406; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]407; VI-NEXT: s_endpgm408 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1409 %gep.0 = getelementptr double, ptr addrspace(1) %in, i32 %tid410 %gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1411 412 %a = load double, ptr addrspace(1) %gep.0, align 8413 %b = load double, ptr addrspace(1) %gep.1, align 8414 415 %cmp = fcmp olt double %a, %b416 %val = select i1 %cmp, double %a, double %b417 store double %val, ptr addrspace(1) %out, align 8418 ret void419}420 421declare i32 @llvm.amdgcn.workitem.id.x() #1422 423attributes #0 = { nounwind }424attributes #1 = { nounwind readnone }425