443 lines · plain
1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI,GCN,FUNC %s2 3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,FUNC %s4 5; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope --check-prefixes=EG,FUNC %s6 7declare i32 @llvm.amdgcn.workitem.id.x() #18 9; The two inputs to the instruction are different SGPRs from the same10; super register, so we can't fold both SGPR operands even though they11; are both the same register.12 13; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32:14; EG: MIN *15; SI: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}16 17; VI: v_cmp_nlt_f32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}18define amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32(ptr addrspace(1) %out, <4 x float> %reg0) #0 {19 %r0 = extractelement <4 x float> %reg0, i32 020 %r1 = extractelement <4 x float> %reg0, i32 121 %r2 = fcmp uge float %r0, %r122 %r3 = select i1 %r2, float %r1, float %r023 store float %r3, ptr addrspace(1) %out24 ret void25}26 27; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32_fast:28 29; SI: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}30 31; VI: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}32define amdgpu_kernel void @s_test_fmin_legacy_subreg_inputs_f32_fast(ptr addrspace(1) %out, <4 x float> %reg0) #0 {33 %r0 = extractelement <4 x float> %reg0, i32 034 %r1 = extractelement <4 x float> %reg0, i32 135 %r2 = fcmp nnan nsz uge float %r0, %r136 %r3 = select nnan nsz i1 %r2, float %r1, float %r037 store float %r3, ptr addrspace(1) %out38 ret void39}40 41; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32:42; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}43 44; SI: v_mov_b32_e32 [[VA:v[0-9]+]], s[[#LOAD + 2]]45 46; VI: v_mov_b32_e32 [[VB:v[0-9]+]], s[[#LOAD + 3]]47 48; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, s[[#LOAD + 3]], [[VA]]49 50; VI: v_mov_b32_e32 [[VA:v[0-9]+]], s[[#LOAD + 2]]51; VI: v_cmp_ngt_f32_e32 vcc, s[[#LOAD + 2]], [[VB]]52; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[VB]], [[VA]]53define amdgpu_kernel void @s_test_fmin_legacy_ule_f32(ptr addrspace(1) %out, float %a, float %b) #0 {54 %cmp = fcmp ule float %a, %b55 %val = select i1 %cmp, float %a, float %b56 store float %val, ptr addrspace(1) %out, align 457 ret void58}59 60; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32_fast:61; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}62 63; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[#LOAD + 3]]64 65; GCN: v_min_f32_e32 {{v[0-9]+}}, s[[#LOAD + 2]], [[VB]]66define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_fast(ptr addrspace(1) %out, float %a, float %b) #0 {67 %cmp = fcmp ule float %a, %b68 %val = select nnan nsz i1 %cmp, float %a, float %b69 store float %val, ptr addrspace(1) %out, align 470 ret void71}72 73; Nsz also needed74; FIXME: Should separate tests75; GCN-LABEL: {{^}}s_test_fmin_legacy_ule_f32_nnan_src:76; GCN: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}77 78; SI: s_mov_b64 s[[[#COPY:]]:{{[0-9]+}}], s{{\[}}[[#LOAD + 2]]:[[#LOAD + 3]]{{\]}}79; SI-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#COPY]], 1.080; SI-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#COPY + 1]], 2.081 82; VI-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#LOAD + 2]], 1.083; VI-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#LOAD + 3]], 2.084; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]85 86; VI: v_cmp_ngt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]87; VI: v_cndmask_b32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]], vcc88define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src(ptr addrspace(1) %out, float %a, float %b) #0 {89 %a.nnan = fadd nnan float %a, 1.090 %b.nnan = fadd nnan float %b, 2.091 %cmp = fcmp ule float %a.nnan, %b.nnan92 %val = select i1 %cmp, float %a.nnan, float %b.nnan93 store float %val, ptr addrspace(1) %out, align 494 ret void95}96 97; Nsz also needed98; FIXME: Should separate tests99; GCN-LABEL: {{^}}s_test_fmin_legacy_ule_f32_nnan_src_fast:100; GCN: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}101 102; SI: s_mov_b64 s[[[#COPY:]]:{{[0-9]+}}], s{{\[}}[[#LOAD + 2]]:[[#LOAD + 3]]{{\]}}103; SI-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#COPY]], 1.0104; SI-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#COPY + 1]], 2.0105 106; VI-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#LOAD + 2]], 1.0107; VI-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#LOAD + 3]], 2.0108 109; GCN: v_min_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]110define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src_fast(ptr addrspace(1) %out, float %a, float %b) #0 {111 %a.nnan = fadd nnan float %a, 1.0112 %b.nnan = fadd nnan float %b, 2.0113 %cmp = fcmp ule float %a.nnan, %b.nnan114 %val = select nnan nsz i1 %cmp, float %a.nnan, float %b.nnan115 store float %val, ptr addrspace(1) %out, align 4116 ret void117}118 119; FUNC-LABEL: {{^}}test_fmin_legacy_ule_f32:120; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]121; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]122 123; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]124 125; VI: v_cmp_ngt_f32_e32 vcc, [[A]], [[B]]126; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]127define amdgpu_kernel void @test_fmin_legacy_ule_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {128 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1129 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid130 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1131 132 %a = load volatile float, ptr addrspace(1) %gep.0, align 4133 %b = load volatile float, ptr addrspace(1) %gep.1, align 4134 135 %cmp = fcmp ule float %a, %b136 %val = select i1 %cmp, float %a, float %b137 store float %val, ptr addrspace(1) %out, align 4138 ret void139}140 141; FUNC-LABEL: {{^}}test_fmin_legacy_ule_f32_fast:142; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]143; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]144 145; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]146define amdgpu_kernel void @test_fmin_legacy_ule_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {147 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1148 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid149 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1150 151 %a = load volatile float, ptr addrspace(1) %gep.0, align 4152 %b = load volatile float, ptr addrspace(1) %gep.1, align 4153 154 %cmp = fcmp ule float %a, %b155 %val = select nnan nsz i1 %cmp, float %a, float %b156 store float %val, ptr addrspace(1) %out, align 4157 ret void158}159 160; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32:161; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]162; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]163 164; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]165 166; VI: v_cmp_le_f32_e32 vcc, [[A]], [[B]]167; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]168define amdgpu_kernel void @test_fmin_legacy_ole_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {169 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1170 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid171 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1172 173 %a = load volatile float, ptr addrspace(1) %gep.0, align 4174 %b = load volatile float, ptr addrspace(1) %gep.1, align 4175 176 %cmp = fcmp ole float %a, %b177 %val = select i1 %cmp, float %a, float %b178 store float %val, ptr addrspace(1) %out, align 4179 ret void180}181 182; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32_fast:183; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]184; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]185 186; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]187define amdgpu_kernel void @test_fmin_legacy_ole_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {188 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1189 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid190 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1191 192 %a = load volatile float, ptr addrspace(1) %gep.0, align 4193 %b = load volatile float, ptr addrspace(1) %gep.1, align 4194 195 %cmp = fcmp ole float %a, %b196 %val = select nnan nsz i1 %cmp, float %a, float %b197 store float %val, ptr addrspace(1) %out, align 4198 ret void199}200 201; FUNC-LABEL: {{^}}test_fmin_legacy_olt_f32:202; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]203; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]204 205; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[A]], [[B]]206 207; VI: v_cmp_lt_f32_e32 vcc, [[A]], [[B]]208; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]209define amdgpu_kernel void @test_fmin_legacy_olt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {210 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1211 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid212 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1213 214 %a = load volatile float, ptr addrspace(1) %gep.0, align 4215 %b = load volatile float, ptr addrspace(1) %gep.1, align 4216 217 %cmp = fcmp olt float %a, %b218 %val = select i1 %cmp, float %a, float %b219 store float %val, ptr addrspace(1) %out, align 4220 ret void221}222 223; FUNC-LABEL: {{^}}test_fmin_legacy_olt_f32_fast:224; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]225; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]226 227; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]228define amdgpu_kernel void @test_fmin_legacy_olt_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {229 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1230 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid231 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1232 233 %a = load volatile float, ptr addrspace(1) %gep.0, align 4234 %b = load volatile float, ptr addrspace(1) %gep.1, align 4235 236 %cmp = fcmp olt float %a, %b237 %val = select nnan nsz i1 %cmp, float %a, float %b238 store float %val, ptr addrspace(1) %out, align 4239 ret void240}241 242; FUNC-LABEL: {{^}}test_fmin_legacy_ult_f32:243; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]244; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]245 246; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]247 248; VI: v_cmp_nge_f32_e32 vcc, [[A]], [[B]]249; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]250define amdgpu_kernel void @test_fmin_legacy_ult_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {251 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1252 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid253 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1254 255 %a = load volatile float, ptr addrspace(1) %gep.0, align 4256 %b = load volatile float, ptr addrspace(1) %gep.1, align 4257 258 %cmp = fcmp ult float %a, %b259 %val = select i1 %cmp, float %a, float %b260 store float %val, ptr addrspace(1) %out, align 4261 ret void262}263 264; FUNC-LABEL: {{^}}test_fmin_legacy_ult_f32_fast:265; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]266; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]267 268; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]269define amdgpu_kernel void @test_fmin_legacy_ult_f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {270 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1271 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid272 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1273 274 %a = load volatile float, ptr addrspace(1) %gep.0, align 4275 %b = load volatile float, ptr addrspace(1) %gep.1, align 4276 277 %cmp = fcmp ult float %a, %b278 %val = select nnan nsz i1 %cmp, float %a, float %b279 store float %val, ptr addrspace(1) %out, align 4280 ret void281}282 283; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v1f32:284; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]285; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]286 287; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[A]]288 289; VI: v_cmp_nge_f32_e32 vcc, [[A]], [[B]]290; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]291define amdgpu_kernel void @test_fmin_legacy_ult_v1f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {292 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1293 %gep.0 = getelementptr <1 x float>, ptr addrspace(1) %in, i32 %tid294 %gep.1 = getelementptr <1 x float>, ptr addrspace(1) %gep.0, i32 1295 296 %a = load volatile <1 x float>, ptr addrspace(1) %gep.0297 %b = load volatile <1 x float>, ptr addrspace(1) %gep.1298 299 %cmp = fcmp ult <1 x float> %a, %b300 %val = select <1 x i1> %cmp, <1 x float> %a, <1 x float> %b301 store <1 x float> %val, ptr addrspace(1) %out302 ret void303}304 305; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v1f32_fast:306; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]307; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]308 309; GCN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[B]]310define amdgpu_kernel void @test_fmin_legacy_ult_v1f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {311 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1312 %gep.0 = getelementptr <1 x float>, ptr addrspace(1) %in, i32 %tid313 %gep.1 = getelementptr <1 x float>, ptr addrspace(1) %gep.0, i32 1314 315 %a = load volatile <1 x float>, ptr addrspace(1) %gep.0316 %b = load volatile <1 x float>, ptr addrspace(1) %gep.1317 318 %cmp = fcmp ult <1 x float> %a, %b319 %val = select nnan nsz <1 x i1> %cmp, <1 x float> %a, <1 x float> %b320 store <1 x float> %val, ptr addrspace(1) %out321 ret void322}323 324; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v2f32:325; GCN: {{buffer|flat}}_load_dwordx2326; GCN: {{buffer|flat}}_load_dwordx2327; SI: v_min_legacy_f32_e32328; SI: v_min_legacy_f32_e32329 330; VI: v_cmp_nge_f32_e32331; VI: v_cndmask_b32_e32332; VI: v_cmp_nge_f32_e32333; VI: v_cndmask_b32_e32334define amdgpu_kernel void @test_fmin_legacy_ult_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {335 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1336 %gep.0 = getelementptr <2 x float>, ptr addrspace(1) %in, i32 %tid337 %gep.1 = getelementptr <2 x float>, ptr addrspace(1) %gep.0, i32 1338 339 %a = load volatile <2 x float>, ptr addrspace(1) %gep.0340 %b = load volatile <2 x float>, ptr addrspace(1) %gep.1341 342 %cmp = fcmp ult <2 x float> %a, %b343 %val = select <2 x i1> %cmp, <2 x float> %a, <2 x float> %b344 store <2 x float> %val, ptr addrspace(1) %out345 ret void346}347 348; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v2f32_fast:349; GCN: {{buffer|flat}}_load_dwordx2350; GCN: {{buffer|flat}}_load_dwordx2351 352; GCN: v_min_f32_e32353; GCN: v_min_f32_e32354define amdgpu_kernel void @test_fmin_legacy_ult_v2f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {355 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1356 %gep.0 = getelementptr <2 x float>, ptr addrspace(1) %in, i32 %tid357 %gep.1 = getelementptr <2 x float>, ptr addrspace(1) %gep.0, i32 1358 359 %a = load volatile <2 x float>, ptr addrspace(1) %gep.0360 %b = load volatile <2 x float>, ptr addrspace(1) %gep.1361 362 %cmp = fcmp ult <2 x float> %a, %b363 %val = select nnan nsz <2 x i1> %cmp, <2 x float> %a, <2 x float> %b364 store <2 x float> %val, ptr addrspace(1) %out365 ret void366}367 368; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v3f32:369; SI: v_min_legacy_f32_e32370; SI: v_min_legacy_f32_e32371; SI: v_min_legacy_f32_e32372; SI-NOT: v_min_373 374; VI: v_cmp_nge_f32_e32375; VI: v_cndmask_b32_e32376; VI: v_cmp_nge_f32_e32377; VI: v_cndmask_b32_e32378; VI: v_cmp_nge_f32_e32379; VI: v_cndmask_b32_e32380; VI-NOT: v_cmp381; VI-NOT: v_cndmask382define amdgpu_kernel void @test_fmin_legacy_ult_v3f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {383 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1384 %gep.0 = getelementptr <3 x float>, ptr addrspace(1) %in, i32 %tid385 %gep.1 = getelementptr <3 x float>, ptr addrspace(1) %gep.0, i32 1386 387 %a = load <3 x float>, ptr addrspace(1) %gep.0388 %b = load <3 x float>, ptr addrspace(1) %gep.1389 390 %cmp = fcmp ult <3 x float> %a, %b391 %val = select <3 x i1> %cmp, <3 x float> %a, <3 x float> %b392 store <3 x float> %val, ptr addrspace(1) %out393 ret void394}395 396; FUNC-LABEL: {{^}}test_fmin_legacy_ult_v3f32_fast:397; VI-NOT: v_cmp398; VI-NOT: v_cndmask399 400; GCN: v_min_f32_e32401; GCN: v_min_f32_e32402; GCN: v_min_f32_e32403; GCN-NOT: v_min_404define amdgpu_kernel void @test_fmin_legacy_ult_v3f32_fast(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {405 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1406 %gep.0 = getelementptr <3 x float>, ptr addrspace(1) %in, i32 %tid407 %gep.1 = getelementptr <3 x float>, ptr addrspace(1) %gep.0, i32 1408 409 %a = load <3 x float>, ptr addrspace(1) %gep.0410 %b = load <3 x float>, ptr addrspace(1) %gep.1411 412 %cmp = fcmp ult <3 x float> %a, %b413 %val = select nnan nsz <3 x i1> %cmp, <3 x float> %a, <3 x float> %b414 store <3 x float> %val, ptr addrspace(1) %out415 ret void416}417 418; FUNC-LABEL: {{^}}test_fmin_legacy_ole_f32_multi_use:419; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]420; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]421; GCN-NOT: v_min422; GCN: v_cmp_le_f32423; GCN-NEXT: v_cndmask_b32424; GCN-NOT: v_min425; GCN: s_endpgm426define amdgpu_kernel void @test_fmin_legacy_ole_f32_multi_use(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %in) #0 {427 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1428 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid429 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1430 431 %a = load volatile float, ptr addrspace(1) %gep.0, align 4432 %b = load volatile float, ptr addrspace(1) %gep.1, align 4433 434 %cmp = fcmp ole float %a, %b435 %val0 = select i1 %cmp, float %a, float %b436 store float %val0, ptr addrspace(1) %out0, align 4437 store i1 %cmp, ptr addrspace(1) %out1438 ret void439}440 441attributes #0 = { nounwind }442attributes #1 = { nounwind readnone }443