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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4; GCN-LABEL: {{^}}test_fmin_f32_ieee_mode_on:5; GCN: v_mul_f32_e64 [[QUIET0:v[0-9]+]], 1.0, s{{[0-9]+}}6; GCN: v_mul_f32_e64 [[QUIET1:v[0-9]+]], 1.0, s{{[0-9]+}}7; GCN: v_min_f32_e32 [[RESULT:v[0-9]+]], [[QUIET1]], [[QUIET0]]8; GCN-NOT: [[RESULT]]9; GCN: buffer_store_dword [[RESULT]]10define amdgpu_kernel void @test_fmin_f32_ieee_mode_on(ptr addrspace(1) %out, float %a, float %b) #0 {11 %val = call float @llvm.minnum.f32(float %a, float %b) #112 store float %val, ptr addrspace(1) %out, align 413 ret void14}15 16; GCN-LABEL: {{^}}test_fmin_nnan_f32_ieee_mode_on:17; GCN: s_waitcnt18; GCN-NEXT: v_min_f32_e32 v0, v0, v119; GCN-NEXT: s_setpc_b6420define float @test_fmin_nnan_f32_ieee_mode_on(float %a, float %b) #0 {21 %val = call nnan float @llvm.minnum.f32(float %a, float %b) #122 ret float %val23}24 25; GCN-LABEL: {{^}}test_fmin_nnan_f32_ieee_mode_off:26; GCN-NOT: v027; GCN-NOT: v128; GCN: v_min_f32_e32 v0, v0, v129; GCN-NEXT: ; return30define amdgpu_ps float @test_fmin_nnan_f32_ieee_mode_off(float %a, float %b) #0 {31 %val = call nnan float @llvm.minnum.f32(float %a, float %b) #132 ret float %val33}34 35; GCN-LABEL: {{^}}test_fmin_f32_ieee_mode_off:36; GCN: v_min_f32_e32 v0, v0, v137; GCN-NEXT: ; return38define amdgpu_ps float @test_fmin_f32_ieee_mode_off(float %a, float %b) #0 {39 %val = call float @llvm.minnum.f32(float %a, float %b) #140 ret float %val41}42 43; GCN-LABEL: {{^}}test_fmin_v2f32:44; GCN: v_min_f32_e3245; GCN: v_min_f32_e3246define amdgpu_kernel void @test_fmin_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {47 %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b)48 store <2 x float> %val, ptr addrspace(1) %out, align 849 ret void50}51 52; GCN-LABEL: {{^}}test_fmin_v4f32:53; GCN: v_min_f32_e3254; GCN: v_min_f32_e3255; GCN: v_min_f32_e3256; GCN: v_min_f32_e3257define amdgpu_kernel void @test_fmin_v4f32(ptr addrspace(1) %out, <4 x float> %a, <4 x float> %b) #0 {58 %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)59 store <4 x float> %val, ptr addrspace(1) %out, align 1660 ret void61}62 63; GCN-LABEL: {{^}}test_fmin_v8f32:64; GCN: v_min_f32_e3265; GCN: v_min_f32_e3266; GCN: v_min_f32_e3267; GCN: v_min_f32_e3268; GCN: v_min_f32_e3269; GCN: v_min_f32_e3270; GCN: v_min_f32_e3271; GCN: v_min_f32_e3272define amdgpu_kernel void @test_fmin_v8f32(ptr addrspace(1) %out, <8 x float> %a, <8 x float> %b) #0 {73 %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b)74 store <8 x float> %val, ptr addrspace(1) %out, align 3275 ret void76}77 78; GCN-LABEL: {{^}}test_fmin_v16f32:79; GCN: v_min_f32_e3280; GCN: v_min_f32_e3281; GCN: v_min_f32_e3282; GCN: v_min_f32_e3283; GCN: v_min_f32_e3284; GCN: v_min_f32_e3285; GCN: v_min_f32_e3286; GCN: v_min_f32_e3287; GCN: v_min_f32_e3288; GCN: v_min_f32_e3289; GCN: v_min_f32_e3290; GCN: v_min_f32_e3291; GCN: v_min_f32_e3292; GCN: v_min_f32_e3293; GCN: v_min_f32_e3294; GCN: v_min_f32_e3295define amdgpu_kernel void @test_fmin_v16f32(ptr addrspace(1) %out, <16 x float> %a, <16 x float> %b) #0 {96 %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b)97 store <16 x float> %val, ptr addrspace(1) %out, align 6498 ret void99}100 101; GCN-LABEL: {{^}}constant_fold_fmin_f32:102; GCN-NOT: v_min_f32_e32103; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0104; GCN: buffer_store_dword [[REG]]105define amdgpu_kernel void @constant_fold_fmin_f32(ptr addrspace(1) %out) #0 {106 %val = call float @llvm.minnum.f32(float 1.0, float 2.0)107 store float %val, ptr addrspace(1) %out, align 4108 ret void109}110 111; GCN-LABEL: {{^}}constant_fold_fmin_f32_nan_nan:112; GCN-NOT: v_min_f32_e32113; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000114; GCN: buffer_store_dword [[REG]]115define amdgpu_kernel void @constant_fold_fmin_f32_nan_nan(ptr addrspace(1) %out) #0 {116 %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)117 store float %val, ptr addrspace(1) %out, align 4118 ret void119}120 121; GCN-LABEL: {{^}}constant_fold_fmin_f32_val_nan:122; GCN-NOT: v_min_f32_e32123; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0124; GCN: buffer_store_dword [[REG]]125define amdgpu_kernel void @constant_fold_fmin_f32_val_nan(ptr addrspace(1) %out) #0 {126 %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000)127 store float %val, ptr addrspace(1) %out, align 4128 ret void129}130 131; GCN-LABEL: {{^}}constant_fold_fmin_f32_nan_val:132; GCN-NOT: v_min_f32_e32133; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0134; GCN: buffer_store_dword [[REG]]135define amdgpu_kernel void @constant_fold_fmin_f32_nan_val(ptr addrspace(1) %out) #0 {136 %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0)137 store float %val, ptr addrspace(1) %out, align 4138 ret void139}140 141; GCN-LABEL: {{^}}constant_fold_fmin_f32_p0_p0:142; GCN-NOT: v_min_f32_e32143; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0144; GCN: buffer_store_dword [[REG]]145define amdgpu_kernel void @constant_fold_fmin_f32_p0_p0(ptr addrspace(1) %out) #0 {146 %val = call float @llvm.minnum.f32(float 0.0, float 0.0)147 store float %val, ptr addrspace(1) %out, align 4148 ret void149}150 151; GCN-LABEL: {{^}}constant_fold_fmin_f32_p0_n0:152; GCN-NOT: v_min_f32_e32153; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}154; GCN: buffer_store_dword [[REG]]155define amdgpu_kernel void @constant_fold_fmin_f32_p0_n0(ptr addrspace(1) %out) #0 {156 %val = call float @llvm.minnum.f32(float 0.0, float -0.0)157 store float %val, ptr addrspace(1) %out, align 4158 ret void159}160 161; GCN-LABEL: {{^}}constant_fold_fmin_f32_n0_p0:162; GCN-NOT: v_min_f32_e32163; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}164; GCN: buffer_store_dword [[REG]]165define amdgpu_kernel void @constant_fold_fmin_f32_n0_p0(ptr addrspace(1) %out) #0 {166 %val = call float @llvm.minnum.f32(float -0.0, float 0.0)167 store float %val, ptr addrspace(1) %out, align 4168 ret void169}170 171; GCN-LABEL: {{^}}constant_fold_fmin_f32_n0_n0:172; GCN-NOT: v_min_f32_e32173; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}174; GCN: buffer_store_dword [[REG]]175define amdgpu_kernel void @constant_fold_fmin_f32_n0_n0(ptr addrspace(1) %out) #0 {176 %val = call float @llvm.minnum.f32(float -0.0, float -0.0)177 store float %val, ptr addrspace(1) %out, align 4178 ret void179}180 181; GCN-LABEL: {{^}}fmin_var_immediate_f32_no_ieee:182; GCN: v_min_f32_e32 v0, 2.0, v0183define amdgpu_ps float @fmin_var_immediate_f32_no_ieee(float %a) #0 {184 %val = call float @llvm.minnum.f32(float %a, float 2.0) #1185 ret float %val186}187 188; GCN-LABEL: {{^}}fmin_immediate_var_f32_no_ieee:189; GCN: v_min_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0190define amdgpu_ps float @fmin_immediate_var_f32_no_ieee(float inreg %a) #0 {191 %val = call float @llvm.minnum.f32(float 2.0, float %a) #1192 ret float %val193}194 195; GCN-LABEL: {{^}}fmin_var_literal_f32_no_ieee:196; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000197; GCN: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]198define amdgpu_ps float @fmin_var_literal_f32_no_ieee(float inreg %a) #0 {199 %val = call float @llvm.minnum.f32(float %a, float 99.0) #1200 ret float %val201}202 203; GCN-LABEL: {{^}}fmin_literal_var_f32_no_ieee:204; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000205; GCN: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]206define amdgpu_ps float @fmin_literal_var_f32_no_ieee(float inreg %a) #0 {207 %val = call float @llvm.minnum.f32(float 99.0, float %a) #1208 ret float %val209}210 211; GCN-LABEL: {{^}}test_func_fmin_v3f32:212; GCN: v_min_f32_e32213; GCN: v_min_f32_e32214; GCN: v_min_f32_e32215; GCN-NOT: v_min_f32216define <3 x float> @test_func_fmin_v3f32(<3 x float> %a, <3 x float> %b) nounwind {217 %val = call <3 x float> @llvm.minnum.v3f32(<3 x float> %a, <3 x float> %b) #0218 ret <3 x float> %val219}220 221declare float @llvm.minnum.f32(float, float) #1222declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #1223declare <3 x float> @llvm.minnum.v3f32(<3 x float>, <3 x float>) #1224declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1225declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #1226declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #1227 228attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }229attributes #1 = { nounwind readnone }230